Unit I

1. Briefly explain the steps involved in conventional electronic circuit

2 Describe the following levels of design description Circuit level, Gate level, Data flow,
Behavioral level.
3 Describe the physical design in a ASIC design flow
4 Explain the structure of a typical simulation module
5 What is the need for synthesis? Briefly discuss the two common approaches for hardware
realization
6 Discuss different levels of design description in Verilog with suitable examples.
7 Discuss the different driving strengths in Verilog with strength level
8 Write the structure of typical simulation module and explain.
9 Explain Language Constructs and conventions in verilog with an examples
Unit II
1 With instantiation, functional representation and functional explain tri-state buffer primitives.
2 Write Verilog module for 8-bit comparator with test bench.
3 Explain in detail net, gate and tri-state delays with examples

Unit III
1 Design a module of an up-down counter and a test bench
2 With an example explain how the INITIAL construct used in Verilog
3 Explain how the ALWAYS statements are used in Verilog
4 Design a counter module and test bench to illustrate the use of WAIT
Unit IV
1 Explain with example how assign and net declarations can be combined
2 Write the operator precedence for unary, binary and ternary operators
3 Draw the basic functional unit of a dynamic shift register
4 Differentiate between regular and resistive switches in Verilog.
Unit V
1 Illustrate the differences between *> and => operators

2 Why specparam construct is used in specify block Explain. Also compare specparam and
parameter.
3 Explain recursive function with example- 6M
4 Briefly explain combinational and sequential UDPs in Verilog. write Verilog module for D
latch using UDP.

Another Important questions

1. Explain concatenation of vectors.
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Design a verilog module to 8 bit adder at data

Explain clocked RS Flip-flop verilog module and Test Bench?
Write about dierent scalars and vectors in verilog module, with examples.
Explain NMOS enhancement with conditions.
Write about Basic switch primitives
Design verilog code of OR gate using for and disable.
Write simulation results of above question with explanation.
Design a Master Slave JK flip flop using NAND gates.
Write Short Notes for following with Examples:
(a) Intra Assignment Delays
(b) Delay Assignments

(c) Zero Delay

10. Design CMOS switch with a single control line.
11. Design code, testbench, results for CMOS switch with a single control line.
12. Design verilog module using of path delay.