Implementation of First and Third Order

Fractional Order Differentiators and Integrators

using Switched Capacitors
Pragya Varshney, Member, IEEE, Maneesha Gupta, and G. S. Visweswaran

Abstract-- This paper proposes first-order and third-order

Switched Capacitor
realizations
of
fractional
order
differentiators and integrators. First, the s-to-z transformation is
expanded for fractional powers using Taylor series expansion
(TSE) and continued fraction expansion (CFE). Then, the
stabilized models of the fractional order differentiators and
integrators are realized using Switched capacitor (SC) circuits
and implemented using OrCAD Pspice. The simulation results
obtained using Pspice matched with their corresponding
MATLAB simulation results and are in close conformity with the
theoretical results of the continuous-time (c-t) counter parts. The
fractional order of the differentiator or integrator helps in
enhancing the system control performance better than the
conventional order systems. The major purpose of this paper is to
emphasize that the mixed mode realizations of fractional order
differentiators and integrators using SC technique allow
integration of both digital and analog functions on a single chip,
and can be used in various control applications.
Index Terms--Switched Capacitor circuits, fractional order
differentiator (FOD), fractional order integrator (FOI), AlAlaoui operator, Schneider operator, Al-SKG rule and Hsue
operator.

suggested by Fried [1]. In [2], Hosticka et al. suggested that

the resistor in a Miller Integrator could be replaced by a
capacitor and two switches. In [3], Caves et al. have
developed parallel and series switched capacitor resistor
realizations. In the late seventies and early eighties, extensive
work on design of MOS switched capacitor ladder filters has
been done [4-11]. In the thesis of Gupta [12], a different
approach for the design of switched capacitor ladder filters is
proposed and analyzed. The z-domain transfer functions of the
ladder filters are expanded using continued fraction expansion
(CFE) into mixed Cauer forms by Mitra et al. [13]. Then, each
row of the expansion is implemented using parasitic
insensitive SC realizations of integrators and amplifiers.
One of the SC realizations of a continuous resistor is shown
in Fig 1. This configuration is called parallel SC equivalent
resistor. It consists of two independent voltage sources, v1(t)
and v2(t), two controlled switches, s1 and s2, and a capacitor C.
The switches, s1 and s2, are controlled by two non-overlapping
clock waveforms e and o shown in Fig 3. If the clock
period is TC then resistance is given by
TC
1 1
(1)
=

C
fC C
where fC is the clock frequency. Equation (1) shows that the
parallel SC circuit realization of Fig 1 is equivalent to a
resistor (Fig 2). If the clock frequency is much larger than the
frequency of the inputs v1 and v2, we can consider the inputs to
be constant over the time period T and the emulated resistance
can be used in place of a normal resistor.
R=

I. INTRODUCTION

N switched capacitor circuits, the function resistors are

realized using MOS switches and capacitors. The advantage
of using Switched Capacitor (SC) circuits is that the accuracy
of the signal-processing function is proportional to the
accuracy of capacitor ratios. The other advantages of SC
circuits include compatibility with CMOS technology; good
accuracy of time constant; programmability; good voltage
linearity; flexibility; good temperature characteristics, better
accuracy and stability and ease of fabrication.
The idea of implementing a simple RC filter using
capacitors, MOSFETS and a pulse generator was first
Dr. Pragya Varshney is Assistant Professor in ICE Deptt. at NSIT, New
Delhi, 110078 India. Ph- +919810063924, email: pragyava@rediffmail.com
Dr. Maneesha Gupta is Associate Professor, in ECE Deptt. at NSIT, New
Delhi, 110078 India. (email: maneeshapub@gmail.com).
Dr. G. S. Visweswaran is Professor, in EE Deptt. at IIT, New Delhi,
110016 India. (email: gswaran@ee.iitd.ac.in).

978-1-4244-7882-8/11/$26.00 2011 IEEE

i1(t)

S1
v1(t)

i2(t)

i1(t)

i2(t)

S2
+

vC(t)

v2(t)

Fig 1 Parallel SC equivalent

resistor

v1(t)

Fig 2

v2(t)

Continuous-time resistor R

The realization of Fig. 1 is sensitive to parasitic

capacitances and hence for all practical purposes parasitic
insensitive realizations are used. Some of the parasitic
insensitive realizations are given in Table I.

TABLE I
BASIC SWITCHED CAPACITOR BLOCKS AND Z-DOMAIN EXPRESSIONS

II. CONTINUED FRACTION EXPANSION

The continued fraction expansion of a digital transfer
function of (2) of order n is given in (3). These expansions are
based on mixed Cauer form involving the terms (Ap+Bpz) and /
or (Ap+Bpz-1) or both:

()

G z =
n

n
n1
+ " + a0
an z + an1z
n
n1
+ " + b0
bn z + bn1z

G ( z ) = A G' ( z )
n
0 n

(2)

or G ( z ) = A / G' ( z )
n
0 n

(3)
where A0=(an/bn) is a constant; gp(z)=(ApBpz) or (ApBpz-1)
p=1,2,,n; ais, bis are the coefficients of numerator and
denominator polynomials for i=0,1,,n; and Ap and Bp are
coefficients of the expansion.
Each row of the function of (3) can be represented by any
one of the following recursive relationship of (4).
G

or
Usually real-world physical systems are described by
fractional order differential equations. Most of the researchers
have developed analog realizations of fractional order circuits.
In [14]-[16], the authors have developed analogue realizations
of s-domain fractional order controllers using ideal resistance
and capacitor networks. Since ideal capacitor cannot exist,
Bohannan in [17] has proposed a fractional order control
element using a lossy capacitor with Lithium Hydrazinium
Sulphate (LiN2H5SO4) as dielectric. In [18], Krishna et al.
have made an attempt to realize the half differentiator and half
integrator in s-domain using continued fraction expansion.
Digital realizations of fractional order controller have been
developed in [19-23].
In this paper, SC realizations of the fractional-order
differentiators and integrators [24-30] of order based on AlAlaoui operator, Tustin operator, Schneider operator, AlAlaoui-SKG rule and the Hsue operator have been developed.
OrCAD Pspice simulation results have been presented to
validate the effectiveness of the proposed approach.
The paper is organized as follows: Section II discusses
briefly about continued fraction expansion technique. In
Section III, the continued fraction expansions of the various
operator based half differentiator and half integrator models
are given. Section IV shows the first-order and third-order SC
realizations of half differentiators and half integrators. Section
V presents the OrCAD Pspice simulation results and compares
them with the theoretical results of their continuous-time
counterparts. Section VI concludes the paper.

j,p (

z) =

1
Ap + Bpz + G
z
m,p+1 ( )

(4)

where j=0,1,,(n-1) and m=j+1.

Equation (4) represents transfer functions of leaky inverting
and non-inverting integrators, which are realizable using SC
integrators. The constant term represents gain or attenuation,
and is realized using SC amplifier. The SC circuit for the half
differentiator and half integrator are then obtained by
connecting the different blocks of integrator and differentiator
in ladder form.
III. CONTINUED FRACTION EXPANSIONS OF THE DIFFERENT
OPERATOR BASED HALF DIFFERENTIATOR AND HALF
INTEGRATOR MODELS
In this section, the continued fraction expansions of
fractional-order differentiator and integrator models of order
obtained by discretizations of Al-Alaoui operator [33], Tustin
operator [33], Schneider operator, Al-Alaoui-SKG rule and
Hsue operator have been developed as suggested in Section II
and listed in Table IIA and IIB.
Some expansions which have poor realizability have not
been reported in the tables.
IV. SWITCHED CAPACITOR REALIZATIONS OF HALF
DIFFERENTIATORS AND HALF INTEGRATORS
The basic building blocks of Switched capacitor circuits are
the SC amplifier / attenuator and the SC integrator [34]. Figs.
4, 5 show the stray insensitive SC implementations of
amplifier of gain A0=C1/C2 and integrator having transfer
function of the form:

G1, p ( z ) =

(5)

1
B p z Ap

1
G1 (z) = C * A0 +

g11 (z)

C2

(t-T0)

C1
VIN

C1 e

C2 e

' (z)
G3 (z) = C * G3
'
G3 (z) = A0 +
g31 (z)

(t-T0)

TABLE IIA
DIFFERENT OPERATOR BASED CONTINUED FRACTION EXPANSIONS

VOUT

H3 (z) = C * H3' (z)

H3' (z) = 1 +

1
1
1
g32 (z)
g33 (z)

1
g31 (z) +

1
g32 (z) +

1
g33 (z)

T/2 T 3T/2 2T

Fig 3 Non-overlapping clocks

e even clock o odd clock

In Fig. 5,

Fig 4

Switched Capacitor
Amplifier

= AP C and ( + ) = BPC . Using the

recursive relations of (4), several different SC integrator

configurations can be developed. The different configurations
[12] and their transfer functions are given in (6) to (11) (Type
I to Type VI).


e
+

VIN

e 

Transfer Function
Expansion
Al-Alaoui Operator Based Half Differentiator Models
C = 169;A0 = 0.2;
236.6z 169
First
G
z =

1aldiff ( )
7z 1

Order
g11 (z) = 8.75z 1.25;
Third
Order

g31 (z) = 3.25z 0.464;

g32 (z) = 3.76z 1.6236;
g33 (z) = 3.23z 1.381

Al-Alaoui Operator Based Half Integrator Models

Expansion Obtained Using TSE
C = 0.0296;A0 =1;
H3altay int (z) =
Third
Order
g31 (z)=1.7501z-1.2499;
0.0296z3 + 0.0148z2

+0.0111z + 0.0092

z3 0.0714z2

+0.0077z 0.0009111

VOUT

Switched Capacitor Integrator

The appropriate SC blocks are connected in ladder form to

yield Switched Capacitor realizations of half differentiators
and half integrators based on various first and higher order
operators and then the circuits have been simulated using
OrCAD Pspice.
Based on the proposed design approach (refer to
Appendix), the following SC realizations have been
developed.
1. Al-Alaoui operator based first-order half differentiator (Fig
6)
2. Tustin operator based first-order half integrator (Fig 7)
3. Schneider operator based third-order half differentiator
(Fig 8)
4. Al-Alaoui-SKG rule based third-order half integrator
(Fig 9)
5. Hsue operator based third-order half differentiator using
TSE (Fig. 10).
However there are certain limitations to the above
mentioned technique. In some cases, it is not possible to
expand the transfer functions in one of the six types of
expansions, and hence some models are not realizable.
For the simulation of the above mentioned fractional order
circuits using OrCAD Pspice, level-3 MOSFETS and CMOS
amplifiers have been used.

g32 (z)=7.2582z+40.5036;
g33 (z)=0.0049z-0.0242;

Expansion Obtained Using CFE

H1alcfeint (z) =
First
Order
0.0296z 0.04229

Fig 5

C = 62.78;A0 = 0.538;

G
(z) =
3aldiff
1657z3 2603z2

+1048z 62.78

3
2
49z 49z + 7z + 1

Third
Order

z 0.7143

C = 0.0296;A0 = 1;
g11 (z) = 1.75z 1.25;

H3alcfe int (z) =

C = 0.0296;A0 = 1;

0.0296z3 0.0296z2

+0.00423z + 0.0006026
z3 1.571z2

+0.6327z 0.0379

g31 (z) = 1.7513z - 1.2490;

g32 (z) = 7.0393z - 3.0123;
g33 (z) = 1.7341z - 0.7455;

Tustin Operator Based Models

First Order
G1Tu s diff (z) =
Differentiator
44.72z 22.36
First Order
Integrator

z + 0.5

G1Tu sin t (z) =

C = 44.72;A0 = 1;
g11 (z) = z + 0.5;

C = 0.02236;A0 = 1;

0.02236 z + 0.01118

z - 0.5

g11 (z) = z 0.5

Schneider Operator Based Half Differentiator Models

G
(z) =
C = 37.28;A0 = 1;
Third
3Schdiff
Order
37.28z3 18.64z2 4.661z 2.33 g31 (z) = 1.3390z + 0.3495;

z3 + 0.2468z2 0.1356z + 0.1946 g32 (z) = 1.5684z 0.3228;

g33 (z) = 1.6368z 0.3601;

Schneider Operator Based Half Integrator Models

C = 0.02041;A0 = 1;
H3SCHint (z) =
Third
g31 (z) = 0.7692z 0.2101;
0.02041z3 + 0.01633z2

Order

0.008573z + 0.006858
z3 0.5z2 0.125z 0.0625

V.

g32 (z) = 2.6345z 0.4846;

g33 (z) = 1.2711z 0.0546;

SIMULATION RESULTS AND DISCUSSION

In this paper, we have developed Switched Capacitor

realizations of fractional order differentiators and fractional
order integrators of order based on first-order Al-Alaoui
operator and Hsue operator, second order Schneider operator
and third order Al-SKG rule. Figures 11 - 15 show the OrCAD
Pspice results of the different operator based discretizations of
first, third order half differentiators and half integrators.
The results are summarized as follows:

TYPE I



e
o

e C2 e

e
o

C1

Hsue Operator Based Half Differentiator Models

C = 44.72;A0 = 1;
G
(z) =
Third
3HsuetayDiff
g31 (z) = 1.5615z 0.0614;
Order
3
2

Gm,p+1 (z)

TYPE II

44.72z 22.36z

5.591z -2.795

3
2
z + 0.1404z

0.009804z + 0.001382

1
G1,p (z) =
Bpz Ap Gm,p + 1 (z)


e 

Bp =

;Ap =
C
C

(7)

+
o

Gm,p+1 (z)

TYPE III
1 e o

e
o C

2.192e - 4z + 3.091e - 5
3

2
z - 0.5z - 0.125z 0.0625

;Bp = ;
C
C
1 & 2 =

Gm,p +1 (z)

TYPE IV

e 

Ap =

;Bp =
C
C

g33 (z) = 1.5620z - 0.5613;

C2

(9)

o
Gm,p +1 (z)

TYPE V

1
G1, p (z) =
Bp z Ap + Gm, p + 1 (z)




e
o

e C2 e
o

C1 e

;Bp = ;
C
C
C1 & C2 = C

Ap =

C1

VIN

(10)

C2

C1

g31 (z) = 1.5624z - 1.0614;

g32 (z) = 6.2403z - 2.2483;

fifth-order half differentiator results did not show any

perceptible improvement in the phase / magnitude
characteristics.

1
G1,p (z) =
Bpz Ap Gm,p + 1 (z)

C = 0.02236;A0 = 1;

-0.00106z + 8e - 4
3

2
z 1.399z + 0.4132z + 0.0186

(8)

g32 (z) = 6.2505z + 1.4491;

g33 (z) = 1.4310z - 0.0743;

Expansions Obtained Using CFE

H
(z) =
Third
3HsuecfeInt
Order

0.02236z3 - 0.01697z2

Ap =

g32 (z) = 6.2410z + 1.4455;

g33 (z) = 1.4332z 0.0744;

Hsue Operator Based Half Integrator Models

Expansions Obtained Using TSE
H3HsuetayInt (z) =
C = 0.02236;A0 = 1;
Third
g31 (z) = 1.5616z - 0.0617;
Order
0.02236z3 + 0.003139z2

1
G1, p (z) =
Bpz + Ap Gm,p + 1 (z)

g32 (z) = 3.8594z 0.4657;

g33 (z) = 1.4177z 0.0854;

+0.001464z 0.0001366
3

2
z 0.8376z + 0.1577z 0.1157

(6)

TABLE IIB
DIFFERENT OPERATOR BASED CONTINUED FRACTION EXPANSIONS
Al-Alaoui-SKG Rule Based Half Integrator Models
H3ALSKG int (z) =
C = 0.02804;A0 = 1;
Third
g31 (z) = 1.7146z 1.1260;

Order
0.02804z3 0.007133z2

1
G1, p (z) =
Bpz Ap Gm,p + 1 (z)
+

Bp =
;Ap =
C
C
C1 & C2 = C

VOUT

C6

o C4 e

C5

C4

Gm,p +1 (z)

TYPE VI

e
o

e C2 e

o
+

C1
o

1 e o
o

Fig 6

1
G1, p (z) =
Bpz + Ap + Gm, p + 1 (z)

Bp =
;Ap = ;
C
C
C1 & C2 = C; 1 & 2 =

Al-Alaoui operator based first order SC half differentiator

C2

(11)

Gm,p+1 (z)

The frequency responses for the Al-Alaoui operator based

discretizations match with the MATLAB results given in [33],
and also with the theoretical result of half differentiator in
continuous-time domain. Out of these, the results for the AlAlaoui operator based third-order half differentiator realization
are the best. The simulations with higher order fractional order
differentiator were also performed but the

C1
o

Fig 7

e
o

VOUT

C4
o

C2

C1

VIN

C5

C6 o

e
C6

Tustin operator based first order SC half integrator

C2

VIN

e
o

C1

e C1
o o

C7

VOUT

C6

o e

e
o

C5

C6

C8

C8

VOUT

OUT

OUT

e
o o e

C5

o
+

o
OUT

C6

e
o

C6

C10

e C11 e
o o

+OUT

C9

oe
C9

Fig 8

C7

o e

C10
C11

o e C9 e
C9 o o

C4

o e

OUT
+

C1

o e C3 e
C3
o o
o e C3 e
o o
C3

C7

C2

C4

+ OUT

e e

e
o

OUT

e C5 e
o o

C8

e
o

C1

VIN

o C3 e
e o
o C3 e
e o

C2

C2

Schneider operator based third order SC half differentiator.

OUT

Fig 10 Hsue operator based third order SC half differentiator (using TSE)

C2
C1

VIN

e
o

C1

e C2 e
o o
-

VOUT

OUT

C4

o e C3 e
C3 o
o
o e C3 e
C3 o o
e

C8
C7

OUT

C6

o o
OUT

C5

o
e
o

C6

C10

oe
C9

Fig 9

e C11 e
o o
C9

o o

OUT

Al-Alaoui-SKG rule based third order SC half integrator

The phase response of Al-Alaoui operator based third order

half differentiator is very close to theoretical phase of
continuous-time domain half differentiator i.e. 45, whereas
the phase of Al-Alaoui based first-order half differentiator
approaches 45 at higher frequencies only (Fig 11).
In Fig 12, the response of Tustin operator based first-order
half integrator is presented. The realization of Tustin operator
based first-order half integrator is not very encouraging as the
magnitude does not follow the theoretical results of
continuous-time domain half integrator. So the higher order
Tustin operator based discretizations of half integrator were
not explored [33]. The phase results are also not very good.
The simulation results of the Schneider operator based
discretizations of third-order half differentiator are presented
in Fig. 13. From the magnitude plot, it is observed that the
magnitude error as compared to the continuous-time domain
half differentiator is large (more than 2%) and this result

Fig 11 SC results: Al-Alaoui operator based half differentiator

matches with the MATLAB simulation results presented in

[30]. The phase of the Schneider operator based third-order
half differentiator varies from 30 to 60.
In Fig 14, the response of Al-Alaoui-SKG rule based thirdorder half integrator is presented. The magnitude plot matches
with the theoretical results of continuous-time domain half
integrator and the MATLAB simulation results of [30].
However, the phase plot obtained is not so good.
Fig 15 shows the frequency response of Hsue operator
based third-order half differentiator obtained using TSE. The
magnitude plot matches with the MATLAB results presented
in [30], but with slightly larger magnitude error. The phase

shift is observed to be approximately linear approaching 45 at

approx. 550Hz.
Higher order models of the various operator based
fractional-order differ-integrators can also be easily realized
using the proposed method, but the complexity of the SC
circuit increases.
From the above simulation results, it is evident that AlAlaoui-SKG rule and Hsue operator based third-order SC half
differentiator and half integrator realizations match with the
theoretical results of their continuous-time domain counter
parts.

Fig 14 SC results: Al-SKG rule based half integrator

Fig 12 SC results: Tustin operator based half integrator

Fig 15 Hsue operator based half differentiator

VI. CONCLUSION
In this paper, Switched capacitor realizations of fractionalorder differ-integrators ( s r ; r = 1 2 ) based on the different

Fig 13 SC results: Schneider operator based half differentiator

operators have been developed. This method can be extended

to develop fractional-order models and their Switched
Capacitor
realizations
for
different
values
of
( r ; 1 < r < 1; r R ) [35, 36].
The fractional order differentiators and integrators provide
better control as the number of tuning knobs is increased and

CMOS TRANSMISSION
GATE

so they are useful in various control applications viz

temperature control systems.

VII. APPENDIX
The design procedure is as follows:
The Al-Alaoui-SKG rule based third order half integrator
model is (Table IIB)
0.02804 z 3 0.007133 z 2 + 0.001464 z 0.0001366 (12)
H

3 ALSKG int

(z) =

z 3 0.8376 z 2 + 0.1577 z 0.1157

Fig 17 CMOS transmission gate

This expression is expanded as (Table IIB)

( z ) = 0.02804 H '
( z)
3 ALSKG int
3 ALSKG int
1
H'
( z ) = 1 +
3 ALSKG int
1
g (z)
1
1
g ( z)
2
g (z)
3
H

VIII. REFERENCES
(13)

[1]
[2]
[3]

g ( z ) = 1.7146 z 1.1260; g ( z ) = 3.8594 z 0.4657;

1
2
g ( z ) = 1.4177 z 0.0854;
3

In the expansion of (13), the constant term is 0.02804,

which is implemented using a SC amplifier of Fig. 4. The
transfer functions of integrators 1/gi(z) i = 1, 2, 3 are of the
forms
(14)
1
1
g1 ( z )

B z A G
(z)
p
p
m, p + 1

1
1
=
g ( z) B z A G
(z)
p
p
m, p + 1
2

(15)

1
1
=
( z)
g ( z) B z A G
3
p
p
m, p + 1

(16)

These are integrator configurations of Type I, II and I

respectively. These can be implemented using the various SC
integrator configurations given in (6), (7) and connected in
ladder form as shown by the block diagram of Fig. 16.
SC AMPLIFIER

VIN

VOUT

[4]
[5]
[6]
[7]
[8]
[9]

[10]
[11]
[12]
[13]
[14]

SC
INTEGRATOR
TYPE I

[15]
SC
INTEGRATOR
TYPE II

+
[16]

SC
INTEGRATOR
TYPE I

[17]

Fig 16 SC results: Al-SKG rule based half integrator

[18]

In Fig 16, the summers used to connect various blocks of

the ladder have been realized using switched capacitors.
CMOS transmission gates are used as switches and they are
driven by two-phase non-overlapping clock (Fig. 17)

[19]

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J. T. Caves, M. A. Copeland, C. F. Rahim and S. D. Rosenbaum,
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R. Gregorian and G. C. Temes, Analog MOS Integrated Circuits for
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P. E. Allen and D. R. Holberg, CMOS Analog Circuit Design, Prentice
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G. M. Jacobs, D. J. Allstot, R. W. Brodersen and P. R. Gray, Design
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1980, pp. 237-244, also published as BNR Internal Technical Rep. No.
TRlE81, Mar. 1978.
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P. Varshney (M IEEE2005) received the degree of B. E. in

EE in 1993 from University of Roorkee, M.E. in Control &
Instrumentation in 1996 from DCE, DU and Ph. D. from
Delhi University, Delhi, India in 2009. Her major field of
interest is in Analog mixed mode design. She is currently
Assistant Professor in the Instrumentation & Control
Engineering Department at NSIT, New Delhi.
M. Gupta received the degree of B. E. in Electronics
Engineering in 1981 and M. E. in Communication Systems
in 1983 from Government Engineering College, Jabalpur,
and Ph. D. from IIT Delhi, India in 1990. Her major field of
study is Analog Signal Processing. She is currently
Associate Professor in the Electronics & Communication Engineering
Department at NSIT, New Delhi.

G. S. Visweswaran obtained B.E. in Electronics and

Communication Engineering from Madras University in
1971, M. E. in Electronics Engineering from BITS Pilani in
1973 and Ph.D. in Electrical Engineering (Semiconductor
Devices) from IIT Kanpur, India in 1980. Has been a
faculty at IIT Delhi in the EE Department since 1980. He is
currently a Professor in the same department. Major area of interest is in
Circuit Design with larger emphasis on Analog and Mixed Signal Circuits.

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capacitor half differentiator using Schneider operator, ELECO 2005,
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Dec. 2005, site:
http://www.emo.org.tr/etkinlikler/eleco_en/etkinlik_bildiriler.php?etkinlikkod=54

[29] P. Varshney, M. Gupta and G. S. Visweswaran, Switched capacitor

realization of fractional order differentiator, ISIC 2004, 10th Int.
Symposium on Integrated Circuits, Devices and Systems, Suntec,
Singapore, pp. 215-218.
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fractional order differentiator and integrator models based on first and
higher order operators, in press in International Journal of Circuit
Theory and Applications, 2010. DOI: 10.1002/cta.650.
[36] M. Gupta, P. Varshney and G. S. Visweswaran, First and Higher Order
Operator based Fractional Order Differentiator and Integrator Models,
TENCON 2009, Singapore, Nov. 23 26, pp. 1-6.