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Lecture 4

Yield Analysis & Product

Yield and manufacturing cost
Clustered defect yield formula
Yield improvement
Defect level
Test data analysis
Example: SEMATECH chip

Original slides copyright by Mike Bushnell and Vishwani Agrawal


Fraction (or percentage) of good chips produced in a manufacturing process is called the yield. A chip with no manufacturing defect is called a good chip. Cost of a chip: Cost of fabricating and testing a wafer -------------------------------------------------------------------Yield x Number of chip sites on the wafer 2 . Yield is denoted by symbol Y.VLSI Chip Yield n n n n A manufacturing defect is a finite chip area with electrically malfunctioning circuitry caused by errors in the fabrication process.

77 3 .55 Clustered defects (VLSI) Wafer yield = 17/22 = 0.Clustered VLSI Defects Good chips Faulty chips Defects Wafer Unclustered defects Wafer yield = 12/22 = 0.

p (x ) is a delta function (max. p (x ) is Poisson distr. (no clustering) 4 . ---------------------x ! Γ (α) (1+Ad /α) α+x where Γ is the gamma function α =0.Yield Parameters n n n n Defect density (d ) = Average number of defects per unit of chip area Chip area (A) Clustering parameter (α) Negative binomial distribution of defects.. p (x ) = Prob (number of defects on a chip = x ) Γ (α+x ) (Ad /α) x = ------------. clustering) α = ∞ .

Y = 0.37 too pessimistic ! 5 . Y = 0.0.Y=e ∞ .Ad . α = 0.Yield Equation Y = Prob ( zero defect on a chip ) = p (0) Y = ( 1 + Ad / α ) − α Example: Ad = 1.0. α = ∞.58 Unclustered defects: α = Example: Ad = 1.5.

DL is a measure of the effectiveness of tests. DL is measured as parts per million (ppm). 6 .Defect Level or Reject Ratio n n n n Defect level (DL) is the ratio of faulty chips among the chips that pass tests. DL is a quantitative measure of the manufactured product quality. For commercial VLSI chips a DL greater than 500 ppm is considered unacceptable.

From test data: Fault coverage of tests and chip fallout rate are analyzed. The number of returned chips normalized to one million chips shipped is the DL. 7 .Determination of DL n n From field return data: Chips failing in the field are returned to the manufacturer. A modified yield model is fitted to the fallout data to estimate the DL.

β 8 .Modified Yield Equation n n Three parameters: n Fault density.0) remove all faulty chips. β n Stuck-at fault coverage. Y = Y (1) = (1 + Af / β) . T The modified yield equation: Y (T ) = (1 + TAf / β) . f = average number of stuck-at faults per unit chip area n Fault clustering parameter.β Assuming that tests with 100% fault coverage (T =1.

Af is the average number of faults on the chip of area A. β is the fault clustering parameter. 9 .Y (1) DL (T ) = -------------------Y (T ) β ( β + TAf ) = 1 . Af and β are determined by test data analysis.Defect Level Y (T ) .-------------------β ( β + Af ) Where T is the fault coverage of tests.

99.45µ CMOS. some parts 50MHz 0. 9.Example: SEMATECH Chip n n n n n n n n Bus interface controller ASIC fabricated and tested at IBM. 3. Vermont 116.3V.8mm area Full scan.000 equivalent (2-input NAND) gates 304-pin package.4mm x 8.466 chips tested at 2. 249 I/O Clock: 40MHz.79% fault coverage Advantest 3381 ATE. 18.5MHz test clock Data obtained courtesy of Phil Nigh (IBM) 10 . Burlington.

Stuck-at fault coverage Test Coverage from Fault Simulator Vector number 11 .

Measured chip fallout Measured Chip Fallout Vector number 12 .

7623 Measured chip fallout Y (T ) for Af = 2. fault coverage Y (1) = 0.Chip fallout and computed 1-Y (T ) Model Fitting Chip fallout vs.1 and β = 0. T 13 .083 Stuck-at fault coverage.

23%) Stuck-at fault coverage (%) 14 .700 ppm (Y = 76.Computed DL Defect level in ppm 237.

fault coverage ~ 99% 15 . defect density (d ) and clustering parameter (α) Yield drops as chip area increases. low yield means high cost Fault coverage measures the test quality Defect level (DL) or reject ratio is a measure of chip quality DL can be determined by an analysis of test data For high quality: DL < 500 ppm.Summary n n n n n n VLSI yield depends on two process parameters.

Walker. "Critical Area and Fault Probability Prediction. 16 . ed. M. .contains exhaustive survey of all yield modeling research from the beginning in 1960 to 1987. Pineda de Gyvez and D. J. Pradhan." in Integrated Circuit Manufacturability: The Art of Process and Design Integration. IEEE of methods through 1998.. M. VLSI Yield Simulation for Integrated Circuits. 1987.Yield References n n D. H. Kluwer Academic Publishers. Walker. 1998. . D. H. Boston.