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  • Question 3 Case 1 Bode Plot

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    Aseem Garg
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    This document contains 6 sections with Bode plot and transfer characteristic plots for different cases of an inverter circuit. It discusses how increasing the width of an inverter from 3*Wmin to 10*Wmin theoretically decreases the delay time by increasing the speed of the PMOS and NMOS transistors, but this is not observed in the output plots.

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    This document contains 6 sections with Bode plot and transfer characteristic plots for different cases of an inverter circuit. It discusses how increasing the width of an inverter from 3*Wmin to 10*Wmin theoretically decreases the delay time by increasing the speed of the PMOS and NMOS transistors, but this is not observed in the output plots.

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    © All Rights Reserved
    Download as DOCX, PDF, TXT or read online from Scribd
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    17 views7 pages

    Question 3 Case 1 Bode Plot

    Uploaded by

    Aseem Garg
    This document contains 6 sections with Bode plot and transfer characteristic plots for different cases of an inverter circuit. It discusses how increasing the width of an inverter from 3*Wmin to 10*Wmin theoretically decreases the delay time by increasing the speed of the PMOS and NMOS transistors, but this is not observed in the output plots.

    Copyright:

    © All Rights Reserved
    Download as DOCX, PDF, TXT or read online from Scribd
    Flag for inappropriate content
    of 7

    Question 3 Case 1 Bode Plot

    Question 3 Case 2 Bode Plot

    Question 3 Case 3 Bode Plot

    Question 3 Case 4 Bode Plot

    Transfer Characteristics of Invertor with width = 3*Wmin

    Transfer Characteristics of Invertor with width = 10*Wmin

    Answer 5: In the output plots of Invertor with two different widths, we did not observe any
    distinct change but according to the theory, increasing the width increases the speed of the
    PMOS and NMOS. So we can observe less delay time in second case as compared first case.

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