Program Name B.E.

( Electronics & Communication Engineering)

Semester 6th

Course Code EC211

High Speed VLSI Circuits
Course Name
Lecture / Tutorial (per week) 3/1 Course Credits 03

Lect. No. 9-12 || Choosing the best number of stages

Course Coordinator Name Dr. Kulbhushan Sharma

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Contents
 Choosing the best number of stages.
• Model of a logic.
• Delay in a logic gate,
• minimizing delay along a path.

• Books to be referred:
• BO2: ‘High Speed CMOS Design Styles’ by Kerry Bernstein Keith M. Carrig Christopher M. Durham Patrick R. Hansen David
Hogenmiller Edward J. Nowak Norman J. Rohrer, 5th edition, Springer Science+Business Media, LLC Publications (1999).
• BO3: ‘CMOS Digital integrated circuit analysis and design” by Sung-Mo (Steve) Kang, Yusuf Leblebigi, 3 rd edition, Tata
Mcgraw-Hill, (2007).

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Choosing the best number of stages

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Choosing the best number of stages

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Delay of a logic circuit

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Procedure for logical effort calculation

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Examples

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Delay in logic gate

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Delay in logic gate

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Calculating the gate sizes

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Model of a logic gate

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Model of a logic gate

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Delay in a logic gate

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Delay in a logic gate

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Minimizing delay along a path

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Minimizing delay along a path

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Choosing the length of a path

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Choosing the length of a path

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Choosing the length of a path

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Choosing the length of a path

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Using wrong number of stages

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Using wrong number of stages

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Using wrong gate size

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