Verilog code for BCD Adder:

module bcdadd(a,b,cin,s,cout); //Main module of one digit BCD adder

input [3:0]a;
input [3:0]b;
input cin;
output[3:0]s;
output cout;
wire [3:0]w;
wire y,c0,c1,c2,c3,c4,c5;
fulladd m1(a[0],b[0],cin,w[0],c0);
fulladd m2(a[1],b[1],c0,w[1],c1);
fulladd m3(a[2],b[2],c1,w[2],c2);
fulladd m4(a[3],b[3],c2,w[3],c3);
assign y=c3|(w[3]&(w[2]|w[1]));
halfadd m5(w[1],y,s[1],c4);
fulladd m6(w[2],y,c4,s[2],c5);
halfadd m7(w[3],c5,s[3],cout);
assign s[0]=w[0];
endmodule
module fulladd(a,b,cin,s,cout); //submodule for fulladder
input a,b;
input cin;
output s;
output cout;
wire w1,w2,w3;
halfadd g1(a,b,w1,w2);
halfadd g2(w1,cin,s,w3);
assign cout=w3|w2;
endmodule
module halfadd(a,b,s,cout); //submodule for halfadder
input a,b;
output s,cout;
assign s=a^b;
assign cout=a&b;
endmodule

BCD Adder design and simulation with Verilog HDL Code in ModelSim
Computers understand binary number system while humans are used to arithmetic operations in
decimal number systems. To enhance Computer-Human relationship in this perspective,
arithmetic operations are performed by the computer in a binary coded decimal, (BCD) form.
In this article Ill analyse and design a BCD adder which requires a minimum of nine inputs and
five outputs, four bits are require to code the aguend and the addend making eight bits, and the
circuit input carry makes the nine inputs. The four bit sum output and the output carry represents
the five outputs.
Consider adding 9+9+1 in decimal, the result is 19, in straight binary this should produce an
output 100112, this is an invalid number in BCD, because in BCD code the group of four bit
binary only represent decimal numbers 0-9. The table bellow shows decimal numbers 0-19 with
their corresponding binary and BCD codes. The K and C in the table are the respective binary
carry and BCD carry bits.

Bellow the ruled level on the table, the BCD adder should detect that the binary codes are
unusable in BCD coding system and provide the necessary correction. The conditions for the
levels on the table where correction is required a;
1. Point where binary sum has output carry K =1 or,

2. where Z8 and Z2 are both = 1 or,

3. where Z8 and Z4 are both = 1.
The gives the expression for correction requirement: Cor = K + Z8Z4 +Z8Z2
When Cor = 1, it is necessary to add 0110 to the binary sum and provide an output carry for the
next stage.
For example:
Adding:

Figure 1: Block diagram of BCD adder

When an output carry K = 0 nothing happens as the out S8S4S2S1 is added to 0000 in the second
4-bit adder, but when K=1 OR Z8&Z4 OR Z8&Z2 is equal to 1, the output carry generates a 1,
thus 0110 is added to the output of the first 4-bit adder. The MSB 0 and LSB 0 in the 0110 to
be added is generate by the EXOR gate which accept the output carry at its two input, either the
output carry is 0 or 1 the EXOR generates a 0 (both its input are equal).
The CBCD is the carry generated by the BCD adder, whenever the output of the OR-gate is 1 a
carry is generated by the BCD adder to the next four-bit group of the BCD code, carry output
generated by the 4-bit adder of the second stage is discarded as it will provided by CBCD as
required. Bellow is the Verilog HDL code for BCD adder and figure 2,3, and four shows the
simulations changing the bits value at 100ns, 200ns and 300ns.
//----------------------------------------------------module BCD_adder(S, C, A, B, C0);
input [3:0] A, B;
input C0;
output [3:0] S;
output C;
wire C1, C2, C3, C4, C5;
wire [3:0]X, Z;
and (C1, Z[3], Z[2]);
and (C2, Z[3], Z[1]);
or (C, C3, C1,C2);
xor (C5, C, C);
assign
assign
assign
assign

X[2]
X[1]
X[3]
X[0]

=
=
=
=

C;
C;
C5;
C5;

//four bit adder body from instance of full_adder

four_bit_adder F_1 (Z, C3, A, B, C0);
four_bit_adder F_2 (S, C4, X, Z, C0);
endmodule
//---------------------------------------------------------//------------------------------------------------------------// Test bench for BCD_Adder
module t_BCD_adder;
wire [3:0] S;
wire C;
reg [3:0]A, B;
reg C0;
BCD_adder F1(S, C, A, B, C0);
initial

begin
A[3:0] = 4'b0000; B = 4'b0000; C0 = 1'b0;
#100 A[3:0] = 4'b1001; B = 4'b1001; C0 = 1'b0;
#100 A[3:0] = 4'b1000; B = 4'b0011; C0 = 1'b0;
#100 A[3:0] = 4'b0100; B = 4'b0011; C0 = 1'b0;
end
initial #400 $finish;
endmodule
//--------------------------------------------

Figure 2: Simulation showing the initial bits value of A: 0000, B: 0000, Sum S: 0000 and Carry
C: 0 for the BCD adder (i.e. 0 + 0 = 0 0).

F
i
g
u
r
e Figure 3: Simulation showing the bits value at 100ns for A: 1001, B: 1001, Sum S: 1000 and
5 Carry C: 1 for the BCD adder (i.e. 9 + 9 = 1 8 ).
:
S
i
m
u
la
ti
o
n
s
h
o
w
i
n
g
t
h
e
b
it Figure 4: Simulation showing the bits value at 300ns for A: 1000, B: 0011, Sum S: 0001 and
s Carry C: 1 for the BCD adder (i.e. 8+ 3 = 1 1 ).
v
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at
3
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f

Design of 8 Bit Adders

Aim:
To design a BCD adder circuit using Verilog HDL
Apparatus Required:
Synthesis tool: Xilinx ISE.
Simulation tool: ModelSim Simulator
Theory:
A BCD adder is the circuit that adds two BCD digits in parallel and produces a sum digit also in
BCD. The input digit does not exceed 9,the output sum cannot greater than 9+9+1=19, the 1 in
the sum being an input carry. Suppose we apply two decimal digits, together with the input carry,
are first added in the top 4-bit binary adder to produce the binary sum. When the output carry is
equal to zero, nothing is added in the binary sum . When it is equal to one, binary 0110 is added
to binary sum through the bottom 4-bit binary adder. Output generated from bottom binary adder
can be ignored. The output carry can be expressed in Boolean function
k = c4 + s3s2 + s3s1
Procedure:
1. The BCD adder circuit is designed and the Boolean function is found out.
2. The VHDL program source code for the circuit is written.
3. It is implemented in Model Sim and Simulated.
4. Signals are provided and Output Waveforms are viewed
Bcd adder using Verilog :
module bcdadder(s,k,a,b,c,d,e);
output [4:7] s;
inout k;
input [0:3]a,b;
input c,d,e;
wire c1,c2,c3,c4,s0,s1,s2,s3,e1,e2,e3,e4;
fulladder f1(s0,c1,a[0],b[0],c);
fulladder f2(s1,c2,a[1],b[1],c1);
fulladder f3(s2,c3,a[2],b[2],c2);
fulladder f4(s3,c4,a[3],b[3],c3);
assign k=((s3 & s2) | (s3 & s1)| c4);
fulladder f5(s[4],e1,s0,d,e);
fulladder f6(s[5],e2,s1,k,e1);
fulladder f7(s[6],e3,s2,k,e2);
fulladder f8(s[7],e4,s3,d,e3);
endmodule
module fulladder(s,ca,a,b,c);
output s,ca;
input a,b,c;

xor(s,a,b,c);
assign ca=((a & b)|(b & c)| (c & a));
endmodule

Logic Diagram