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Structural Modeling
EL 310
Erkay Sava
Sabanc University
1
Structural Modeling
Behavioral Modeling (describing internal
behavior of a component)
CSA statements (dataflow model)
Process
Structural Modeling
Describing Structure
Block diagrams
Full Adder
in1
in2
c_in
s1
HA1
sum
HA2 s2
s3
O1
c_out
Full Adder
We assume that we have the description of
half adders and or gate.
Actually, we are not interested in the internal
behavior of these components.
sum
carry
x
z
y
Connecting Components
List of components
Uniquely labeling components to distinguish
among multiple instances of the same
component.
Set of signals connecting them
Specify how signals are connected to ports of
components.
component
declarations
signal
declarations
component
instantiation
statements
Structural Model
Different instances of a component have
identical input port names.
This is not a problem; since the port name is
associated with a specific instance through a unique
label.
combinational
carry
logic
s2
s1
Q
clk
00/0
01/1
10/1
11/0
01/0
10/0
11/1
00/1
8
the component
component dff is
port (D,clk, R: in std_logic;
Q, Qbar: out std_logic);
end component dff;
signal or port
on the entity
not connected
10
11
a0
b0
a1
b1
a2
b2
ALU0
s0
c1
ALU1
s1
s2
s3
(1111) + (0001)
worse case
addition
c2
ALU2
Carry-ripple adder
c3
a3
b3
ALU3
c4
12
A Faster Adder
To add two corresponding bits of A an B, we
have to know the carry from the sum of
previous bits.
c1 = b0c0 + a0c0 + a0b0
c2 = b1c1 + a1c1 + a1b1 =
(b1+a1)(b0c0+a0c0+a0b0)+a1b1
c3 = b2c2 + a2c2 + a2b2 =
(b2+a2)(b1+a1)(b0c0+a0c0+a0b0)+a1b1+a2b2
c4 = b3c3 + a3c3 + a3b3 =
(b3+a3)(b2+a2)(b1+a1)(b0c0+a0c0+a0b0) + a1b1
+ a2b2 + a3b3 =
13
Carry Lookahead - 1
An approach in-between the two extremes
Motivation:
If we didn't know the value of carry-in, what
could we do?
When would a carry be always generated?
gi = aibi
When would the carry be propagated?
pi = ai+bi
Using them we can write the following formula
ci+1 = gi+pici
To see where the signals get their names suppose
gi=1 ci+1=1+pici= 1
that is, the adder generates the CarryOut
(independent of CarryIn)
14
Carry Lookahead 2
gi = 0 and pi = 1 ci+1=ci
That is CarryIn is propagated to CarryOut.
c1 = g0 + p0c0
c2 = g1 + p1c1 = g1 + p1g0 + p1p0c0
c3 = g2 + p2c2 = g2 + p2g1 + p2p1g0 +
p2p1p0c0
c4 = g3 + p3c3 = g3 + p3g2 + p3p2g1 +
p3p2p1g0 + p3p2p1p0c0
Question: How can we compute pis and gis
efficiently?
15
Brent-Kung Formulation
An associative operation:
(x, y)(w,z) = (x+yw, yz)
(c0, 1)
(g0, p0)(c0, 1)=(g0+ p0c0, p0)= (c1, p0)
(g1, p1)(c1, p0)=(g1+ p1c1, p1p0)=(c2, p1p0)
(g2, p2)(c2, p1)=(g2+ p2c2, p2p1p0)=(c2, p2p1p0)
...
(gi, pi)(ci, pip1p0)=
(gi+ pici, pip1p0)=(ci+1, pip1p0)
16
Brent-Kung Circuit
gi
ci+1
pi
ci
pi-1 ...p1 p0
pi pi-1 ...p1 p0
Brent-Kung Formulation
(gi, pi )
(g1, p1 )
(g0, p0 )
(c0, 1 )
(c1, p0 )
(c2, p1 p0 )
(ci, pi ... p0 )
Prefix Problem
Prefix Algorithms
Sequential or Serial Algorithm
x7
x3
x2
x1
x0
y0
y1
y2
y3
y7
Depth: n-1
Size: n-1
20
Prefix Algorithms
Obvious Parallelization Algorithm
x3 x2
x1
y3
x0
x2
x1
x0
x1
y2
y1
x0
x0
y0
Depth: log2n
Size: 0 +1 + 2 + 3 + + n-1 = n(n-1)/2=O(n2)
21
Ladner-Fischer Constructions
Depth: O(log2n)
Size: O(n)
Assumption: n=2d.
(n is the number of bits in our adder)
Ladner-Fischer constructions provide a family of
circuits for n:
Pk(n) where 0 k d and d = log2n.
For example:
n = 2 (d = 1) P0(2) and P1(2)
n = 4 (d = 2) P0(4) , P1(4), and P2(4).
n = 8 (d = 3) P0(8) , P1(8), P2(8), and P3(8)
22
Ladner-Fischer Constructions
Properties of Pk(n) circuit:
Depth: Dk(n) = d + k
Size: Sk(n) = 2(1+2-k)n F(5+d-k) + 1 k
where F is the Fibonacci number
i
f(i)
0
0
1
1
2
1
3
2
4
3
5
5
6 7 8 9
8 13 21 34
S0(n) = 3n-F(5+d)+1
S1(n) = 3n-F(4+d)
23
Ladner-Fischer Circuits
Pk(1) and k = 0 P0(1)
D = 0, S = 0
D = 1, S = 1
24
Ladner-Fischer Circuits
Pk(4) and k = 0, 1, 2 P0(4) , P1(4), and P2(4)
There is no other circuit but P0(4) for n = 4.
Question: how to construct P0(4) from P0(2) ?
x3 x2
P0(2)
x3x2x1x0
x2x1x0
x1
x0
P1(2)
x1x0
x0
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(c3, p2 p1 p0)
(g1, p1)
(g0, p0)
(c0, 1)
(c2, p1 p0)
(c1, p0)
(c0, 1)
Brent-Kung Circuit
26
n-1
P0(n/2)
n/2-1
P1(n/2)
27
n-1 n-2
4 3 2 1
P0(n/2)
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P1(4)=P0(4)
43210
543210
6543210
76543210
P0(4)
10
210
3210
P0(8)
0 (c0, 1)
1 (g0, p0)
2 (g1, p1)
3 (g2, p2)
7 (g6, p6)
10 (c1, p0)
210 (c2, p1p0)
3210 (c3, p2p1p0)
29
P1(8)
7
6 5
4 3
P0(4)
30
Assignment
31
Hierarchy of Models
full_adder.vdh
half_adder.vdh
or2.vdh
and2.vdh
xor2.vdh
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Flattening
When the simulator loads the hierarchy of
structural model, it replace each component by
its behavioral description.
This process is repeated at each level hierarchy.
Parameterized Models
Aim: to construct parameterized models.
35
Generics
library IEEE;
use IEEE.std_logic_1164.all
entity xor2 is
generic(gate_delay: Time:= 2ns);
port(x, y: in std_logic;
z: out std_logic);
end entity xor2;
architecture behavioral of xor2 is
begin
z <= (x and y) after gate_delay;
xor gate is defined
end architecture behavioral;
with generic
Generics
architecture structural of half_adder is
component xor2 is
generic(gate_delay: Time);
port (x,y: in std_logic;
z: out std_logic);
end component xor2;
component and2 is
generic(gate_delay: Time:=3 ns);
port (x, y: in std_logic;
z: out std_logic);
end component and2;
begin
EX1: xor2 generic map(gate_delay => 6 ns)
port map(x=>x, y=>y, z=>sum);
AND1: and2 port map(x=>x, y=>y, z=>carry)
end architecture structural;
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38
full_adder.vhd
...
H1: half_adder generic map(gate_delay => 6 ns)
port map(a => in1, b => in2, sum => s1, carry=>s2);
H2: half_adder ...
...
6 ns
6 ns
half_adder.vhd
6 ns
6 ns
...
EX1:xor2 generic map
(gate_delay=>gate_delay)
...
...
EX1:xor2 generic map
(gate_delay=>gate_delay)
...
6 ns
xor2.vhd
entity and2 is
generic(gate_delay: Time:= 2ns);
...
6 ns
and2.vhd
entity xor2 is
generic(gate_delay: Time:= 2ns);-...
40
Another Example
entity another_gen_ex is
end entity another_gen_ex;
architecture generic of another_gen_ex is
-- component declaration for the gates
component and_gate is
generic(n:natural:=5);
port(x: in std_logic_vector(n-1 downto 0); z: out std_logic);
end component;
component or_gate is
generic(m:integer);
port(x: in std_logic_vector(m downto 1); z: out std_logic);
end component;
signal s1, s2, s3, s4: std_logic;
signal sa: std_logic_vector(1 to 5);
signal sb: std_logic_vector(2 downto 1);
signal sc: std_logic_vector(1 to 10);
signal sd: std_logic_vector(5 downto 0);
begin
-- component instantiations
o1: or_gate generic map(6) port map(sd, s1);
a1: and_gate generic map(N => 10) port map(sc, s3);
a2: and_gate port map(sa, s4);
-- o2: or_gate port map(sb, s2); -- illegal
end architecture generic;
42
N-bit Register
library IEEE;
use IEEE.std_logic_1164.all;
entity generic_reg is
generic(n: positive := 2);
port(clk, reset, enable: in std_logic;
d: in std_logic_vector(n-1 downto 0);
q: out std_logic_vector(n-1 downto 0));
end entity generic_reg;
architecture behavioral of generic_reg is
begin
reg_process: process(clk, reset) is
begin
if reset = 1 then
q <= (others => 0);
elsif (rising_edge(clk)) then
if enable = 1 then
q <= d;
end if;
end if;
end process reg_process;
end architecture behavioral;
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44
Core Generators
A CAD tool
allow you select and then configure the components
of your choice.
The CAD tool will then generate a synthesizeable
model of this component and corresponding VHDL
model.
The CAD tools generally do a good job of producing
models that will generate highly optimized
implementations for the target FPGA device.
The LogiBLOX of Xilinx Foundation is such a tool.
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addsub8.vhi File
------------------------------------------------------- LogiBLOX ADD_SUB Module "addsub8"
-- Created by LogiBLOX version E.35
-on Sun Nov 02 17:37:55 2003
-- Attributes
-MODTYPE = ADD_SUB
-BUS_WIDTH = 8
-OPTYPE = ADD_SUB
-REGISTERED = NONE
-ENCODING = SIGNED
-STYLE = MAX_SPEED
---------------------------------------------------------------------------------------------------------
50
addsub8.vhi File
-- Component Declaration
---------------------------------------------------component addsub8
PORT(
ADD_SUB: IN std_logic;
C_IN: IN std_logic;
A: IN std_logic_vector(7 DOWNTO 0);
B: IN std_logic_vector(7 DOWNTO 0);
SUM: OUT std_logic_vector(7 DOWNTO 0);
OVFL: OUT std_logic;
C_OUT: OUT std_logic);
end component;
----------------------------------------------------- Component Instantiation
---------------------------------------------------instance_name : addsub8 port map
(ADD_SUB => ,C_IN => , A => , B => , SUM => , OVFL => ,C_OUT => );
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