TITLE:

DESIGN OF A LOW POWER FLIP-FLOP USING CMOS DEEP

SUBMICRON TECHNOLOGY

GROUP MEMBERS:
M.AMULYA
K.KEDAR
N.D.S.K.SEKHAR

BLENU4ECE08508
BLENU4ECE08507
BLENU4ECE08503

VII SEM/ ECE A

AMRITA SCHOOL OF ENGINEERING, BANGALORE

NAME OF THE GUIDE:

SIGN OF THE GUIDE:

Ms. KIRTI S PANDE

ABSTRACT:
This project enumerates low power, high speed design of flip-flop having
less number of transistors and only one transistor being clocked by short pulse
train which is true single phase clocking (TSPC) flip-flop.
Compared to Conventional flip-flop, it has 5 Transistors and one transistor
clocked, thus has lesser size and lesser power consumption. It can be used in
various applications like digital VLSI clocking system, buffers, registers,
microprocessors etc.
The analysis for various flip flops and latches for power dissipation and
propagation delays at 0.13 micron and 0.35 micron technologies is carried out. The
leakage power increases as technology is scaled down.
The leakage power is reduced by using best technique among all run time
techniques viz. MTCMOS. Thereby comparison of different conventional flipflops latches and TSPC flip-flop in terms of power consumption, propagation
delays and product of power dissipation and propagation delay with SPICE
simulation results is presented.

PLAN OF WORK AND TIME CHART:

DEADLINE

WORK TO BE DONE

End of December

Ground work to understand all the basic

designs, concepts and techniques to be
used in the project.
Understanding the working of the
various flip-flops used in the project.
Understanding the working of SPICE
and exploring the usage of various
commands needed for implementing
the various flip-flops.
Implementation of the flip-flops using
the designs found at the simulation
level.
Comparing the various results obtained
and finding the best design that has the

End of January
End of February

End of March

End of April

lowest power dissipation, propagation

delay.

REFERENCES:
1. Surya Naik, Rajeevan Chandel, "Design of a Low Power Flip-Flop Using
CMOS Deep Sub Micron Technology," itc, pp.253-256, 2010 International
Conference on Recent Trends in Information, Telecommunication and
Computing, 2010
2. http://www.informatik.uni-oldenburg.de/~pipsoft/lpdesignguide.pdf
3. http://etd.library.vanderbilt.edu/available/etd-09062010120803/unrestricted/benakanakeresheshadri.pdf
4. Massoud Pedram, Department of EE-Systems, University of Southern
California, Los Angeles CA 90089. Hirendu Vaishnav, Synopsys, Inc., 700 East
Middleled Road, Mountain View, CA-94043, Power Optimization in VLSI
Layout: A Survey, http://atrak.usc.edu/~massoud/Papers/lp-layout-survey.pdf