LIST OF FIGURES

Figure No.

Title

Page No.

Figure 2.1 Block diagram of operational amplifier

Figure 2.2 Differential Operational amplifier

Figure 2.3 Differential amplifier and double swing representation

Figure 2.4 One stage differential operational amplifier

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Figure 2.5 Telescopic amplifier topology

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Figure 2.6 Folded-cascode amplifier topology

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Figure 2.7 Gain boosted differential operational amplifier

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Figure 2.8 Two-stage amplifier topology

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Figure 3.1 Flow chart for integrated circuit design process

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Figure 3.2 Simple Compensated OP-Amp circuit with capacitive load

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Figure 4.1 Simulation setup for Input differential amplifier stage

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Figure 4.2 Two-stage op-amp using level 2 MOSFET

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Figure 4.3 Implementation of the Nulling resistor

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Figure 4.4 Bias references for FET M9, M10.

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Figure 5.1 Circuit arrangement for slew rate measurement

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Figure 5.2 Simulation result for slew rate measurement

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Figure 5.3 Circuit arrangement for Swing measurement

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Figure 5.4 Simulation result for swing measurement

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Figure 5.5 Circuit arrangement for gain measurement

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Figure 5.6 Simulation result for gain measurement

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Figure 5.7 Generic low-power design flows.

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