1) OPEN Dsch2 Application ICON in Export dsch2 folder

2) Take new and draw the schematics take all basic symbols from symbol
library
Ex:(DML NOR GATE)

Save schematic with ckt name

3) Run the simulation

4)obser inputs and outputs on timing diagram

5)generate Verilog file:

Ok

6)make new symbol

Ok

7)open Microwind 2 Application from Export microwind2 folder

8)compile verilog file which is generated from digital schematic

9)compile and back to editor

10:obser layouts of ckt

11:run simulation

13:obser simulated output