Logic Design Homework No. 2.

Write your name your ID clearly on a separate page and hand it in.

0. Read and reproduce the results from xilinx tutorial1.pdf and read Verilog II.pdf.

1. Verilog to Schematics : Draw schematics from the following Verilog code. You can use all the basic
logic gates (AND, OR, INV) as well as multiplexors (MUX).

module vs (a, b, c, d, s, t);

input s, a, b, c, d;
output t;
reg t;
always @(s or a or b or c or d)
if (s)
t = c|d;
else
t = ~(a & b);
endmodule

2. Schematics to Verilog: Look at the following schematics:

and fill in the missing Verilog code below. Feel free to add wire’s that you need, but you MUST NOT
modify module name or ports.

module blah (a, b, c, e);

input a, b, c;
output e;

// add verilog code here

endmodule

3. Verilog Design: Make sure you have reproduced the results from xilinx tutorial1.pdf.

Design a Verilog module with 3 inputs: a, b, c, and one output, m. The output m is the majority of its 3
inputs. Copy the following code header to a new ISE project and finish up the design:

module majority (a, b, c, m);

input a, b, c;
output m;

// add verilog code here

endmodule

Your submission must include:

- print out of your Verilog code (as you did in xilinx tutorial 1.pdf)
- print out of waveform results of the simulation (as you did in xilinx tutorial 1.pdf)