Ex. No.

: 2a SIMULATION OF 4X1 MULTIPLEXER USING 3 MODELING

STYLES IN VERILOG
Date:

AIM

To model and simulate a 4x1 multiplexer using Verilog in 3 modelling styles (data flow
model, behavioural model and structural model).

SOFTWARE REQUIRED:

Simulation tool: Xilinx Vivado 2015

BLOCK DIAGRAM:

4x1 Multiplexer

PROCEDURE:

1. Design the Logic circuit (Schematic / logic diagram) and write the Boolean function/
expressions.
2. Create new RTL project in Xilinx Vivado.
3. Choose the HDL language (Verilog) and the device (Zedboard).
4. Write the Verilog module for the designed logic circuit using three modeling styles in the
Code editor.
5. Simulate the source program using Xilinx Simulator tool. Run behavioural Simulation.
6. Force the inputs (and clock if any) in the object window and Run simulation.
7. Verify the output in the obtained simulation waveform .

PROGRAM CODE:
SIMULATION WAVEFORM:
Data Flow Model:

Behavioural Model:

Structural Model:

RESULT:
Verilog Programs for 4x1 multiplexer in three modelling styles (Data flow, behavioural and
structural) were written, simulated and the outputs were verified from the generated simulation
waveform.
Ex. No.:2b SYNTHESIS, P&R AND POST P&R SIMULATION OF 4x1 Multiplexer
Date:

AIM:
To synthesize, implement and perform post implementation simulation for 4x1 Multiplexer
using Verilog program.

SOFTWARE/HARDWARE REQUIRED:
Simulation tool: Xilinx Vivado 2015
ZedboardZynq 7000 Development Board

PROCEDURE:

1. After simulation, Click on Run Synthesis under the flow navigatorpane.

2. Open Synthesized Designand view the Elaborated Synthesized Design.
3. Examine the resources utilised in the synthesized design from the project summary.
4. Perform IO pin assignment for each of the inputs and outputs as per board configuration
and save constraints.
5. Re-run the synthesis.
6. Click on Run Implementation under the Flow Navigatorpane. Open and view the
implemented design.
7. Examine the resources utilised in the implemented design from the project summary.
8. Run Post-Implementation Timing Simulation under the Simulation tasks in the Flow
Navigator pane and obtain the waveform by giving test vector inputs.

OUTPUT:

1. Constraints Files
2. Implemented Design

3. Elaborated Design

4. Utilisation after synthesis

 5. Utilisation after Implementation

6. Utilisation Report

7. Post – implementation Simulation

RESULT: Thus 4x1 Multiplexer Verilog program was synthesized, implemented and post
implementation simulation was performed.
Ex. No.:2c HARDWARE FUSING AND TESTING OF 4x1 Multiplexer
Date:

AIM:

To perform hardware fusing and testing of 4x1 Multiplexer module in Zedboard using Xilinx
Vivado.

SOFTWARE/HARDWARE REQUIRED:

Simulation tool: Xilinx Vivado 2015

ZedboardZynq 7000 Development Board

PROCEDURE:

1. Connect the Zedboard to the PC and power ON.

2. Click on Generate Bit stream entry under the Program and Debugtasks of the Flow
Navigator pane.
3. Click on “Open Hardware Manager”. Click on “Open Target” and select “Auto Connect”.
4. Program the Device xc7z020_1.
5. Once the program is downloaded into the Zedboard, verify the functionality by varying
the input switches and checking the output LEDs.

RESULT:

Thus the hardware fusing and testing of 4x1 Multiplexer module was performed in Zedboard
using Xilinx Vivado.