DDD

STATIC TIMING ANALYSIS
BASIC CONCEPTS - I
CADENCE CONFIDENTIAL
STA overview
There are two primary methods of
analyzing or verifying the timing of a
design -
Dynamic Timing Simulation

Static Timing Analysis
STA02_basic_concepts
STA overview
Static timing Analysis is a method for determining if a
circuit meets timing constraints without having to
simulate clock cycles.
These involves three main steps -
Design is broken into sets of timing paths
The delay of each path is calculated
All path delays are compared to see if timing constraints have

been meet.
STA overview
TECHNOLOGY
LIBRARY
Netlist
STA tool
sdf/spef
Report
Slack Report
Clock waveform report
Violation Report
CONSTRAINTS
STA overview
Steps to do Timing Analysis :
read in the Timing libraries, Timing constraints, Netlist, spef/sdf
Specify the operating conditions to specify process, voltage, and
temperature (PVT) values.
Specify the analysis mode you want to use for timing analysis. : single, best-case
worst-case (BC-WC), and on-chip variation
Generate reports : report_timing, report_slack etc
Example script for ETS

read_verilog test.v
set_top_module test
read_lib -max stdcell_max.lib -min stdcell_min.lib
read_sdc test.sdc
set_op_cond -maxLibrary worstlib -max slow -minLibrary bestlib
-min fast
set_analysis_mode -bcWc
report_timing -late
report_timing -early
Timing Constraints
Every design has to meet certain Timing requirements.
Designer must specify these requirements by setting the
constraints.
Timing constraints are use to set Speed of Design ( clock frequency)
boundary condition ( input delay, output delay)

Slew rates
Path exception such as false path, multicycle path
Disable certain path in design
Link for constraints :

http://pubs.cadence.com/tkps/test/release/SOC62/sun4v/doc/fetxtcmdref/sdcT.html#1035472
Constraints
create_clock
create_generated_clock
set_propogated_clock
set_clock_uncertainty
set_clock_latency
set_input_delay
set_output_delay
set_max_delay
set_min_delay
set_max_fanout
set_max_capacitance
set_max_transition
8
Constraints
set_drivie
set_driving_cell
set_false_path
set_multicycle_path
set_fanout_load
set_load
set_case_analysis
Link for constraints :

http://pubs.cadence.com/tkps/test/release/SOC62/sun4v/doc/fetxtcmdref/sdcT.html#1035472
Clock latency
Source latency
Network Latency
10
Clock latency
Source latency
Source latency is the time a clock signal takes to propagate from
its ideal waveform origin point to clock definition point of design
Specified using the -source option
Honored in both ideal and propagated modes.
Example :
set_clock_latency -source -max -rise 2 {clkA}
11
Clock latency
Network latency :
It is the time a clock signal takes to propagate from clock
definition point to register clock pin
FF
Clk
Default latency type

Considered only in ideal mode.
In propagated mode, this delay is replaced by the actual clock
tree delays
Example : set_clock_latency -max -rise 0.4 Clk
12
Clock uncertainty
Clock uncertainty is the difference between the arrival of clock
at registers in one clock domain or between domains
IN1
D
CK1
OUT1
CK2
CK
CK1
CK2
Skew
13
Clock uncertainty
Uncertainty value will be subtracted from data required time when
doing setup analysis
This will be add to data required time when doing hold analysis
Example :
set_clock_uncertainty
clk1
2.0
set_clock_uncertainty -from clk1 -to clk2 -rise -hold 2.0
14
set_input_delay
It is the arrival times relative to a clock edge on input
ports or internal input pins.
T
ck
D Q
L1
ck
clk
In1
L2
D Q
C
In1
Input delay
input delay
clock period
Example
set_input_delay -clock ck 1.0 [all_inputs]
15
Example
D Q
L1
clk
clk
input delay
clock period
clock period = 4
L1 = 0.8
L2 = 3.0
setup =0.3
16
In1
L2
D Q
C
Without set_input_delay :
tool will analyse as :
Required time = 4- 0.3 = 3.7
Arrival time = input_delay + L2 = 0 + 3.0 =3.0
Slack = 3.7 3.0 = 0.7 (met)
But Actually what happened :
Required time = 4 0.3 = 3.7
Arrival time = L1 + L2 =0.8 + 3.0 = 3.8
Slack = 3.7 -3.8 = -0.1 (violated)
With set_input_delay = 0.8

tool will analyse as :
Required time = 4-0.3 = 3.7
Arrival time = input_delay + L2 = 0.8 + 3.0 = 3.8
Slack = 3.7 3.8 = -0.1 (violated)
set_output_delay
It is the data required time at the output port
D Q
L4
out1
L5
D Q
C
clk
out1
output delay
ck
output delay
clock period
Example
set_output_delay 2.5 -clock ck { out1 }
17
Set_false_path
False path is a timing path that cannot propogate a signal.
It is required to specify the false path, so that tool will

not consider this path while analyzing timing.
U1
a
b
c
d
0
1
s
U2
0
U4
y
a+c
False Path
+
U3
U5
y
b+d
Example : set_false_path from U1/a to U5/y
18
set_multicycle_path
A multicycle path is a path that is not expected

to propagate a signal in one cycle.
By default all paths are constrained for single

cycle timing.
Specify multicycle path explicitly if required

ff2
ff1
D
CL
C
clk
clk
Clock Period
Example : set_multicycle_path 2 from ff1 to ff2
19
Time allowed
Example : (how to constrain)

Design
D Q
L1
ck
clk
In0
L2
D Q
L3
L4
out1
L5
input delay
clock period
D Q
D Q
C
output delay
clock period
clock period
create_clock -name clk1 -period 20 -waveform {0 10} [get_ports {ck}]

set_input_delay -clock clk1 1.0 [all_inputs]
set_output_delay -clock clk1 1.2 [all_outputs]
set_clock_uncertainty 2.0
set_clock_latency -early -late 0.3 -source clk1
set_propagated_clock [all_clocks]
20
How STA tools analyze Timing

Example (setup Analysis):
0 0.037
In0
0.037
0.0
0.037
ff1
0.0
0.0
Clock Period = 20ns

Input Delay = 1ns
0.022
source latency =0.3 ns Constraints

Uncertainty = 2 ns
0.056
clk1
tsetup = 0.249 From Library
Data Arrival time = 0.3+ 1.0 + 0.037 + 0.037 +0.037

= 1.412
Data Required time = 0.3 + 0.022 +0.056 + 20 0.249 2
= 18.129
Slack = Data Required time - Data arrival time
= 18.129 1.412 = 16.717 ns
21
Example of Timing report (CTE)

report_timing -from in0 -to ff1 -late
Path 1: MET Setup Check with Pin ff1/CK
Endpoint: ff1/D (^) checked with leading edge of 'clk1'
Beginpoint: in0 (v) triggered by leading edge of 'clk1'
Other End Arrival Time
0.378
- Setup
0.249
+ Phase Shift
20.000
- Uncertainty
2.000
= Required Time
18.129
- Arrival Time
1.412
= Slack Time
16.717
Clock Rise Edge
0.000
+ Input Delay
1.000
+ Source Insertion Delay
0.300
= Beginpoint Arrival Time
1.300
22
How STA tools analyze Timing

Example (hold Analysis):
0
In0
0.033
0.033
0.0
0.033
0.0
0.020 0.050
source latency =0.3 ns Constraints
thold = 0.15
0.0
D
Clock Period = 20ns

Input Delay = 1ns
Uncertainty = 2 ns
ff1
clk1
From Library
Data Arrival time = 0.3 + 1.0 + 0.033 + 0.033 +0.033

= 1.399
Data Required time = 0.3 + 0.020 + 0.050 + 0.15 + 2
=2.385
Slack = Data Arrival time - Data Req time
= 1.399 2.385 = -0.986 ns (violated)
23
Timing Analysis Modes

Single
Best case- Worst case (BC-WC)
On-Chip Variation (OCV)
24
Late path & Early path
path 1
FF1
D
FF2
Q
5/3
5/3
5/3
5/3
D
CK
5/3
path2
5/3
CK
CLK
Path 1 is late path
Path 2 is early path
25

Single Timing Analysis mode :
In this mode tool uses single set of delays using one library based on
one set of process , temperature and voltage conditions.
FF1
D
FF2
Q
CK
CLK
26
CK
For setup :
Lunch clock
Data path
Capture clock
: late path
: late pat
: early path
For Hold :
Lunch clock
Data path
Capture clock
: early path
: early path
: late path

Performing Timing Analysis in Single Timing Analysis mode
read_lib stdwst.lib
set_op_cond worst -library stdwst
set_analysis_mode single -setup
report_timing
set_op_cond best -library stdwst
Set_analysis_mode single -hold
report_timing
27

BC-WC Timing Analysis mode :
In this mode tool uses two operating conditions and checks both
operating condition in one timing analysis run
FF1
D
FF2
Q
CK
CLK
28
CK
For setup :
Lunch clock
Data path
Capture clock
: late path from max lib

: late path from max lib
: early path from max lib
For Hold :
Lunch clock
Data path
Capture clock
: early path from min lib

: late path from min lib
Example (BC-WC)
Example:
FF1
D
0.6 / 0.4
CLK
Q
2.5 /2
CK
0.7 / 0.5
FF2
3.5 / 3
CK
0.5 / 0.3
clock period = 4
Launch clock late path delay (max) = 0.7 + 0.6 = 1.3
Data late path delay (max) = 3.5
Capture clock early path delay (max) = 0.7 + 0.5 = 1.2
Setup = 0.2
Data arrival time = 1.3 + 3.5 = 4.8
Data required time = 4 + 1.2 - 0.2 = 5.0
Slack =5 - 4.8 = 0.2 (met)
29

BC-WC Timing Analysis mode :
read_lib max stdwst.lib min stdbest.lib
set_op_cond -max wccom -maxLibrary stdwst -min bccom -minLibrary stdbest
set_analysis_mode -bcWc
report_timing -late
30

OCV Timing Analysis mode :
On-chip variation considers that cells and nets can operate at

different operating conditions
early paths are computed using the delay of the min operating
condition
late paths are computed using the delay of the max operating
condition
31

OCV Timing Analysis mode :
FF1
D
0.6 / 0.4
CLK
0.7 / 0.5
FF2
3.5 / 3
D
Q
2.5 /2
CK
CK
0.5 / 0.3
For setup :
Lunch clock path : late path delay from max lib
Data Path
: late path delay from max lib
Capture Clock path : early path from min lib
For Hold Analysis:
Lunch clock path
Data Path
Capture Clock path : late path from max lib
32
Example (OCV)
FF1
D
0.6 / 0.4
CLK
0.7 / 0.5
FF2
3.5 / 3
D
Q
2.5 /2
CK
CK
0.5 / 0.3
clock period = 4
Capture clock early path delay (min) = 0.5 + 0.3 = 0.8
Flipflop Setup = 0.2
Data required time = 4 + 0.8 - 0.2 = 4.6
Slack = 4.6- 4.8 = -0.2 (violated)
33

OCV Timing Analysis mode : With two lib
read_lib max stdwst.lib min stdbest.lib
set_op_cond -max wccom -maxLibrary stdwst -min bccom -minLibrary stdbest
set_analysis_mode -onChipVariation
report_timing -late
34

OCV Timing Analysis mode : With derating factor
read_lib stdwst.lib
set_op_cond wccom library stdwst
set_analysis_mode -onChipVariation
set_timing_derate -early 0.8 -late 1.0
report_timing -late
35
Clock Path Pessimism Removal

CPRR is the process of identifying and removing pessimism introduced in the
slack reports in the clock path when the clock path have a segment in
common
FF1
D
0.6 / 0.4
CLK
0.7 / 0.5
FF2
3.5 / 3
D
Q
2.5 /2
CK
CK
0.5 / 0.3
Example :
set_analysis_mode onChipVariation -crpr
36
Example (CRPR)
FF1
D
0.6 / 0.4
CLK
Q
2.5 /2
CK
0.7 / 0.5
FF2
3.5 / 3
CK
0.5 / 0.3
clock period = 4
Capture clock early path delay (min) = 0.5 + 0.3 = 0.8
Flipflop Setup = 0.2
Data required time = 4 + 0.8 - 0.2 + 0.2 = 4.8
Slack = 4.8 - 4.8 = 0 (met)
37
Clock Path Pessimism Removal

Flow:
load design, sdc, library
set_analysis_mode -onChipVariation -cppr
set_timing_derate -late 1 -early 0.9 -clock
report_timing
38
Result before CRPR

Path 1: Violated Setup Check with Pin reg_2/CK
Endpoint:
reg_2/D (v) checked with leading edge of 'CLK1'
Beginpoint: reg_1/Q (v) triggered by leading edge of 'CLK1'
0.800
- Setup
0.200
+ Phase Shift
4.000
= Required Time
4.600
- Arrival Time
4.800
= Slack Time
-0.200
Clock Rise Edge
0.000
0.000
39
Result after CRPR

Path 1: MET Setup Check with Pin reg_2/CK
Endpoint:
reg_2/D (v) checked with leading edge of 'CLK1'
Beginpoint: reg_1/Q (v) triggered by leading edge of 'CLK1'
0.800
- Setup
0.200
+ Phase Shift
4.000
+ CPPR Adjustment
0.200
= Required Time
4.800
- Arrival Time
4.800
= Slack Time
0.000
Clock Rise Edge
0.000
0.000
40
Summary
STA overviewSTA flow with example script
Timing Constraints
clock latency
clock uncertainty
input/output delay
false path
multicycle path
Timing analysis modes
Single
BC-WC
OCV
CRPR
41
Few Guidelines
Dont use combinational feedback in your design.
Most STA tools does not analyze the combinational

feedback path.
Synchronous flip flop based designs are very easy for

timing analysis.
Transparent latches present unique challenges for static

timing analysis tool.
Cycle stealing or time borrowing technique is used for

timing analysis of latch based design.
Avoid Gated clocks and internally generated clock , if

possible.
If you have to use gated clock, check for any glitches in

the gated clock.
42
THANKS
43

DDD

Uploaded by

Document Information

Original Title

Copyright

Available Formats

Share this document

Share or Embed Document

Sharing Options

Did you find this document useful?

Is this content inappropriate?

Copyright:

Available Formats

DDD

Uploaded by

Copyright:

Available Formats

STATIC TIMING ANALYSIS

Dynamic Timing Simulation

These involves three main steps -

Design is broken into sets of timing paths

The delay of each path is calculated

All path delays are compared to see if timing constraints have

Example script for ETS

Timing constraints are use to set Speed of Design ( clock frequency)

boundary condition ( input delay, output delay)

Link for constraints :

Link for constraints :

Default latency type

set_clock_uncertainty -from clk1 -to clk2 -rise -hold 2.0

With set_input_delay = 0.8

It is required to specify the false path, so that tool will

Example : set_false_path from U1/a to U5/y

A multicycle path is a path that is not expected

By default all paths are constrained for single

Specify multicycle path explicitly if required

Example : set_multicycle_path 2 from ff1 to ff2

Example : (how to constrain)

create_clock -name clk1 -period 20 -waveform {0 10} [get_ports {ck}]

How STA tools analyze Timing

Clock Period = 20ns

source latency =0.3 ns Constraints

tsetup = 0.249 From Library

Data Arrival time = 0.3+ 1.0 + 0.037 + 0.037 +0.037

Example of Timing report (CTE)

How STA tools analyze Timing

source latency =0.3 ns Constraints

Clock Period = 20ns

Data Arrival time = 0.3 + 1.0 + 0.033 + 0.033 +0.033

Timing Analysis Modes

Late path & Early path

Timing Analysis Modes

Timing Analysis Modes

Timing Analysis Modes

: late path from max lib

: early path from min lib

Timing Analysis Modes

set_op_cond -max wccom -maxLibrary stdwst -min bccom -minLibrary stdbest

Timing Analysis Modes

On-chip variation considers that cells and nets can operate at

Timing Analysis Modes

Timing Analysis Modes

set_op_cond -max wccom -maxLibrary stdwst -min bccom -minLibrary stdbest

Timing Analysis Modes

Clock Path Pessimism Removal

Clock Path Pessimism Removal

Result before CRPR

Result after CRPR

Dont use combinational feedback in your design.

Most STA tools does not analyze the combinational

Synchronous flip flop based designs are very easy for

Transparent latches present unique challenges for static

Cycle stealing or time borrowing technique is used for

Avoid Gated clocks and internally generated clock , if

If you have to use gated clock, check for any glitches in

You might also like