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Classe D Tutorial PDF
Classe D Tutorial PDF
Gate Driver
How to drive the gate, key parameters in gate
drive stage
MOSFET
How to choose, tradeoff relationships, loss calculation
Package
Importance of layout and package, new packaging
technology
Design Example
200W+200W stereo Class D amplifier
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Prepared Oct.8 2003 by Jun Honda and Jorge Cerezo
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Vcc
Error amp
Bias
Vcc
Feed back
Triangle
+V C C
Nch
Level Shift
Error Amp
COMP
Dead Time
Nch
-V C C
COMP
Class D
switching stage
LPF
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Efficiency
Output
Output
Gain
Proportional to
Vbus
PSRR
0 dB
Direction of
energy flow
Both way
Creates Vbus pumping
phenomena
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Class D Amplifier
Fc of LPF is above
20KHz
Gate Driver
Gate Driver
Q1
MOSFET
Q1
MOSFET
3
2
1
INDUCTOR
U1A
L1
L1
+
1
INDUCTOR
U1A
ERROR AMP
ERROR AMP
C1
CAPACITOR
Vref
C1
CAPACITOR
R1
LOAD
R1
LOAD
Q2
MOSFET
Q2
MOSFET
Loss
2
Pc = 0.2
Loss in class AB
VCC
8 RL
Vcc
1
(1 K sin t ) Vcc K sin t d t
PC =
2 0 2
2 RL
Vcc 2
=
8 RL
2K K 2
Regardless of output
device parameters.
K=2/
K=1
Loss
Loss in Class D
Efficiency can be
improved further!
RDS (ON )
RL
Po
2
K=1
0.5 x 2ch
Current ratings
MOSFET
2 MOSFETs/CH
4 MOSFETs/CH
Gate Driver
1 Gate Driver/CH
2 Gate Drivers/CH
Linearity
DC Offset
Adjustment is needed
PWM pattern
2 level
Notes
Pumping effect
Need a help of feed back
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Audio source
PWM
+V C C
Gate Driver
-V C C
Dead time
Delay time
Finite RDS(on)
Vth and Qg
Body diode recovery
R DS(ON)
ON delay
OFF delay
Finite dV/dt
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ON
High Side
OFF
ON
Low Side
OFF
34
40
30
20
10
Vout( t )
Falling edges
0
10
20
THD=2.1%
THD=0.18%
30
34 40
0
0
5 .10
Low
0.001Side edges
0.0015
t
0.002
0.0021
THD =
V2 + V3 +
V fundamental
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( O v e r la p t im e m e a s u r e d f r o m 5 0 % V g s h ig h s id e f a ll t o 1 0 % V g s lo w s id e r is e )
120
80
R g=1O hm s
60
R g=5O hm s
rg=10O hm s
40
20
0
-10
-5
10
15
20
O v e r la p tim e (n s )
Commutation
current
-Vcc
VBUS max =
Half Bridge
Load Current
VBUS
8 f PWM RLOAD C BUS
Full Bridge
Commutation
current
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1.
2.
3.
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Input Logic
High side well
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Discharge
ON
ON
When Vs is pulled down to ground through the low side FET, the bootstrap capacitor (CBOOT)
charges through the bootstrap diode (Dbs) from the Vcc supply, thus providing a supply to
Vbs.
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To minimize the risk of overcharging and further reduce ripple on the Vbs voltage the
Cbs value obtained from the above equation should be should be multiplied by a factor
of 15 (rule of thumb).
PG = V f SW QG
For two IRF540 HEXFET MOSFETs operated at 400kHz with Vgs = 12V, we
have:
PG = 2 12 37 10-9 400 103 = 0.36W
R3
High Side
R3
High Side
SW1
SW1
R2
Low Side
C1
Ciss
R2
Low Side
C1
Ciss
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150.00
200
125.00
100.00
Junction Tem perature (C )
100
10
75.00
50.00
25.00
0.00
1.E +03
1.E +04
1.E +05
1.E +06
Frequency (H z)
Figure 32: IR 2010S Tj vs Frequency
R G ATE = 10 O hm , V cc = 15V w ith IR FP E50
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Layout Considerations
IR2011
IR2011(S)
SO-8
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Trench Technology
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Key
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VBDSS min =
2 * POUT * RLOAD
* 1.5
M
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(1)
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(2)
MOSFET Turn-On
MOSFET Turn-Off
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Qg tSWITCHING PSWITCHING
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Esw =
VDS(t) * ID(t) dt
POUT
RLOAD
Thermal Design
Pmax = (Tamb Tjmax ) / (Rthjc max + Rthcs max + Rths max + Rthsa max)
Where: Tamb = Ambient Temperature
Tjmax = Max. Junction Temperature
Rthjc max = Max. Thermal Resistance Junction to Case
Rthcs max = Max. Thermal Resistance Case to Heatsink
Rths max = Max. Thermal Resistance of Heatsink
Rthsa max = Max. Thermal Resistance Heatsink to Ambient
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RDS(ON) vs Qg
There is tradeoff between Static Drain-to-Source OnResistance, RDS(ON) and Gate charge, Qg
Higher RDS(ON) Lower Qg Higher PCONDUCTION & Lower PSWITCHING
Lower RDS(ON) Higher Qg Higher PSWITCHING & Lower PCONDUCTION
Gen 7.5 100V MOSFET Platform
RDS(ON) vs. Qg
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Total Loss
Conduction
Loss
Switching
Loss
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Drain and source stray inductances reduces the gate voltage during
turn-on resulting in longer switching time.
Also during turn-off, drain and source stray inductances generate a
large voltage drop due to dID/dt, producing drain to source overvoltage transients.
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DirectFET Packaging
Use a single multiple-finned heat sink
to dissipate heat from devices
passivated die
copper drain clip
gate connection
DirectFET devices
source connection
copper track on board
Circuit board
4.
8m
Both Side
Cooling
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DirectFET Packaging
DirectFET waveform
SO-8 waveform
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Feed back
+V C C
Integrator
Level Shifter
LT1220
2N5401
LPF
IR2011S
Gate Driver
GND
Comparator
IRFB23N15D
74HC04
-V C C
-VCC
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Circuit Diagram
1
CH1
R1
R3
47K
1K
TP3
PAD
R4
GNDP
Q1
1K
8
7
6
5
1
2
3
4
8
7
6
5
HO
VB
6
LT1220CS8
TC7WH04FU
MMBT5401
TC7WH08FU
Q9
MMBT3904
B
C?
.01uF, 50V
R41
100K
TP4
PAD
Quantize
Hin
COM
LO
TP
R13
C26
10K
0.1uF,50V
3.3uF, 35V
GNDP
GNDP
VS
C
C42
GNDP
Lin
VCC
GNDP
1
2
3
4
R31
3
C23
0.33uF, 25V
D10
R39
1
IRFB23N15D
MURS120
L1
C38
GNDP
GNDP
CH1 OUT
RLY1A
J5
8
18uH
R49
4.7
MA2YD23
D7
Gate Driver
R50
IR2011
R64
10
9.1
C31
470uF, 50V
LPF
C30
Q5
0.22uF, 100V
U1
U6
9.1
D14
MURS120DICT
C49
Q6
D11
IRFB23N15D
MURS120
GNDP
R53 R54 R55 R56
dummy
dummy
dummy
dummy
1
2
255-1054 (1)
C51
MKDS5/2-9.5
R61
10, 1W
0.47uF, 100V
MA2YD23
D6
VDD_1
0.22uF, 100V
7
D2
R82
10K
U4
0.1uF, 100V
C9
1uF, 16V
U2
D1
1N4148
10K
-50V
GNDP
22K
R26
1K
1
8
C6
R10
dummy
C3
R8 10uF, 50V
330K
1N4148
1418-ND
MMBT5401
R28
PROTECT
TP
R11
10K
C18
1000pF, 100V
R21
5K
J1
GNDP
Input analog
MKDS5/3-9.5
R12
10K
470
100
1
2
3
0.1uF, 50V
Q2
J3
R37
47mOHM, 2W
C25
0.01uF
R35
Integrator
C17
1000pF, 100V
R23
Over Current
GNDP
Level Shift
GNDP
+50V
C1
220pF, 100V
+5V
C8
GNDP
Speaker output
C33
0.22uF, 100V
GNDP
-5V
R44
4.7K
SD1
R47
10
C44
Snubber
1uF, 16V
GNDP
GNDP
-50_1
GNDP
Sheet 2
of 4
File:
2
C39
Title
Drawn by:
C32
470uF, 50V
R14
10K
-50+VCC
0.22uF, 100V
dummy
C19
Number:
INTERNATIONAL RECTIFIER
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Revision:1.0
Approved by:
1. ClassD_Refbd_R2-0_CH1.~ch
Date: 23-Sep-2003
4
Time: 15:13:04
Protection
Analog Input
(CH2)
(CH2)
Bus Capacitor
Modulator
HeatSink
5V
Regulator
MOSFET
(CH1)
MOSFET
(CH1)
Gate Driver
Analog Input
Gate Driver
Modulator
LPF
(CH1)
LPF
(CH2)
Speaker
(CH1)
Speaker
(CH2)
+12V DC/DC
Power Supply
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Performance
50W / 4, 1KHz, THD+N=0.0078%
10
HP8903B
CH1, f=1KHz, RL=4
VCC=50.0V
fPWM=426KHz
THD 0.1
0.01
3
7.5101 .10 3
0.1
0.16
10
100
Output_Power
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1 .10
342.3
Performance (Contd)
Switching waveform
10
10
1 VCC=50.0V
fPWM=364KHz
THD 0.1
0.01
3
7.1101 .10 3
10
20
100
1 .10
Frequency
1 .10
1 .10
4
210
LPF
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Conclusion
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