Code No.

A0601
JAWAHARLAL NEHRU TECHNOLOGY UNIVERSITY, HYDERABAD
M.Tech. I Semester Regular Examinations, March 2009
DIGITAL SYSTEM DESIGN
(Common to Digital Systems & Computer Electronics, Digital
Electronics & Communications Systems and VLSI System Design)
Time: 3 hours

Max. Marks.60
Answer any Five questions
All questions carry equal marks
---

1.a)

b)
2.a)
b)

Design a FSM that counts the following decimal sequence.

3,7,2,6,3,7,2,6,.
The count is to be represented directly by the contents of the D
flip-flops. The counting starts when the control in put C is
asserted and stops whenever C is deasserted. Assume that the
next state from all unused states is the state for the first count in
the sequence.
How does the ASM chart differ from a software flow chart?
Draw the general structure of a CPLD and explain how a logic
function can be realized on CPLD with simple example.
Design a four-way traffic light controller that will keep traffic
moving efficiently along two busy streets that intersect. Implement
the controller using PALS.

3.a)

Using the path-sensitization method and Boolean difference

method find the test vectors for SAO fault on input line 1 and SA1
fault on the internal line 2 of the circuit shown in figure.

b)

Draw the table giving the set of all possible single struck faults and
the faulty and fault-free responses and also construct the fault
cover table for the circuit in figure.

Contd.2

Code No. A0601

::2::

4.a)

The response of the machine shown in table 1 below to an un

known input sequence is give to the experimenter. Devise a
procedure that the experimenter may use in order to identify the
initial state. What are the minimum-length sequences that will
make such an identification possible?
Table 1
NS
PS
x = 0 x =1
A
A, 0 B, 0
B
C, 0 D, 0
C
D. 1 C. 1
D
B. 1 A.1
b) Discuss the different types of faults in a digital circuits.

5.a)

Find a minimized PLA of the following multiple-output Boolean

function on the map. Calculate the area and number of cross
points in the given and minimized PLA. Hence calculate the
improvement in area reduction and cross point compaction.
b) What is the difference between PAL and PLA programming
structure.

6.

A fundamental mode sequential machine has two inputs, x1 and

x2, and two outputs, z1 and z2. z1 becomes 1 when x1 changes its
value preceded by a change in value in x2. z2 becomes 1 when x2
changes its value preceded by a change in value in x1. once 1,
both z1 and z2 return to 0 only when both x1 and x2 become 0.
(i)
Derive a minimum-row state table having fast and flickerfree output
(ii)
Show a valid assignment (race-free) and write a set of (static)
hazard-free exitation and output equations.
(iii) Implement the circuit.

7.a)
b)

Discuss the BIST scheme for PLD and CPLDs

Plot the following PLA on the map. Identify the undetectable
faults. Derive a minimal test set for all detectable faults.
x1
1
2
1
0

8.

Write
a)
b)
c)

x2
2
0
1
1

x3
0
1
0
1

x4
1
1
2
0

a short note on any two

Races, cycles and hazards
Design for testability
Field programmable gate arrays
*-*-*

z1
1
1
1
0

z2
0
0
1
1