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1 Introduction PDF
1 Introduction PDF
Microprocessors
Introduction
1.1
Assembly Language
Decimal digits: 0, 1, 2, 3, 4, 5, 6, 7, 8, 9
Binary digits: 0, 1
The
1.2
Assembly Language
Decimal
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Binary
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
1.3
Hexadecimal
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
Assembly Language
Quotient
Remainder
35/2
17
17/2
8/2
4/2
2/2
1/2
1 (MSB)
(100011.0)2
(35)10 = (100011)2
The 80x86 Microprocessors
1.4
Assembly Language
0.7
0 (MSB)
0.7*2
0.4
0.4*2
0.8
0.8*2
0.6
0.6*2
0.2
0.2*2
0.4
0 (LSB)
(0.01011)2
(0.35)10 = (0.010110)2
1.5
Assembly Language
3102
1101
5100
3100
110
51
1.6
Assembly Language
125
124
023
122
021
120
132 + 116 + 08 + 14 + 02 + 11
(110101)2 = (53)10
1.7
Assembly Language
12-1
12-2
02-3
12-4
02-5
12-6
1.8
Assembly Language
1001
9
1111
F
0101
5
2
0010
9
1001
B
1011
1.9
Assembly Language
2/16
Remainder
13 (hex D)
2
(L.S.D)
(M.S.Digit)
1.10
Assembly Language
(129+128+027+126+025+124+123+022+022+121+020)10 =
(1714)10
2. Convert directly from hex to decimal by summing the weight of all
digits.
1.11
Assembly Language
Ci
Carry
Sum
(1010100)2 + (1100100)2 = ?
1010100
1100100
__________
10111000
000100
1.12
Assembly Language
Signed Addition
Add the following signed binary numbers
(01010100)2 + (01100100)2 = ?
01000100
ERROR
01010100
+84
01100100
+100
__________
10111000
-72
1.13
Assembly Language
Unsigned Subtraction
There is no separate circuitry for subtractors.
Instead, adders are used in conjunction with 2's complement circuitry to
perform subtraction.
To implement "x - y", the computer takes the 2's complement of y and
adds it to x.
1100100 1010000 (note that each number has the same number of
digits)
1010000 - 1100100
1.14
Assembly Language
Signed Subtraction
Example: Subtract the following signed numbers (100 80 = 20)
(+100) (+80)
01100100 01010000
(+80) (+100)
01010000 - 01100100
1.15
Assembly Language
ASCII Code
ASCII: American Standard Code for Information Interchange
The great advantage of this system is that it is used by most computers,
1.16
Assembly Language
Note That
The pattern of ASCII codes was designed to allow for easy manipulation
of ASCII data.
Looking at the binary code, the only bit that is different between
1.17
Assembly Language
1.18
Assembly Language
parts:
1.
2.
3.
The CPU is connected to memory and I/O through strips of wire called a
bus. The bus inside a computer carries information from place to place
1.19
Assembly Language
Computer Buses
Address Bus, Data Bus, and Control Bus.
Address bus,
The number of address buses for a CPU determines the number of locations
with which CPU can communicate.
A CPU with 16 address lines can provide a total of 65,536 (2 16) or 64K, bytes
of addressable memory. Each location can have a maximum of 1 byte of data.
The average size of data buses in CPUs varies between 8 and 64.
Data buses are bidirectional, since the CPU must use them either to receive or
to send data.
The processing power of a computer is related to the size of its buses, since an
8-bit bus can send out one byte a time, but a 16-bit bus can send out 2 bytes at
a time, which is twice as fast.
Control bus: used to provide read or write signals to the device to indicate if the
CPU is asking for information or sending it information.
1.20
Assembly Language
For the CPU to process information, the data must be stored in RAM or ROM.
The CPU gets the information to be processed, first from RAM (or ROM).
Only if it is not there does the CPU seek it from a mass storage device such as a
disk, and then it transfers the information to RAM.
For this reason, RAM and ROM are sometimes referred to as primary memory and
disks are called secondary memory.
1.21
Assembly Language
CPU
Fetches instructions from memory
Executes fetched instructions
Assembly Language
The x86
Microprocessors
1.23
Assembly Language
Processor
Architecture
Applications
Technology
The 80x86 Microprocessors
1.24
Assembly Language
~ 30 years
Pentium 4, 2001
55 Million Transistors
1.5 GHz
4004, 1971
2300 Transistors
108 kHz
1.25
Assembly Language
8088
80286
80386
80486
Year
1982
1985
1989
1992
1995
MHz
.108 .5-.8
Pentium P. Pro
2-3
3-8 5-10
5-8
6-16
16-33
25-50
60, 66
150
273
387
18
18
40
40
40
40
68
132
168
# Tran K
2.9
4.5
6.5
29
29
130
275
1,200
Memory
4K
16K
64K 64K
1M
1M
16M
4G
4G
4G
64G
Int.
16
16
16
32
32
32
32
Ext.
16
16
32
32
64
64
Add bus
16
16
20
20
24
32
32
32
36
Data type
Data bus
# Pins
8, 16 8, 16
1.26
8, 16
3,100 5,500
8, 16,
32
Assembly Language
2.
3.
In a system with pipelining, the data and address buses are busy
transferring data while the CPU is processing information, thereby
increasing the effective processing power of the microprocessor.
1.27
Assembly Language
externally
All registers are 16 bits wide and there is a 16-bit data bus to transfer
data in and out of the CPU.
A printed circuit board with a 16-bit data bus was much more expensive.
1.28
Assembly Language
Virtual memory
Real
of 1 megabyte of memory.
Protected
1.29
Assembly Language
32-bit Microprocessor
In 1985 Intel introduced the 80386 (sometimes called 80386DX), internally
4 gigabytes (232).
Later Intel introduced the 386SX, which is internally identical to the 80386
but has a 16-bit external data bus and a 24-bit address bus which gives a
capacity of 16 megabytes (224) of memory.
cheaper.
With the introduction of the 486 in 1989, Intel put a greatly enhanced
version of the 386 and the math coprocessor on a single chip plus
additional features such as cache memory.
1.30
Assembly Language
Pentium
In 1992 Intel introduced the Pentium.
The Pentium had speeds of 60 and 66 MHz, but new design features
memory.
In 1995 Intel introduced the Pentium Pro, the sixth generation of the x86
family.
1.31
Assembly Language
Pipelining
There are two ways to make the CPU process information faster:
1.
2.
The first option is technology dependent, meaning that the designer must
The second option for improving the processing power of the CPU has to
given time.
Fetch
Execute
1.32
Fetch
Execute
Assembly Language
Pipelining (Cont.)
The idea of pipelining in its simplest form is to allow the CPU to fetch and
Fetch
Execute
Fetch
Execute
Fetch
Fetch
2-stage pipeline
Execute
Fetch
Fetch
Non pipelined
Execute
Execute
Decode
Execute
Fetch
Decode
Execute
Fetch
Decode
1.33
3-stage pipeline
Execute
Assembly Language
These two sections work simultaneously. The BIU accesses memory and
This works only if the BIU keeps ahead of the EU; thus the BIU of the
The buffer is 4 bytes long in the 8088 and 6 bytes in the 8086.
If any instruction takes too long to execute, the queue is filled to its
The BIU fetches a new instruction whenever the queue has room for 2
bytes in the 6-byte 8086 queue, and for 1 byte in the 4-byte 8088 queue.
1.34
Assembly Language
address
generation and
bus control
1.35
Assembly Language
8088/86 Registers
Registers: used to store information temporarily.
Information: data (8/16-bit) to be processed or the address of data.
14
Six
categories
Category
Bits
Register Names
16
Pointer
16
Index
16
Segment
16
Instruction
16
IP (instruction pointer)
Flag
16
FR (flag register)
General
1.36
Assembly Language
8-bit/16-bit Registers
8-bit registers
16-bit registers
1.37
Assembly Language