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Pic18f2331 PDF
Data Sheet
28/40/44-Pin Enhanced Flash
Microcontrollers with nanoWatt Technology,
High-Performance PWM and A/D
DS39616D
Note the following details of the code protection feature on Microchip devices:
Microchip products meet the specification contained in their particular Microchip Data Sheet.
Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchips Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
Microchip is willing to work with the customer who is concerned about the integrity of their code.
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as unbreakable.
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchips code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Trademarks
The Microchip name and logo, the Microchip logo, dsPIC,
KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, PICSTART,
PIC32 logo, rfPIC and UNI/O are registered trademarks of
Microchip Technology Incorporated in the U.S.A. and other
countries.
FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor,
MXDEV, MXLAB, SEEVAL and The Embedded Control
Solutions Company are registered trademarks of Microchip
Technology Incorporated in the U.S.A.
Analog-for-the-Digital Age, Application Maestro, CodeGuard,
dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN,
ECONOMONITOR, FanSense, HI-TIDE, In-Circuit Serial
Programming, ICSP, Mindi, MiWi, MPASM, MPLAB Certified
logo, MPLIB, MPLINK, mTouch, Octopus, Omniscient Code
Generation, PICC, PICC-18, PICDEM, PICDEM.net, PICkit,
PICtail, REAL ICE, rfLAB, Select Mode, Total Endurance,
TSHARC, UniWinDriver, WiperLock and ZENA are
trademarks of Microchip Technology Incorporated in the
U.S.A. and other countries.
SQTP is a service mark of Microchip Technology Incorporated
in the U.S.A.
All other trademarks mentioned herein are property of their
respective companies.
2010, Microchip Technology Incorporated, Printed in the
U.S.A., All Rights Reserved.
Printed on recycled paper.
ISBN: 978-1-60932-490-2
Microchip received ISO/TS-16949:2002 certification for its worldwide
headquarters, design and wafer fabrication facilities in Chandler and
Tempe, Arizona; Gresham, Oregon and design centers in California
and India. The Companys quality system processes and procedures
are for its PIC MCUs and dsPIC DSCs, KEELOQ code hopping
devices, Serial EEPROMs, microperipherals, nonvolatile memory and
analog products. In addition, Microchips quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.
DS39616D-page 2
PIC18F2331/2431/4331/4431
28/40/44-Pin Enhanced Flash Microcontrollers with
nanoWatt Technology, High-Performance PWM and A/D
14-Bit Power Control PWM Module:
Power-Managed Modes:
Peripheral Highlights:
Up to 9 Channels
Simultaneous, Two-Channel Sampling
Sequential Sampling: 1, 2 or 4 Selected Channels
Auto-Conversion Capability
4-Word FIFO with Selectable Interrupt Frequency
Selectable External Conversion Triggers
Programmable Acquisition Time
Data Memory
SSP
I/O
10-Bit
CCP
A/D (ch)
SPI
Slave EUSART
I2C
Quadrature
Encoder
14-Bit
Timers
PWM
8/16-Bit
(ch)
PIC18F2331
8192
4096
768
256
24
1/3
PIC18F2431
16384
8192
768
256
24
1/3
PIC18F4331
8192
4096
768
256
36
1/3
PIC18F4431
16384
8192
768
256
36
1/3
DS39616D-page 3
PIC18F2331/2431/4331/4431
Pin Diagrams
28-Pin SPDIP, SOIC
28
RB7/KBI3/PGD
RA0/AN0
27
RB6/KBI2/PGC
RA1/AN1
26
RB5/KBI1/PWM4/PGM
RA2/AN2/VREF-/CAP1/INDX
25
24
RB4/KBI0/PWM5
RA3/AN3/VREF+/CAP2/QEA
4
5
RA4/AN4/CAP3/QEB
23
RB2/PWM2
AVDD
7
8
22
21
RB1/PWM1
AVSS
PIC18F2331/2431
MCLR/VPP
RB3/PWM3
RB0/PWM0
VDD
20
19
VSS
OSC2/CLKO/RA6
9
10
RC0/T1OSO/T1CKI
11
18
RC7/RX/DT/SDO
RC1/T1OSI/CCP2/FLTA
12
13
14
17
16
15
RC6/TX/CK/SS
OSC1/CLKI/RA7
RC2/CCP1
RC3/T0CKI/T5CKI/INT0
RC5/INT2/SCK/SCL
RC4/INT1/SDI/SDA
28
27
26
25
24
23
22
RA1/AN1
RA0/AN0
MCLR/VPP
RB7/KBI3/PGD
RB6/KBI2/PGC
RB5/KBI1/PWM4/PGM
RB4/KBI0/PWM5
28-Pin QFN(1)
PIC18F2331
PIC18F2431
8
9
10
11
12
13
14
1
2
3
4
5
6
7
21
20
19
18
17
16
15
RB3/PWM3
RB2/PWM2
RB1/PWM1
RB0/PWM0
VDD
VSS
RC7/RX/DT/SDO
RC0/T1OSO/T1CKI
RC1/T1OSI/CCP2/FLTA
RC2/CCP1
RC3/T0CKI/T5CKI/INT0
RC4/INT1/SDI/SDA
RC5/INT2/SCK/SCL
RC6/TX/CK/SS
RA2/AN2/VREF-/CAP1/INDX
RA3/AN3/VREF+/CAP2/QEA
RA4/AN4/CAP3/QEB
AVDD
AVSS
OSC1/CLKI/RA7
OSC2/CLKO/RA6
Note
1:
For the QFN package, it is recommended that the bottom pad be connected to VSS.
DS39616D-page 4
PIC18F2331/2431/4331/4431
Pin Diagrams (Continued)
MCLR/VPP/RE3
RA0/AN0
RA1/AN1
RA2/AN2/VREF-/CAP1/INDX
RA3/AN3/VREF+/CAP2/QEA
RA4/AN4/CAP3/QEB
RA5/AN5/LVDIN
RE0/AN6
RE1/AN7
RE2/AN8
AVDD
AVSS
OSC1/CLKI/RA7
OSC2/CLKO/RA6
RC0/T1OSO/T1CKI
RC1/T1OSI/CCP2/FLTA
RC2/CCP1/FLTB
RC3/T0CKI(1)/T5CKI(1)/INT0
RD0/T0CKI/T5CKI
RD1/SDO
Note 1:
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
PIC18F4331/4431
40-Pin PDIP
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
RB7/KBI3/PGD
RB6/KBI2/PGC
RB5/KBI1/PWM4/PGM
RB4/KBI0/PWM5
RB3/PWM3
RB2/PWM2
RB1/PWM1
RB0/PWM0
VDD
VSS
RD7/PWM7
RD6/PWM6
RD5/PWM4(3)
RD4/FLTA(2)
RC7/RX/DT/SDO
RC6/TX/CK/SS
RC5/INT2/SCK(1)/SCL(1)
RC4/INT1/SDI(1)/SDA(1)
RD3/SCK/SCL
RD2/SDI/SDA
RC3 is the alternate pin for T0CKI/T5CKI; RC4 is the alternate pin for SDI/SDA; RC5 is the alternate pin
for SCK/SCL.
2:
3:
DS39616D-page 5
PIC18F2331/2431/4331/4431
Pin Diagrams (Continued)
44
43
42
41
40
39
38
37
36
35
34
RC6/TX/CK/SS
RC5/INT2/SCK(1)/SCL(1)
RC4/INT1/SDI(1)/SDA(1)
RD3/SCK/SCL
RD2/SDI/SDA
RD1/SDO
RD0/T0CKI/T5CKI
RC3/T0CKI(1)/T5CKI(1)/INT0
RC2/CCP1/FLTB
RC1/T1OSI/CCP2/FLTA
NC
44-Pin TQFP
PIC18F4331
PIC18F4431
33
32
31
30
29
28
27
26
25
24
23
12
13
14
15
16
17
18
19
20
21
22
1
2
3
4
5
6
7
8
9
10
11
NC
RC0/T1OSO/T1CKI
OSC2/CLKO/RA6
OSC1/CLKI/RA7
AVSS
AVDD
RE2/AN8
RE1/AN7
RE0/AN6
RA5/AN5/LVDIN
RA4/AN4/CAP3/QEB
NC
NC
RB4/KBI0/PWM5
RB5/KBI1/PWM4/PGM
RB6/KBI2/PGC
RB7/KBI3/PGD
MCLR/VPP/RE3
RA0/AN0
RA1/AN1
RA2/AN2/VREF-/CAP1/INDX
RA3/AN3/VREF+/CAP2/QEA
RC7/RX/DT/SDO
RD4/FLTA(2)
RD5/PWM4(3)
RD6/PWM6
RD7/PWM7
VSS
VDD
RB0/PWM0
RB1/PWM1
RB2/PWM2
RB3/PWM3
Note 1:
RC3 is the alternate pin for T0CKI/T5CKI; RC4 is the alternate pin for SDI/SDA; RC5 is the alternate pin
for SCK/SCL.
2:
3:
DS39616D-page 6
PIC18F2331/2431/4331/4431
Pin Diagrams (Continued)
44
43
42
41
40
39
38
37
36
35
34
RC6/TX/CK/SS
RC5/INT2/SCK(1)/SCL(1)
RC4/INT1/SDI(1)/SDA(1)
RD3/SCK/SCL
RD2/SDI/SDA
RD1/SDO
RD0/T0CKI/T5CKI
RC3/T0CKI(1)/T5CKI(1)/INT0
RC2/CCP1/FLTB
RC1/T1OSI/CCP2/FLTA
RC0/T1OSO/T1CKI
44-Pin QFN(2)
PIC18F4331
PIC18F4431
33
32
31
30
29
28
27
26
25
24
23
12
13
14
15
16
17
18
19
20
21
22
1
2
3
4
5
6
7
8
9
10
11
OSC2/CLKO/RA6
OSC1/CLKI/RA7
VSS
AVSS
AVDD
VDD
RE2/AN8
RE1/AN7
RE0/AN6
RA5/AN5/LVDIN
RA4/AN4/CAP3/QEB
RB3/PWM3
NC
RB4/KBI0/PWM5
RB5/KBI1/PWM4/PGM(2)
RB6/KBI2/PGC
RB7/KBI3/PGD
MCLR/VPP/RE3
RA0/AN0
RA1/AN1
RA2/AN2/VREF-/CAP1/INDX
RA3/AN3/VREF+/CAP2/QEA
RC7/RX/DT/SDO
RD4/FLTA(3)
RD5/PWM4(4)
RD6/PWM6
RD7/PWM7
VSS
VDD
AVDD
RB0/PWM0
RB1/PWM1
RB2/PWM2
Note 1:
RC3 is the alternate pin for T0CKI/T5CKI; RC4 is the alternate pin for SDI/SDA; RC5 is the alternate pin
for SCK/SCL.
2:
For the QFN package, it is recommended that the bottom pad be connected to VSS.
3:
4:
DS39616D-page 7
PIC18F2331/2431/4331/4431
Table of Contents
1.0 Device Overview ........................................................................................................................................................................ 11
2.0 Guidelines for Getting Started with PIC18F Microcontrollers ..................................................................................................... 25
3.0 Oscillator Configurations ............................................................................................................................................................ 29
4.0 Power-Managed Modes ............................................................................................................................................................. 39
5.0 Reset .......................................................................................................................................................................................... 47
6.0 Memory Organization ................................................................................................................................................................. 61
7.0 Data EEPROM Memory ............................................................................................................................................................. 79
8.0 Flash Program Memory .............................................................................................................................................................. 85
9.0 8 x 8 Hardware Multiplier............................................................................................................................................................ 95
10.0 Interrupts .................................................................................................................................................................................... 97
11.0 I/O Ports ................................................................................................................................................................................... 113
12.0 Timer0 Module ......................................................................................................................................................................... 127
13.0 Timer1 Module ......................................................................................................................................................................... 131
14.0 Timer2 Module ......................................................................................................................................................................... 136
15.0 Timer5 Module ......................................................................................................................................................................... 139
16.0 Capture/Compare/PWM (CCP) Modules ................................................................................................................................. 145
17.0 Motion Feedback Module ......................................................................................................................................................... 151
18.0 Power Control PWM Module .................................................................................................................................................... 173
19.0 Synchronous Serial Port (SSP) Module ................................................................................................................................... 205
20.0 Enhanced Universal Synchronous Asynchronous Receiver Transmitter (EUSART) ............................................................... 217
21.0 10-Bit High-Speed Analog-to-Digital Converter (A/D) Module ................................................................................................. 239
22.0 Low-Voltage Detect (LVD)........................................................................................................................................................ 257
23.0 Special Features of the CPU .................................................................................................................................................... 263
24.0 Instruction Set Summary .......................................................................................................................................................... 283
25.0 Development Support............................................................................................................................................................... 325
26.0 Electrical Characteristics .......................................................................................................................................................... 329
27.0 Packaging Information.............................................................................................................................................................. 363
Appendix A: Revision History............................................................................................................................................................. 375
Appendix B: Device Differences......................................................................................................................................................... 375
Appendix C: Conversion Considerations ........................................................................................................................................... 376
Appendix D: Migration from Baseline to Enhanced Devices.............................................................................................................. 376
Appendix E: Migration From Mid-Range to Enhanced Devices ......................................................................................................... 377
Appendix F: Migration From High-End to Enhanced Devices............................................................................................................ 377
INDEX ................................................................................................................................................................................................ 379
The Microchip Web Site ..................................................................................................................................................................... 389
Customer Change Notification Service .............................................................................................................................................. 389
Customer Support .............................................................................................................................................................................. 389
Reader Response .............................................................................................................................................................................. 390
Product Identification System............................................................................................................................................................. 391
DS39616D-page 8
PIC18F2331/2431/4331/4431
TO OUR VALUED CUSTOMERS
It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip
products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and
enhanced as new volumes and updates are introduced.
If you have any questions or comments regarding this publication, please contact the Marketing Communications Department via
E-mail at docerrors@microchip.com or fax the Reader Response Form in the back of this data sheet to (480) 792-4150. We
welcome your feedback.
Errata
An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current
devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision
of silicon and revision of document to which it applies.
To determine if an errata sheet exists for a particular device, please check with one of the following:
Microchips Worldwide Web site; http://www.microchip.com
Your local Microchip sales office (see last page)
When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are
using.
DS39616D-page 9
PIC18F2331/2431/4331/4431
NOTES:
DS39616D-page 10
PIC18F2331/2431/4331/4431
1.0
DEVICE OVERVIEW
PIC18F2331
PIC18F2431
PIC18F4331
PIC18F4431
PIC18LF2331
PIC18LF2431
PIC18LF4331
PIC18LF4431
1.1
1.1.1
On-the-Fly Mode Switching: The powermanaged modes are invoked by user code
during operation, allowing the user to incorporate
power-saving ideas into their applications
software design.
Lower Consumption in Key Modules: The
power requirements for both Timer1 and the
Watchdog Timer have been reduced by up to
80%, with typical values of 1.1 and 2.1 A,
respectively.
1.1.2
DS39616D-page 11
PIC18F2331/2431/4331/4431
1.2
DS39616D-page 12
PIC18F2331/2431/4331/4431
1.3
2.
3.
TABLE 1-1:
The pinouts for all devices are listed in Table 1-2 and
Table 1-3.
Like all Microchip PIC18 devices, members of the
PIC18F2331/2431/4331/4431 family are available as
both standard and low-voltage devices. Standard
devices with Enhanced Flash memory, designated with
an F in the part number (such as PIC18F2331),
accommodate an operating VDD range of 4.2V to 5.5V.
Low-voltage parts, designated by LF (such as
PIC18LF2331), function over an extended VDD range
of 2.0V to 5.5V.
DEVICE FEATURES
Features
PIC18F2331
PIC18F2431
PIC18F4331
PIC18F4431
DC 40 MHz
DC 40 MHz
DC 40 MHz
DC 40 MHz
8192
16384
8192
16384
4096
8192
4096
8192
768
768
768
768
256
256
256
256
34
34
Operating Frequency
Interrupt Sources
22
22
Ports A, B, C
Ports A, B, C
Timers
Capture/Compare/PWM modules
(6 Channels)
(6 Channels)
(8 Channels)
(8 Channels)
1 QEI
or
3x IC
1 QEI
or
3x IC
1 QEI
or
3x IC
1 QEI
or
3x IC
I/O Ports
Serial Communications
SSP,
SSP,
SSP,
SSP,
Enhanced USART Enhanced USART Enhanced USART Enhanced USART
10-Bit High-Speed
5 Input Channels
Analog-to-Digital Converter module
Resets (and Delays)
Ports A, B, C, D, E Ports A, B, C, D, E
5 Input Channels
9 Input Channels
9 Input Channels
POR, BOR,
POR, BOR,
POR, BOR,
POR, BOR,
RESET Instruction, RESET Instruction, RESET Instruction, RESET Instruction,
Stack Full,
Stack Full,
Stack Full,
Stack Full,
Stack Underflow
Stack Underflow
Stack Underflow
Stack Underflow
(PWRT, OST),
(PWRT, OST),
(PWRT, OST),
(PWRT, OST),
MCLR (optional), MCLR (optional), MCLR (optional), MCLR (optional),
WDT
WDT
WDT
WDT
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Instruction Set
75 Instructions
75 Instructions
75 Instructions
75 Instructions
Packages
28-pin SPDIP
28-pin SOIC
28-pin QFN
28-pin SPDIP
28-pin SOIC
28-pin QFN
40-pin PDIP
44-pin TQFP
44-pin QFN
40-pin PDIP
44-pin TQFP
44-pin QFN
DS39616D-page 13
PIC18F2331/2431/4331/4431
FIGURE 1-1:
Table Pointer<21>
8
8
21
Data RAM
(768 bytes)
inc/dec logic
21
Address Latch
RA0/AN0
RA1/AN1
RA2/AN2/VREF-/CAP1/INDX
RA3/AN3/VREF+/CAP2/QEA
RA4/AN4/CAP3/QEB
OSC2/CLKO/RA6
OSC1/CLKI/RA7
Data Latch
Address Latch
20
Program
Memory
PCLATU PCLATH
12
Address<12>
Data Latch
12
BSR
31 Level Stack
16
Decode
Table Latch
PORTB
FSR0
FSR1
FSR2
Bank 0, F
12
inc/dec
logic
RB0/PWM0
RB1/PWM1
RB2/PWM2
RB3/PWM3
RB4/KBI0/PWM5
RB5/KBI1/PWM4/PGM
RB6/KBI2/PGC
RB7/KBI3/PGD
8
ROM Latch
PORTC
IR
Instruction
Decode &
Control
Power-up
Timer
OSC2/CLKO
OSC1/CLKI
Timing
Generation
T1OSI
T1OSO
PRODH PRODL
3
Precision
Band Gap
Reference
8 x 8 Multiply
8
Oscillator
Start-up Timer
Power-on
Reset
4x PLL
RC0/T1OSO/T1CKI
RC1/T1OSI/CCP2/FLTA
RC2/CCP1
RC3/T0CKI/T5CKI/INT0
RC4/INT1/SDI/SDA
RC5/INT2/SCK/SCL
RC6/TX/CK/SS
RC7/RX/DT/SDO
W
8
BITOP
8
8
ALU<8>
Watchdog
Timer
Brown-out
Reset
PORTE
Power-Managed
Mode Logic
MCLR/VPP
INTRC
MCLR/VPP
OSC
VDD, VSS
Timer0
Timer1
Timer2
Timer5
Data EE
CCP1
CCP2
Synchronous
Serial Port
EUSART
DS39616D-page 14
HS 10-Bit
ADC
PCPWM
AVDD, AVSS
MFM
PIC18F2331/2431/4331/4431
FIGURE 1-2:
Table Pointer<21>
8
8
21
RA0/AN0
RA1/AN1
RA2/AN2/VREF-/CAP1/INDX
RA3/AN3/VREF+/CAP2/QEA
RA4/AN4/CAP3/QEB
RA5/AN5/LVDIN
OSC2/CLKO/RA6
OSC1/CLKI/RA7
Data Latch
Data RAM
(768 bytes)
inc/dec logic
21
Address Latch
Address Latch
20
Program Memory
PCLATU PCLATH
12
Address<12>
Data Latch
12
BSR
31 Level Stack
16
Decode
Table Latch
PORTB
FSR0
FSR1
FSR2
Bank 0, F
12
inc/dec
logic
RB0/PWM0
RB1/PWM1
RB2/PWM2
RB3/PWM3
RB4/KBI0/PWM5
RB5/KBI1/PWM4/PGM
RB6/KBI2/PGC
RB7/KBI3/PGD
8
ROM Latch
PORTC
IR
Instruction
Decode &
Control
Power-up
Timer
OSC2/CLKO
OSC1/CLKI
Timing
Generation
T1OSI
T1OSO
PRODH PRODL
3
Power-on
Reset
4x PLL
Precision
Band Gap
Reference
8 x 8 Multiply
8
Oscillator
Start-up Timer
W
8
BITOP
8
PORTD
8
ALU<8>
Watchdog
Timer
Brown-out
Reset
PORTE
RE0/AN6
RE1/AN7
RE2/AN8
INTRC
MCLR/VPP/RE3(1)
OSC
VDD, VSS
Timer0
Timer1
Timer2
Timer5
Data EE
CCP1
CCP2
Synchronous
Serial Port
EUSART
Note 1:
2:
3:
4:
RD0/IT0CKI/T5CKI
RD1/SDO
RD2/SDI/SDA
RD3/SCK/SCL
RD4/FLTA(2)
RD5/PWM4(4)
RD6/PWM6
RD7/PWM7
Power-Managed
Mode Logic
MCLR/VPP
RC0/T1OSO/T1CKI
RC1/T1OSI/CCP2/FLTA
RC2/CCP1/FLTB
RC3/T0CKI/T5CKI/INT0(3)
RC4/INT1/SDI/SDA(3)
RC5/INT2/SCK/SCL(3)
RC6/TX/CK/SS
RC7/RX/DT/SDO
HS 10-Bit
ADC
PCPWM
AVDD, AVSS
MFM
DS39616D-page 15
PIC18F2331/2431/4331/4431
TABLE 1-2:
Pin Name
MCLR/VPP
MCLR
Pin Buffer
SPDIP,
Type
Type
QFN
SOIC
1
26
I
VPP
OSC1/CLKI/RA7
OSC1
P
9
6
I
CLKI
RA7
OSC2/CLKO/RA6
OSC2
ST
I/O
10
Description
7
O
CLKO
RA6
I/O
TTL
RA0/AN0
RA0
AN0
RA1/AN1
RA1
AN1
RA2/AN2/VREF-/CAP1/INDX
RA2
AN2
VREFCAP1
INDX
RA3/AN3/VREF+/CAP2/QEA
RA3
AN3
VREF+
CAP2
QEA
RA4/AN4/CAP3/QEB
RA4
AN4
CAP3
QEB
27
I/O
TTL
I Analog
Digital I/O.
Analog Input 0.
I/O
TTL
I Analog
Digital I/O.
Analog Input 1.
I/O
TTL
I Analog
I Analog
I
ST
I
ST
Digital I/O.
Analog Input 2.
A/D reference voltage (low) input.
Input Capture Pin 1.
Quadrature Encoder Interface index input pin.
I/O
TTL
I Analog
I Analog
I
ST
I
ST
Digital I/O.
Analog Input 3.
A/D reference voltage (high) input.
Input Capture Pin 2.
Quadrature Encoder Interface Channel A input pin.
I/O
TTL
I Analog
I
ST
I
ST
Digital I/O.
Analog Input 4.
Input Capture Pin 3.
Quadrature Encoder Interface Channel B input pin.
28
DS39616D-page 16
PIC18F2331/2431/4331/4431
TABLE 1-2:
Pin Name
Pin Buffer
SPDIP,
Type
Type
QFN
SOIC
Description
PORTB is a bidirectional I/O port. PORTB can be software
programmed for internal weak pull-ups on all inputs.
RB0/PWM0
RB0
PWM0
21
RB1/PWM1
RB1
PWM1
22
RB2/PWM2
RB2
PWM2
23
RB3/PWM3
RB3
PWM3
24
RB4/KBI0/PWM5
RB4
KBI0
PWM5
25
RB5/KBI1/PWM4/PGM
RB5
KBI1
PWM4
PGM
26
RB6/KBI2/PGC
RB6
KBI2
PGC
27
RB7/KBI3/PGD
RB7
KBI3
PGD
28
18
I/O
O
TTL
TTL
Digital I/O.
PWM Output 0.
I/O
O
TTL
TTL
Digital I/O.
PWM Output 1.
I/O
O
TTL
TTL
Digital I/O.
PWM Output 2.
I/O
O
TTL
TTL
Digital I/O.
PWM Output 3.
I/O
I
O
TTL
TTL
TTL
Digital I/O.
Interrupt-on-change pin.
PWM Output 5.
I/O
I
O
I/O
TTL
TTL
TTL
ST
Digital I/O.
Interrupt-on-change pin.
PWM Output 4.
Single-Supply ICSP Programming entry pin.
I/O
I
I/O
TTL
TTL
ST
Digital I/O.
Interrupt-on-change pin.
In-Circuit Debugger and ICSP programming clock pin.
I/O
I
I/O
TTL
TTL
ST
Digital I/O.
Interrupt-on-change pin.
In-Circuit Debugger and ICSP programming data pin.
19
20
21
22
23
24
25
DS39616D-page 17
PIC18F2331/2431/4331/4431
TABLE 1-2:
Pin Name
Pin Buffer
SPDIP,
Type
Type
QFN
SOIC
Description
PORTC is a bidirectional I/O port.
RC0/T1OSO/T1CKI
RC0
T1OSO
T1CKI
11
RC1/T1OSI/CCP2/FLTA
RC1
T1OSI
CCP2
FLTA
12
RC2/CCP1
RC2
CCP1
13
RC3/T0CKI/T5CKI/INT0
RC3
T0CKI
T5CKI
INT0
14
RC4/INT1/SDI/SDA
RC4
INT1
SDI
SDA
15
RC5/INT2/SCK/SCL
RC5
INT2
SCK
SCL
16
RC6/TX/CK/SS
RC6
TX
CK
SS
17
RC7/RX/DT/SDO
RC7
RX
DT
SDO
18
8
I/O
O
I
ST
ST
Digital I/O.
Timer1 oscillator output.
Timer1 external clock input.
9
I/O
ST
I Analog
I/O
ST
I
ST
Digital I/O.
Timer1 oscillator input.
Capture 2 input, Compare 2 output, PWM2 output.
Fault interrupt input pin.
I/O
I/O
ST
ST
Digital I/O.
Capture 1 input/Compare 1 output/PWM1 output.
I/O
I
I
I
ST
ST
ST
ST
Digital I/O.
Timer0 alternate clock input.
Timer5 alternate clock input.
External Interrupt 0.
I/O
I
I
I/O
ST
ST
ST
I2C
Digital I/O.
External Interrupt 1.
SPI data in.
I2C data I/O.
I/O
I
I/O
I/O
ST
ST
ST
I2C
Digital I/O.
External Interrupt 2.
Synchronous serial clock input/output for SPI mode.
Synchronous serial clock input/output for I2C mode.
I/O
O
I/O
I
ST
ST
TTL
Digital I/O.
EUSART asynchronous transmit.
EUSART synchronous clock (see related RX/DT).
SPI slave select input.
I/O
I
I/O
O
ST
ST
ST
Digital I/O.
EUSART asynchronous receive.
EUSART synchronous data (see related TX/CK).
SPI data out.
10
11
12
13
14
15
VSS
8, 19
5, 16
VDD
7, 20
4, 17
DS39616D-page 18
PIC18F2331/2431/4331/4431
TABLE 1-3:
Pin Name
MCLR/VPP/RE3
MCLR
Pin Number
Pin Buffer
Type
Type
PDIP TQFP QFN
1
18
18
VPP
RE3
OSC1/CLKI/RA7
OSC1
13
30
ST
P
I
ST
32
I
CLKI
RA7
I/O
OSC2/CLKO/RA6
OSC2
14
31
Description
Master Clear (input) or programming voltage (input).
Master Clear (Reset) input. This pin is an active-low
Reset to the device.
Programming voltage input.
Digital input. Available only when MCLR is disabled.
33
O
CLKO
RA6
I/O
TTL
DS39616D-page 19
PIC18F2331/2431/4331/4431
TABLE 1-3:
Pin Name
Pin Number
Pin Buffer
Type
Type
PDIP TQFP QFN
Description
PORTA is a bidirectional I/O port.
RA0/AN0
RA0
AN0
RA1/AN1
RA1
AN1
RA2/AN2/VREF-/CAP1/
INDX
RA2
AN2
VREFCAP1
INDX
RA3/AN3/VREF+/
CAP2/QEA
RA3
AN3
VREF+
CAP2
QEA
RA4/AN4/CAP3/QEB
RA4
AN4
CAP3
QEB
RA5/AN5/LVDIN
RA5
AN5
LVDIN
19
20
21
22
23
24
19
I/O
I
TTL
Analog
Digital I/O.
Analog Input 0.
I/O
I
TTL
Analog
Digital I/O.
Analog Input 1.
I/O
I
I
I
I
TTL
Analog
Analog
ST
ST
Digital I/O.
Analog Input 2.
A/D reference voltage (low) input.
Input Capture Pin 1.
Quadrature Encoder Interface index input pin.
I/O
I
I
I
I
TTL
Analog
Analog
ST
ST
Digital I/O.
Analog Input 3.
A/D reference voltage (high) input.
Input Capture Pin 2.
Quadrature Encoder Interface Channel A input pin.
I/O
I
I
I
TTL
Analog
ST
ST
Digital I/O.
Analog Input 4.
Input Capture Pin 3.
Quadrature Encoder Interface Channel B input pin.
I/O
I
I
TTL
Analog
Analog
Digital I/O.
Analog Input 5.
Low-Voltage Detect input.
20
21
22
23
24
DS39616D-page 20
PIC18F2331/2431/4331/4431
TABLE 1-3:
Pin Name
Pin Number
Pin Buffer
Type
Type
PDIP TQFP QFN
Description
PORTB is a bidirectional I/O port. PORTB can be software
programmed for internal weak pull-ups on all inputs.
RB0/PWM0
RB0
PWM0
33
RB1/PWM1
RB1
PWM1
34
RB2/PWM2
RB2
PWM2
35
RB3/PWM3
RB3
PWM3
36
RB4/KBI0/PWM5
RB4
KBI0
PWM5
37
RB5/KBI1/PWM4/
PGM
RB5
KBI1
PWM4
PGM
38
RB6/KBI2/PGC
RB6
KBI2
PGC
39
RB7/KBI3/PGD
RB7
KBI3
PGD
40
10
11
14
15
16
17
9
I/O
O
TTL
TTL
Digital I/O.
PWM Output 0.
I/O
O
TTL
TTL
Digital I/O.
PWM Output 1.
I/O
O
TTL
TTL
Digital I/O.
PWM Output 2.
I/O
O
TTL
TTL
Digital I/O.
PWM Output 3.
I/O
I
O
TTL
TTL
TTL
Digital I/O.
Interrupt-on-change pin.
PWM Output 5.
I/O
I
O
I/O
TTL
TTL
TTL
ST
Digital I/O.
Interrupt-on-change pin.
PWM Output 4.
Single-Supply ICSP Programming entry pin.
I/O
I
I/O
TTL
TTL
ST
Digital I/O.
Interrupt-on-change pin.
In-Circuit Debugger and ICSP programming clock pin.
I/O
I
I/O
TTL
TTL
ST
Digital I/O.
Interrupt-on-change pin.
In-Circuit Debugger and ICSP programming data pin.
10
11
12
14
15
16
17
DS39616D-page 21
PIC18F2331/2431/4331/4431
TABLE 1-3:
Pin Name
Pin Number
Pin Buffer
Type
Type
PDIP TQFP QFN
Description
PORTC is a bidirectional I/O port.
RC0/T1OSO/T1CKI
RC0
T1OSO
T1CKI
15
RC1/T1OSI/CCP2/
FLTA
RC1
T1OSI
CCP2
FLTA
16
RC2/CCP1/FLTB
RC2
CCP1
FLTB
17
RC3/T0CKI/T5CKI/
INT0
RC3
T0CKI(1)
T5CKI(1)
INT0
18
RC4/INT1/SDI/SDA
RC4
INT1
SDI(1)
SDA(1)
23
RC5/INT2/SCK/SCL
RC5
INT2
SCK(1)
SCL(1)
24
RC6/TX/CK/SS
RC6
TX
CK
SS
25
RC7/RX/DT/SDO
RC7
RX
DT
SDO(1)
26
32
35
36
37
42
43
44
34
I/O
O
I
ST
ST
I/O
I
I/O
I
ST
CMOS
ST
ST
Digital I/O.
Timer1 oscillator input.
Capture 2 input, Compare 2 output, PWM2 output.
Fault interrupt input pin.
I/O
I/O
I
ST
ST
ST
Digital I/O.
Capture 1 input/Compare 1 output/PWM1 output.
Fault interrupt input pin.
I/O
I
I
I
ST
ST
ST
ST
Digital I/O.
Timer0 alternate clock input.
Timer5 alternate clock input.
External Interrupt 0.
I/O
I
I
I/O
ST
ST
ST
I2C
Digital I/O.
External Interrupt 1.
SPI data in.
I2C data I/O.
I/O
I
I/O
I/O
ST
ST
ST
I2C
Digital I/O.
External Interrupt 2.
Synchronous serial clock input/output for SPI mode.
Synchronous serial clock input/output for I2C mode.
I/O
O
I/O
I
ST
ST
ST
Digital I/O.
EUSART asynchronous transmit.
EUSART synchronous clock (see related RX/DT).
SPI slave select input.
I/O
I
I/O
O
ST
ST
ST
Digital I/O.
EUSART asynchronous receive.
EUSART synchronous data (see related TX/CK).
SPI data out.
Digital I/O.
Timer1 oscillator output.
Timer1 external clock input.
35
36
37
42
43
44
DS39616D-page 22
PIC18F2331/2431/4331/4431
TABLE 1-3:
Pin Name
Pin Number
Pin Buffer
Type
Type
PDIP TQFP QFN
Description
PORTD is a bidirectional I/O port.
RD0/T0CKI/T5CKI
RD0
T0CKI
T5CKI
19
RD1/SDO
RD1
SDO(1)
20
RD2/SDI/SDA
RD2
SDI(1)
SDA(1)
21
RD3/SCK/SCL
RD3
SCK(1)
SCL(1)
22
RD4/FLTA
RD4
FLTA(2)
27
RD5/PWM4
RD5
PWM4(3)
28
RD6/PWM6
RD6
PWM6
29
RD7/PWM7
RD7
PWM7
30
38
39
40
41
38
I/O
I
I
ST
ST
ST
Digital I/O.
Timer0 external clock input.
Timer5 input clock.
I/O
O
ST
Digital I/O.
SPI data out.
I/O
I
I/O
ST
ST
ST
Digital I/O.
SPI data in.
I2C data I/O.
I/O
I/O
I/O
ST
ST
ST
Digital I/O.
Synchronous serial clock input/output for SPI mode.
Synchronous serial clock input/output for I2C mode.
I/O
I
ST
ST
Digital I/O.
Fault interrupt input pin.
I/O
O
ST
TTL
Digital I/O.
PWM Output 4.
I/O
O
ST
TTL
Digital I/O.
PWM Output 6.
I/O
O
ST
TTL
Digital I/O.
PWM Output 7.
39
40
41
DS39616D-page 23
PIC18F2331/2431/4331/4431
TABLE 1-3:
Pin Name
Pin Buffer
Type
Type
PDIP TQFP QFN
Description
PORTE is a bidirectional I/O port.
RE0/AN6
RE0
AN6
RE1/AN7
RE1
AN7
RE2/AN8
RE2
AN8
10
VSS
12,
31
VDD
NC
25
25
I/O
I
ST
Analog
Digital I/O.
Analog Input 6.
I/O
I
ST
Analog
Digital I/O.
Analog Input 7.
I/O
I
ST
Analog
Digital I/O.
Analog Input 8.
6, 29 6, 30,
31
11,
32
7, 28
7, 8,
28, 29
12, 13,
33, 34
13
NC
NC
No connect.
26
27
26
27
DS39616D-page 24
PIC18F2331/2431/4331/4431
2.0
FIGURE 2-1:
RECOMMENDED
MINIMUM CONNECTIONS
C2(1)
MCLR
VDD
C1
C3(1)
PIC18FXXXX
VSS
VSS
C6(1)
VDD
C5(1)
VSS
R2
VSS
R1
VDD
VDD
VDD
AVSS
AVDD
2.1
C4(1)
DS39616D-page 25
PIC18F2331/2431/4331/4431
2.2
2.2.1
DS39616D-page 26
2.2.2
TANK CAPACITORS
2.2.3
PIC18F2331/2431/4331/4431
2.3
FIGURE 2-2:
2.4
ICSP Pins
The PGC and PGD pins are used for In-Circuit Serial
Programming (ICSP) and debugging purposes. It
is recommended to keep the trace length between the
ICSP connector and the ICSP pins on the device as
short as possible. If the ICSP connector is expected to
experience an ESD event, a series resistor is recommended, with the value in the range of a few tens of
ohms, not to exceed 100.
Pull-up resistors, series diodes, and capacitors on the
PGC and PGD pins are not recommended as they will
interfere with the programmer/debugger communications to the device. If such discrete components are an
application requirement, they should be removed from
the circuit during programming and debugging. Alternatively, refer to the AC/DC characteristics and timing
requirements information in the respective device
Flash programming specification for information on
capacitive loading limits and pin input voltage high (VIH)
and input low (VIL) requirements.
For device emulation, ensure that the Communication
Channel Select (i.e., PGCx/PGDx pins) programmed
into the device matches the physical connections for
the ICSP to the Microchip debugger/emulator tool.
For more information on available Microchip
development tools connection requirements, refer to
Section 25.0 Development Support.
VDD
R1
R2
MCLR
JP
PIC18FXXXX
C1
Note 1:
R1 10 k is recommended. A suggested
starting value is 10 k. Ensure that the
MCLR pin VIH and VIL specifications are met.
2:
DS39616D-page 27
PIC18F2331/2431/4331/4431
2.5
FIGURE 2-3:
2.6
Unused I/Os
Primary Oscillator
Crystal
DEVICE PINS
Primary
Oscillator
OSC1
C1
OSC2
GND
C2
`
T1OSO
T1OS I
Timer1 Oscillator
Crystal
SUGGESTED PLACEMENT
OF THE OSCILLATOR
CIRCUIT
T1 Oscillator: C1
T1 Oscillator: C2
GND
C1
OSCI
DEVICE PINS
DS39616D-page 28
PIC18F2331/2431/4331/4431
3.0
OSCILLATOR
CONFIGURATIONS
3.1
Oscillator Types
FIGURE 3-1:
C1(1)
LP
XT
HS
HSPLL
5.
RC
6.
RCIO
7.
INTIO1
8.
INTIO2
9. EC
10. ECIO
3.2
Low-Power Crystal
Crystal/Resonator
High-Speed Crystal/Resonator
High-Speed Crystal/Resonator
with PLL Enabled
External Resistor/Capacitor with
FOSC/4 Output on RA6
External Resistor/Capacitor with
I/O on RA6
Internal Oscillator with FOSC/4
Output on RA6 and I/O on RA7
Internal Oscillator with I/O on RA6
and RA7
External Clock with FOSC/4 Output
External Clock with I/O on RA6
Crystal Oscillator/Ceramic
Resonators
CRYSTAL/CERAMIC
RESONATOR OPERATION
(XT, LP, HS OR HSPLL
CONFIGURATION)
OSC1
XTAL
To
Internal
Logic
RF(3)
Sleep
RS(2)
C2(1)
Note 1:
PIC18FXXXX
OSC2
TABLE 3-1:
Freq
OSC1
OSC2
XT
455 kHz
2.0 MHz
4.0 MHz
56 pF
47 pF
33 pF
56 pF
47 pF
33 pF
HS
8.0 MHz
16.0 MHz
27 pF
22 pF
27 pF
22 pF
4.0 MHz
2.0 MHz
8.0 MHz
16.0 MHz
DS39616D-page 29
PIC18F2331/2431/4331/4431
TABLE 3-2:
Osc Type
LP
XT
HS
C2
32 kHz
33 pF
33 pF
200 kHz
15 pF
15 pF
1 MHz
33 pF
33 pF
4 MHz
27 pF
27 pF
4 MHz
27 pF
27 pF
8 MHz
22 pF
22 pF
20 MHz
15 pF
15 pF
4 MHz
200 kHz
8 MHz
1 MHz
20 MHz
FIGURE 3-2:
Clock from
Ext. System
PIC18FXXXX
OSC2
Open
3.3
(HS Mode)
3.3.1
FIGURE 3-3:
HS Osc Enable
PLL Enable
(from Configuration Register 1H)
OSC2
HS Mode
OSC1 Crystal
Osc
FIN
Phase
Comparator
FOUT
Loop
Filter
DS39616D-page 30
VCO
MUX
SYSCLK
PIC18F2331/2431/4331/4431
3.4
FIGURE 3-4:
Clock from
Ext. System
PIC18FXXXX
FOSC/4
OSC2/CLKO
3.5
RC Oscillator
FIGURE 3-6:
RC OSCILLATOR MODE
VDD
REXT
FIGURE 3-5:
CEXT
PIC18FXXXX
VSS
OSC1/CLKI
Clock from
Ext. System
PIC18FXXXX
RA6
I/O (OSC2)
Internal
Clock
OSC1
FOSC/4
OSC2/CLKO
FIGURE 3-7:
VDD
REXT
Internal
Clock
OSC1
CEXT
PIC18FXXXX
VSS
RA6
I/O (OSC2)
DS39616D-page 31
PIC18F2331/2431/4331/4431
3.6
Power-up Timer
Fail-Safe Clock Monitor
Watchdog Timer
Two-Speed Start-up
3.6.1
INTIO MODES
DS39616D-page 32
3.6.2
3.6.3
OSCTUNE REGISTER
3.6.4
The factory calibrates the internal oscillator block output (INTOSC) for 8 MHz. This frequency, however, may
drift as the VDD or temperature changes, which can
affect the controller operation in a variety of ways.
The INTOSC frequency can be adjusted by modifying
the value in the OSCTUNE register. This has no effect
on the INTRC clock source frequency.
Tuning the INTOSC source requires knowing when to
make an adjustment, in which direction it should be
made, and in some cases, how large a change is
needed. Three compensation techniques are discussed
in Section 3.6.4.1 Compensating with the
EUSART, Section 3.6.4.2 Compensating with the
Timers and Section 3.6.4.3 Compensating with the
CCP Module in Capture Mode, but other techniques
may be used.
PIC18F2331/2431/4331/4431
REGISTER 3-1:
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
TUN5
TUN4
TUN3
TUN2
TUN1
TUN0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
-n = Value at POR
1 = Bit is set
0 = Bit is cleared
x = Bit is unknown
bit 7-6
Unimplemented: Read as 0
bit 5-0
000001
000000 = Center frequency. Oscillator module is running at the calibrated frequency.
111111
3.6.4.1
3.6.4.2
3.6.4.3
DS39616D-page 33
PIC18F2331/2431/4331/4431
3.7
3.7.1
The OSCCON register (Register 3-2) controls several aspects of the system clocks operation, both in
full-power operation and in power-managed modes.
The System Clock Select bits, SCS<1:0>, select the
clock source that is used when the device is operating
in power-managed modes. The available clock sources
are the primary clock (defined in Configuration Register
1H), the secondary clock (Timer1 oscillator) and the
internal oscillator block. The clock selection has no
effect until a SLEEP instruction is executed and the
device enters a power-managed mode of operation.
The SCS bits are cleared on all forms of Reset.
The Internal Oscillator Select bits, IRCF<2:0>, select
the frequency output of the internal oscillator block that
is used to drive the system clock. The choices are the
INTRC source, the INTOSC source (8 MHz) or one of
the six frequencies derived from the INTOSC postscaler (125 kHz to 4 MHz). If the internal oscillator
block is supplying the system clock, changing the
states of these bits will have an immediate change on
the internal oscillators output. On device Resets, the
default output frequency of the internal oscillator block
is set at 32 kHz.
The OSTS, IOFS and T1RUN bits indicate which clock
source is currently providing the system clock. The OSTS
indicates that the Oscillator Start-up Timer has timed out,
and the primary clock is providing the system clock in
Primary Clock modes. The IOFS bit indicates when the
internal oscillator block has stabilized, and is providing
the system clock in RC Clock modes. The T1RUN bit
(T1CON<6>) indicates when the Timer1 oscillator is
providing the system clock in Secondary Clock modes. In
power-managed modes, only one of these three bits will
be set at any time. If none of these bits are set, the INTRC
is providing the system clock, or the internal oscillator
block has just started and is not yet stable.
The IDLEN bit controls the selective shutdown of the
controllers CPU in power-managed modes. The use of
these bits is discussed in more detail in Section 4.0
Power-Managed Modes
Note 1: The Timer1 oscillator must be enabled to
select the secondary clock source. The
Timer1 oscillator is enabled by setting the
T1OSCEN bit in the Timer1 Control
register (T1CON<3>). If the Timer1
oscillator is not enabled, then any
attempt to select a secondary clock
source, when executing a SLEEP
instruction, will be ignored.
2: It is recommended that the Timer1
oscillator be operating and stable before
executing the SLEEP instruction, or a
very long delay may occur while the
Timer1 oscillator starts.
DS39616D-page 34
PIC18F2331/2431/4331/4431
PIC18F2331/2431/4331/4431 CLOCK DIAGRAM
CONFIG1H <3:0>
Primary Oscillator
OSC2
OSC1
Secondary Oscillator
T1OSC
T1OSO
T1OSI
OSCCON<1:0>
HSPLL
4 x PLL
Sleep
Clock
Control
T1OSCEN
Enable
Oscillator
OSCCON<6:4>
8 MHz
OSCCON<6:4>
MUX
FIGURE 3-8:
Peripherals
Internal Oscillator
CPU
111
4 MHz
8 MHz
(INTOSC)
Postscaler
INTRC
Source
2 MHz
1 MHz
500 kHz
250 kHz
125 kHz
31 kHz
110
IDLEN
101
100
011
MUX
Internal
Oscillator
Block
010
001
000
WDT, FSCM
DS39616D-page 35
PIC18F2331/2431/4331/4431
REGISTER 3-2:
R/W-0
R/W-0
R/W-0
R/W-0
R(1)
R-0
R/W-0
R/W-0
IDLEN
IRCF2
IRCF1
IRCF0
OSTS
IOFS
SCS1
SCS0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
-n = Value at POR
1 = Bit is set
0 = Bit is cleared
x = Bit is unknown
bit 7
bit 6-4
bit 3
bit 2
bit 1-0
Note 1:
2:
DS39616D-page 36
PIC18F2331/2431/4331/4431
3.7.2
OSCILLATOR TRANSITIONS
3.8
TABLE 3-3:
3.9
Power-up Delays
OSC Mode
OSC1 Pin
OSC2 Pin
RC, INTIO1
RCIO, INTIO2
ECIO
EC
LP, XT and HS
Note:
See Table 5-1 in Section 5.0 Reset for time-outs due to Sleep and MCLR Reset.
DS39616D-page 37
PIC18F2331/2431/4331/4431
NOTES:
DS39616D-page 38
PIC18F2331/2431/4331/4431
4.0
4.1.1
POWER-MANAGED MODES
4.1.2
Run modes
Idle modes
Sleep mode
The power-managed modes include several powersaving features offered on previous PIC devices. One
is the clock switching feature, offered in other PIC18
devices, allowing the controller to use the Timer1 oscillator in place of the primary oscillator. Also included is
the Sleep mode, offered by all PIC devices, where all
device clocks are stopped.
TABLE 4-1:
ENTERING POWER-MANAGED
MODES
4.1
CLOCK SOURCES
POWER-MANAGED MODES
OSCCON Bits<7,1:0>
Module Clocking
IDLEN(1)
SCS<1:0>
CPU
Peripherals
N/A
Off
Off
PRI_RUN
N/A
00
Clocked
Clocked
SEC_RUN
N/A
01
Clocked
Clocked
RC_RUN
N/A
1x
Clocked
Clocked
PRI_IDLE
00
Off
Clocked
SEC_IDLE
01
Off
Clocked
RC_IDLE
1x
Off
Clocked
Mode
Sleep
Note 1:
2:
DS39616D-page 39
PIC18F2331/2431/4331/4431
4.1.3
4.1.4
DS39616D-page 40
4.2
Run Modes
4.2.1
PRI_RUN MODE
The PRI_RUN mode is the normal, full-power execution mode of the microcontroller. This is also the default
mode upon a device Reset unless Two-Speed Start-up
is enabled (see Section 23.3 Two-Speed Start-up
for details). In this mode, the OSTS bit is set. The IOFS
bit may be set if the internal oscillator block is the
primary clock source (see Section 3.7.1 Oscillator
Control Register).
4.2.2
SEC_RUN MODE
PIC18F2331/2431/4331/4431
FIGURE 4-1:
Q2
1
T1OSI
n-1
Q3
Q4
Q1
Q2
Q3
Clock Transition(1)
OSC1
CPU
Clock
Peripheral
Clock
Program
Counter
Note 1:
PC
PC + 2
PC + 4
FIGURE 4-2:
Q2
Q3
Q4
Q1
Q2 Q3 Q4 Q1 Q2 Q3
T1OSI
OSC1
TOST(1)
TPLL(1)
1
PLL Clock
Output
n-1 n
Clock
Transition(2)
CPU Clock
Peripheral
Clock
Program
Counter
SCS<1:0> bits Changed
Note 1:
2:
4.2.3
PC + 2
PC
PC + 4
TOST = 1024 TOSC; TPLL = 2 ms (approx). These intervals are not shown to scale.
Clock transition typically occurs within 2-4 TOSC.
RC_RUN MODE
DS39616D-page 41
PIC18F2331/2431/4331/4431
If the IRCF bits and the INTSRC bit are all clear, the
INTOSC output is not enabled and the IOFS bit will
remain clear; there will be no indication of the current
clock source. The INTRC source is providing the
device clocks.
FIGURE 4-3:
Q2
1
INTRC
n-1
Clock Transition
OSC1
Q3
Q4
Q1
Q2
Q3
(1)
CPU
Clock
Peripheral
Clock
Program
Counter
Note 1:
PC
PC + 2
PC + 4
FIGURE 4-4:
Q2
Q3
Q4
Q2 Q3 Q4 Q1 Q2 Q3
Q1
INTOSC
Multiplexer
OSC1
TOST(1)
TPLL(1)
1
PLL Clock
Output
n-1 n
Clock
Transition(2)
CPU Clock
Peripheral
Clock
Program
Counter
SCS<1:0> bits Changed
Note 1:
2:
DS39616D-page 42
PC + 2
PC
PC + 4
TOST = 1024 TOSC; TPLL = 2 ms (approx). These intervals are not shown to scale.
Clock transition typically occurs within 2-4 TOSC.
PIC18F2331/2431/4331/4431
4.3
Sleep Mode
4.4
Idle Modes
FIGURE 4-5:
Q1 Q2 Q3 Q4 Q1
OSC1
CPU
Clock
Peripheral
Clock
Sleep
Program
Counter
PC
FIGURE 4-6:
PC + 2
Q1
OSC1
TOST(1)
PLL Clock
Output
TPLL(1)
CPU Clock
Peripheral
Clock
Program
Counter
PC
Wake Event
PC + 2
PC + 4
PC + 6
Note1: TOST = 1024 TOSC; TPLL = 2 ms (approx). These intervals are not shown to scale.
DS39616D-page 43
PIC18F2331/2431/4331/4431
4.4.1
PRI_IDLE MODE
4.4.2
SEC_IDLE MODE
FIGURE 4-7:
Q3
Q2
Q4
Q1
OSC1
CPU Clock
Peripheral
Clock
Program
Counter
FIGURE 4-8:
PC
PC + 2
Q2
Q3
Q4
OSC1
TCSD
CPU Clock
Peripheral
Clock
Program
Counter
PC
Wake Event
DS39616D-page 44
PIC18F2331/2431/4331/4431
4.4.3
RC_IDLE MODE
In RC_IDLE mode, the CPU is disabled but the peripherals continue to be clocked from the internal oscillator
block using the INTOSC multiplexer. This mode allows
for controllable power conservation during Idle periods.
From RC_RUN, this mode is entered by setting the
IDLEN bit and executing a SLEEP instruction. If the
device is in another Run mode, first set IDLEN, then set
the SCS1 bit and execute SLEEP. Although its value is
ignored, it is recommended that SCS0 also be cleared;
this is to maintain software compatibility with future
devices. The INTOSC multiplexer may be used to
select a higher clock frequency by modifying the IRCF
bits before executing the SLEEP instruction. When the
clock source is switched to the INTOSC multiplexer, the
primary oscillator is shut down and the OSTS bit is
cleared.
If the IRCF bits are set to any non-zero value, or the
INTSRC bit is set, the INTOSC output is enabled. The
IOFS bit becomes set, after the INTOSC output
becomes stable, after an interval of TIOBST
(Parameter 39, Table 26-8). Clocks to the peripherals
continue while the INTOSC source stabilizes. If the
IRCF bits were previously at a non-zero value, or
INTSRC was set before the SLEEP instruction was
executed, and the INTOSC source was already stable,
the IOFS bit will remain set. If the IRCF bits and
INTSRC are all clear, the INTOSC output will not be
enabled, the IOFS bit will remain clear and there will be
no indication of the current clock source.
When a wake event occurs, the peripherals continue to
be clocked from the INTOSC multiplexer. After a delay of
TCSD, following the wake event, the CPU begins executing code being clocked by the INTOSC multiplexer. The
IDLEN and SCS bits are not affected by the wake-up.
The INTRC source will continue to run if either the WDT
or the Fail-Safe Clock Monitor is enabled.
4.5
4.5.1
EXIT BY INTERRUPT
4.5.2
4.5.3
EXIT BY RESET
DS39616D-page 45
PIC18F2331/2431/4331/4431
4.5.4
TABLE 4-2:
EXIT DELAY ON WAKE-UP BY RESET FROM SLEEP MODE OR ANY IDLE MODE
(BY CLOCK SOURCES)
Clock Source
Before Wake-up
Clock Source
After Wake-up
Exit Delay
LP, XT, HS
Primary Device Clock
(PRI_IDLE mode)
HSPLL
EC, RC
TCSD(1)
INTOSC(2)
T1OSC
INTOSC(3)
None
(Sleep mode)
2:
3:
4:
IOFS
LP, XT, HS
TOST(3)
HSPLL
TOST + trc(3)
OSTS
EC, RC
INTOSC(2)
TCSD(1)
TIOBST(4)
IOFS
LP, XT, HS
TOST(3)
HSPLL
TOST + trc(3)
OSTS
EC, RC
TCSD(1)
INTOSC(2)
None
LP, XT, HS
TOST(3)
HSPLL
TOST + trc(3)
OSTS
EC, RC
TCSD(1)
TIOBST(4)
IOFS
INTOSC(2)
Note 1:
OSTS
IOFS
TCSD (Parameter 38) is a required delay when waking from Sleep and all Idle modes, and runs concurrently with any other required delays (see Section 4.4 Idle Modes).
Includes both the INTOSC 8 MHz source and postscaler derived frequencies.
TOST is the Oscillator Start-up Timer (Parameter 32). trc is the PLL Lock-out Timer (Parameter F12); it is
also designated as TPLL.
Execution continues during TIOBST (Parameter 39), the INTOSC stabilization period.
DS39616D-page 46
PIC18F2331/2431/4331/4431
5.0
RESET
FIGURE 5-1:
RESET
Instruction
Stack Full/Underflow Reset
Stack
Pointer
External Reset
MCLR
MCLRE
( )_IDLE
Sleep
WDT
Time-out
VDD Rise
Detect
VDD
POR Pulse
Brown-out
Reset
BOREN
OST/PWRT
OST
1024 Cycles
PWRT
Chip_Reset
65.5 ms
Enable PWRT
Enable OST(1)
Note 1:
DS39616D-page 47
PIC18F2331/2431/4331/4431
5.1
RCON Register
REGISTER 5-1:
R/W-0
U-0
U-0
R/W-1
R-1
R-1
R/W-0
R/W-0
IPEN
RI
TO
PD
POR(2)
BOR(1)
bit 0
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 7
W = Writable bit
1 = Bit is set
bit 6-5
bit 4
bit 3
bit 2
bit 1
bit 0
Note 1:
2:
Note 1: It is recommended that the POR bit be set after a Power-on Reset has been detected so that subsequent
Power-on Resets may be detected.
2: Brown-out Reset is said to have occurred when BOR is 0 and POR is 1 (assuming that POR was set to
1 by software immediately after a Power-on Reset).
DS39616D-page 48
PIC18F2331/2431/4331/4431
5.2
FIGURE 5-2:
5.3
A Power-on Reset pulse is generated on-chip whenever VDD rises above a certain threshold. This allows
the device to start in the initialized state when VDD is
adequate for operation.
R
R1
C
MCLR
PIC18FXXXX
VDD
VDD
EXTERNAL POWER-ON
RESET CIRCUIT (FOR
SLOW VDD POWER-UP)
5.4
DS39616D-page 49
PIC18F2331/2431/4331/4431
5.5
5.5.3
5.5.1
5.5.4
5.5.2
TIME-OUT SEQUENCE
The total time-out will vary based on oscillator configuration and the status of the PWRT. Figure 5-3 through
Figure 5-7 depict time-out sequences on power-up,
with the Power-up Timer enabled and the device operating in HS Oscillator mode. Figure 5-3 through
Figure 5-6 also apply to devices operating in XT or LP
modes.
For devices in RC mode, and with the PWRT disabled,
there will be no time-out at all. Since the time-outs
occur from the POR pulse, if MCLR is kept low long
enough, all time-outs will expire. Bringing MCLR high
will begin execution immediately (Figure 5-5). This is
useful for testing purposes or synchronization of more
than one PIC18FXXXX device operating in parallel.
TABLE 5-1:
Oscillator
Configuration
HSPLL
HS, XT, LP
PWRTEN = 1
Exit From
Power-Managed Mode
(1)
1024 TOSC
1024 TOSC
EC, ECIO
66
ms(1)
RC, RCIO
66 ms(1)
(1)
INTIO1, INTIO2
Note 1:
2:
66 ms
+ 1024 TOSC
66 ms
DS39616D-page 50
PIC18F2331/2431/4331/4431
5.6
FIGURE 5-3:
Status bits from the RCON register (RI, TO, PD, POR
and BOR) are set or cleared differently in different
Reset situations, as indicated in Table 5-2. These bits
are used in software to determine the nature of the
Reset.
Table 5-3 describes the Reset states for all of the
Special Function Registers. These are categorized by
Power-on and Brown-out Resets, Master Clear and
WDT Resets, and WDT wake-ups.
TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD, VDD RISE < TPWRT)
VDD
MCLR
INTERNAL POR
TPWRT
PWRT TIME-OUT
TOST
OST TIME-OUT
INTERNAL RESET
FIGURE 5-4:
VDD
MCLR
INTERNAL POR
PWRT TIME-OUT
TPWRT
TOST
OST TIME-OUT
INTERNAL RESET
DS39616D-page 51
PIC18F2331/2431/4331/4431
FIGURE 5-5:
VDD
MCLR
INTERNAL POR
TPWRT
PWRT TIME-OUT
TOST
OST TIME-OUT
INTERNAL RESET
FIGURE 5-6:
SLOW RISE TIME (MCLR TIED TO VDD, VDD RISE > TPWRT)
5V
VDD
1V
0V
MCLR
INTERNAL POR
TPWRT
PWRT TIME-OUT
TOST
OST TIME-OUT
INTERNAL RESET
DS39616D-page 52
PIC18F2331/2431/4331/4431
FIGURE 5-7:
VDD
MCLR
INTERNAL POR
TPWRT
PWRT TIME-OUT
TOST
TPLL
OST TIME-OUT
PLL TIME-OUT
INTERNAL RESET
Note:
TABLE 5-2:
Program
Counter
RCON
Register
RI
TO
PD
POR
BOR
STKFUL STKUNF
Power-on Reset
0000h
0--1 1100
RESET Instruction
0000h
0--0 uuuu
Brown-out
0000h
0--1 11u-
0000h
0--u 1uuu
0000h
0--u 10uu
0000h
0--u 0uuu
0000h
0--u uuuu
0000h
u--u uuuu
PC + 2
u--u 00uu
PC + 2(1)
u--u u0uu
Legend:
Note 1:
DS39616D-page 53
PIC18F2331/2431/4331/4431
TABLE 5-3:
Power-on Reset,
Brown-out Reset
MCLR Resets
WDT Reset
RESET Instruction
Stack Resets
TOSU
---0 0000
---0 0000
---0 uuuu(3)
TOSH
0000 0000
0000 0000
uuuu uuuu(3)
TOSL
0000 0000
0000 0000
uuuu uuuu(3)
STKPTR
00-0 0000
uu-0 0000
uu-u uuuu(3)
PCLATU
---0 0000
---0 0000
---u uuuu
PCLATH
0000 0000
0000 0000
uuuu uuuu
PCL
0000 0000
0000 0000
PC + 2(2)
TBLPTRU
--00 0000
--00 0000
--uu uuuu
TBLPTRH
0000 0000
0000 0000
uuuu uuuu
TBLPTRL
0000 0000
0000 0000
uuuu uuuu
TABLAT
0000 0000
0000 0000
uuuu uuuu
PRODH
xxxx xxxx
uuuu uuuu
uuuu uuuu
PRODL
xxxx xxxx
uuuu uuuu
uuuu uuuu
INTCON
0000 000x
0000 000u
uuuu uuuu(1)
INTCON2
1111 -1-1
1111 -1-1
uuuu -u-u(1)
INTCON3
11-0 0-00
11-0 0-00
uu-u u-uu(1)
INDF0
N/A
N/A
N/A
POSTINC0
N/A
N/A
N/A
Register
POSTDEC0
N/A
N/A
N/A
PREINC0
N/A
N/A
N/A
PLUSW0
N/A
N/A
N/A
FSR0H
---- xxxx
---- uuuu
---- uuuu
FSR0L
xxxx xxxx
uuuu uuuu
uuuu uuuu
WREG
xxxx xxxx
uuuu uuuu
uuuu uuuu
INDF1
N/A
N/A
N/A
POSTINC1
N/A
N/A
N/A
POSTDEC1
N/A
N/A
N/A
PREINC1
N/A
N/A
N/A
PLUSW1
N/A
N/A
N/A
DS39616D-page 54
PIC18F2331/2431/4331/4431
TABLE 5-3:
Power-on Reset,
Brown-out Reset
MCLR Resets
WDT Reset
RESET Instruction
Stack Resets
FSR1H
---- 0000
---- uuuu
---- uuuu
FSR1L
xxxx xxxx
uuuu uuuu
uuuu uuuu
BSR
---- 0000
---- 0000
---- uuuu
INDF2
N/A
N/A
N/A
Register
POSTINC2
N/A
N/A
N/A
POSTDEC2
N/A
N/A
N/A
PREINC2
N/A
N/A
N/A
PLUSW2
N/A
N/A
N/A
FSR2H
---- 0000
---- uuuu
---- uuuu
FSR2L
xxxx xxxx
uuuu uuuu
uuuu uuuu
STATUS
---x xxxx
---u uuuu
---u uuuu
TMR0H
0000 0000
0000 0000
uuuu uuuu
TMR0L
xxxx xxxx
uuuu uuuu
uuuu uuuu
T0CON
1111 1111
1111 1111
uuuu uuuu
OSCCON
0000 q000
0000 q000
uuuu uuuu
LVDCON
--00 0101
--00 0101
--uu uuuu
WDTCON
0--- ---0
0--- ---0
u--- ---u
RCON(4)
0--1 11q0
0--q qquu
u--u qquu
TMR1H
xxxx xxxx
uuuu uuuu
uuuu uuuu
TMR1L
xxxx xxxx
uuuu uuuu
uuuu uuuu
T1CON
0000 0000
u0uu uuuu
uuuu uuuu
TMR2
0000 0000
0000 0000
uuuu uuuu
PR2
1111 1111
1111 1111
1111 1111
T2CON
-000 0000
-000 0000
-uuu uuuu
SSPBUF
xxxx xxxx
uuuu uuuu
uuuu uuuu
SSPADD
0000 0000
0000 0000
uuuu uuuu
SSPSTAT
0000 0000
0000 0000
uuuu uuuu
SSPCON
0000 0000
0000 0000
uuuu uuuu
DS39616D-page 55
PIC18F2331/2431/4331/4431
TABLE 5-3:
Power-on Reset,
Brown-out Reset
MCLR Resets
WDT Reset
RESET Instruction
Stack Resets
ADRESH
xxxx xxxx
uuuu uuuu
uuuu uuuu
ADRESL
xxxx xxxx
uuuu uuuu
uuuu uuuu
ADCON0
--00 0000
--00 0000
--uu uuuu
ADCON1
00-0 0000
00-0 0000
uu-u uuuu
ADCON2
0000 0000
0000 0000
uuuu uuuu
ADCON3
00-0 0000
00-0 0000
uu-u uuuu
ADCHS
0000 0000
0000 0000
uuuu uuuu
CCPR1H
xxxx xxxx
uuuu uuuu
uuuu uuuu
CCPR1L
xxxx xxxx
uuuu uuuu
uuuu uuuu
CCP1CON
--00 0000
--00 0000
--uu uuuu
CCPR2H
xxxx xxxx
uuuu uuuu
uuuu uuuu
CCPR2L
xxxx xxxx
uuuu uuuu
uuuu uuuu
CCP2CON
--00 0000
--00 0000
--uu uuuu
ANSEL1
---- ---1
---- ---1
---- ---u
ANSEL0
1111 1111
1111 1111
uuuu uuuu
T5CON
0000 0000
0000 0000
uuuu uuuu
QEICON
0000 0000
0000 0000
uuuu uuuu
SPBRGH
0000 0000
0000 0000
uuuu uuuu
SPBRG
0000 0000
0000 0000
uuuu uuuu
RCREG
0000 0000
0000 0000
uuuu uuuu
TXREG
0000 0000
0000 0000
uuuu uuuu
TXSTA
0000 -010
0000 -010
uuuu -uuu
RCSTA
0000 000x
0000 000x
uuuu uuuu
BAUDCON
-1-1 0-00
-1-1 0-00
-u-u u-uu
EEADR
0000 0000
0000 0000
uuuu uuuu
EEDATA
0000 0000
0000 0000
uuuu uuuu
EECON2
0000 0000
0000 0000
0000 0000
EECON1
xx-0 x000
uu-0 u000
uu-0 u000
IPR3
---1 1111
---1 1111
---u uuuu
PIE3
---0 0000
---0 0000
---u uuuu
PIR3
---0 0000
---0 0000
---u uuuu
Register
DS39616D-page 56
PIC18F2331/2431/4331/4431
TABLE 5-3:
Register
Power-on Reset,
Brown-out Reset
MCLR Resets
WDT Reset
RESET Instruction
Stack Resets
IPR2
1--1 -1-1
1--1 -1-1
u--u -u-u
PIR2
0--0 -0-0
0--0 -0-0
u--u -u-u
PIE2
0--0 -0-0
0--0 -0-0
u--u -u-u
IPR1
-111 1111
-111 1111
-uuu uuuu
PIR1
-000 0000
-000 0000
-uuu uuuu(1)
-000 0000
-000 0000
-uuu uuuu(1)
0000 0000
0000 0000
uuuu uuuu
-000 0000
-000 0000
-uuu uuuu
PIE1
OSCTUNE
--00 0000
--00 0000
--uu uuuu
TRISE(6)
---- -111
---- -111
---- -uuu
TRISD
1111 1111
1111 1111
uuuu uuuu
TRISC
1111 1111
1111 1111
uuuu uuuu
TRISB
1111 1111
1111 1111
uuuu uuuu
TRISA(5)
1111 1111(5)
1111 1111(5)
uuuu uuuu(5)
PR5H
1111 1111
1111 1111
uuuu uuuu
PR5L
1111 1111
1111 1111
uuuu uuuu
LATE(6)
---- -xxx
---- -uuu
---- -uuu
LATD
xxxx xxxx
uuuu uuuu
uuuu uuuu
LATC
xxxx xxxx
uuuu uuuu
uuuu uuuu
LATB
xxxx xxxx
uuuu uuuu
uuuu uuuu
(5)
LATA
xxxx xxxx(5)
uuuu uuuu(5)
uuuu uuuu(5)
TMR5H
xxxx xxxx
uuuu uuuu
uuuu uuuu
TMR5L
xxxx xxxx
uuuu uuuu
uuuu uuuu
PORTE(6)
---- xxxx
---- xxxx
---- uuuu
PORTD
xxxx xxxx
uuuu uuuu
uuuu uuuu
PORTC
xxxx xxxx
uuuu uuuu
uuuu uuuu
PORTB
xxxx xxxx
uuuu uuuu
uuuu uuuu
PORTA(5)
xx0x 0000(5)
uu0u 0000(5)
uuuu uuuu(5)
DS39616D-page 57
PIC18F2331/2431/4331/4431
TABLE 5-3:
Power-on Reset,
Brown-out Reset
MCLR Resets
WDT Reset
RESET Instruction
Stack Resets
PTCON0
0000 0000
uuuu uuuu
uuuu uuuu
PTCON1
00-- ----
00-- ----
uu-- ----
PTMRL
0000 0000
0000 0000
uuuu uuuu
PTMRH
---- 0000
---- 0000
---- uuuu
PTPERL
1111 1111
1111 1111
uuuu uuuu
PTPERH
---- 1111
---- 1111
---- uuuu
PDC0L
0000 0000
0000 0000
uuuu uuuu
PDC0H
--00 0000
--00 0000
--uu uuuu
PDC1L
0000 0000
0000 0000
uuuu uuuu
PDC1H
--00 0000
--00 0000
--uu uuuu
PDC2L
0000 0000
0000 0000
uuuu uuuu
PDC2H
--00 0000
--00 0000
--uu uuuu
PDC3L
0000 0000
0000 0000
uuuu uuuu
PDC3H
--00 0000
--00 0000
--uu uuuu
SEVTCMPL
0000 0000
0000 0000
uuuu uuuu
SEVTCMPH
---- 0000
---- 0000
---- uuuu
PWMCON0
-111 0000
-111 0000
-uuu uuuu
PWMCON1
0000 0-00
0000 0-00
uuuu u-uu
DTCON
0000 0000
0000 0000
uuuu uuuu
FLTCONFIG
0000 0000
0000 0000
uuuu uuuu
OVDCOND
1111 1111
1111 1111
uuuu uuuu
OVDCONS
0000 0000
0000 0000
uuuu uuuu
CAP1BUFH/
VELRH
xxxx xxxx
uuuu uuuu
uuuu uuuu
CAP1BUFL/
VELRL
xxxx xxxx
uuuu uuuu
uuuu uuuu
CAP2BUFH/
POSCNTH
xxxx xxxx
uuuu uuuu
uuuu uuuu
CAP2BUFL/
POSCNTL
xxxx xxxx
uuuu uuuu
uuuu uuuu
CAP3BUFH/
MAXCNTH
xxxx xxxx
uuuu uuuu
uuuu uuuu
Register
DS39616D-page 58
PIC18F2331/2431/4331/4431
TABLE 5-3:
Register
Applicable Devices
Power-on Reset,
Brown-out Reset
CAP3BUFL/
MAXCNTL
xxxx xxxx
uuuu uuuu
uuuu uuuu
CAP1CON
-0-- 0000
-0-- 0000
-u-- uuuu
CAP2CON
-0-- 0000
-0-- 0000
-u-- uuuu
CAP3CON
-0-- 0000
-0-- 0000
-u-- uuuu
DFLTCON
-000 0000
-000 0000
-uuu uuuu
DS39616D-page 59
PIC18F2331/2431/4331/4431
NOTES:
DS39616D-page 60
PIC18F2331/2431/4331/4431
6.0
MEMORY ORGANIZATION
FIGURE 6-1:
6.1
FIGURE 6-2:
PC<20:0>
21
CALL,RCALL,RETURN
RETFIE,RETLW
21
CALL,RCALL,RETURN
RETFIE,RETLW
Stack Level 1
Stack Level 1
Stack Level 31
Stack Level 31
Reset Vector LSb
000018h
On-Chip Flash
Program Memory
001FFFh
002000h
User Memory
Space
On-Chip Flash
Program Memory
000000h
User Memory
Space
003FFFh
004000h
Unused
Read 0s
1FFFFFh
Unused
Read 0s
1FFFFFh
DS39616D-page 61
PIC18F2331/2431/4331/4431
6.1.1
PROGRAM COUNTER
6.1.2
DS39616D-page 62
6.1.2.1
Top-of-Stack Access
6.1.2.2
PIC18F2331/2431/4331/4431
When the stack has been popped enough times to
unload the stack, the next pop will return a value of zero
to the PC and set the STKUNF bit, while the Stack
Pointer remains at zero. The STKUNF bit will remain
set until cleared by software or a POR occurs.
FIGURE 6-3:
Note:
TOSH
1Ah
TOSL
34h
Top-of-Stack
REGISTER 6-1:
STKPTR<4:0>
00010
00011
001A34h 00010
000D58h 00001
00000
R/C-0
R/C-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
STKFUL(1)
STKUNF(1)
SP4
SP3
SP2
SP1
SP0
bit 7
bit 0
Legend:
C = Clearable bit
R = Readable bit
W = Writable bit
-n = Value at POR
1 = Bit is set
0 = Bit is cleared
bit 7
bit 6
bit 5
Unimplemented: Read as 0
bit 4-0
Note 1:
x = Bit is unknown
DS39616D-page 63
PIC18F2331/2431/4331/4431
6.1.2.3
6.1.2.4
6.1.3
DS39616D-page 64
EXAMPLE 6-1:
CALL SUB1, FAST
SUB1
RETURN FAST
6.1.4
6.1.4.1
Computed GOTO
EXAMPLE 6-2:
MOVFW
CALL
0xnn00
ADDWF
RETLW
RETLW
RETLW
ORG
TABLE
.
.
.
PIC18F2331/2431/4331/4431
6.1.4.2
6.2
FIGURE 6-4:
Clocking Scheme/Instruction
Cycle
CLOCK/INSTRUCTION CYCLE
Q1
Q2
Q3
Q4
Q2
Q1
Q3
Q4
Q2
Q1
Q3
Q4
OSC1
Q1
Q2
Internal
Phase
Clock
Q3
Q4
PC
OSC2/CLKO
(RC mode)
6.3
1. MOVLW 55h
TCY0
TCY1
Fetch 1
Execute 1
2. MOVWF PORTB
3. BRA SUB_1
4. BSF
Instruction Flow/Pipelining
EXAMPLE 6-3:
PC + 4
PC + 2
PC
Fetch 2
TCY2
TCY3
TCY4
TCY5
Execute 2
Fetch 3
Execute 3
Fetch 4
Flush (NOP)
Fetch SUB_1 Execute SUB_1
All instructions are single cycle, except for any program branches. These take two cycles since the fetch instruction
is flushed from the pipeline, while the new instruction is being fetched and then executed.
DS39616D-page 65
PIC18F2331/2431/4331/4431
6.4
FIGURE 6-5:
6.4.1
TWO-WORD INSTRUCTIONS
LSB = 0
0Fh
EFh
F0h
C1h
F4h
55h
03h
00h
23h
56h
Program Memory
Byte Locations
Instruction 1:
Instruction 2:
MOVLW
GOTO
055h
000006h
Instruction 3:
MOVFF
123h, 456h
EXAMPLE 6-4:
TWO-WORD INSTRUCTIONS
CASE 1:
Object Code
Source Code
0000
0011
0110
0000
0110
1100
1111
0010
0000
0011
0110
0000
0110
0001
0100
0100
Word Address
000000h
000002h
000004h
000006h
000008h
00000Ah
00000Ch
00000Eh
000010h
000012h
000014h
0000
0010
0101
0000
DS39616D-page 66
TSTFSZ
MOVFF
ADDWF
REG1
; is RAM location 0?
REG1, REG2 ; No, skip this word
; Execute this word as a NOP
REG3
; continue code
Source Code
TSTFSZ
MOVFF
ADDWF
REG1
; is RAM location 0?
REG1, REG2 ; Yes, execute this word
; 2nd word of instruction
REG3
; continue code
PIC18F2331/2431/4331/4431
6.5
FIGURE 6-6:
BSR<3:0>
= 0000
= 0001
= 0010
00h
Access RAM
FFh
00h
GPR
Bank 0
000h
05Fh
060h
0FFh
100h
GPR
Bank 1
1FFh
200h
FFh
00h
GPR
Bank 2
FFh
00h
2FFh
300h
Access Bank
Access RAM Low
= 0011
= 1110
Bank 3
to
Bank 14
00h
5Fh
Access RAM High 60h
(SFRs)
FFh
Unused
Read 00h
When a = 0:
The BSR is ignored and the
Access Bank is used.
The first 96 bytes are
General Purpose RAM
(from Bank 0).
= 1111
00h
Unused
FFh
SFR
Bank 15
EFFh
F00h
F5Fh
F60h
FFFh
DS39616D-page 67
PIC18F2331/2431/4331/4431
6.5.1
DS39616D-page 68
6.5.2
ACCESS BANK
6.5.3
PIC18F2331/2431/4331/4431
6.5.4
TABLE 6-1:
Address
Name
Address
FFFh
TOSU
FDFh
INDF2(1)
Name
Address
FFEh
TOSH
FDEh
POSTINC2(1)
FFDh
TOSL
FDDh POSTDEC2(1)
(1)
Name
FBFh
CCPR1H
FBEh
CCPR1L
FBDh CCP1CON
Address
Name
Address
Name
F9Fh
IPR1
F7Fh
PTCON0
F9Eh
PIR1
F7Eh
PTCON1
F9Dh
PIE1
F7Dh
PTMRL
(2)
FFCh
STKPTR
FDCh
PREINC2
FBCh
CCPR2H
F9Ch
F7Ch
PTMRH
FFBh
PCLATU
FDBh
PLUSW2(1)
FBBh
CCPR2L
F9Bh OSCTUNE
F7Bh
PTPERL
FFAh
PCLATH
FDAh
FSR2H
FBAh CCP2CON
F9Ah
ADCON3
F7Ah
PTPERH
FF9h
PCL
FD9h
FSR2L
FB9h
F99h
ADCHS
F79h
PDC0L
F78h
PDC0H
F77h
PDC1L
(3)
ANSEL1
FF8h
TBLPTRU
FD8h
STATUS
FB8h
ANSEL0
F98h
(2)
FF7h
TBLPTRH
FD7h
TMR0H
FB7h
T5CON
F97h
(2)
FF6h
TBLPTRL
FD6h
TMR0L
FB6h
QEICON
F96h
TRISE
F76h
PDC1H
FF5h
TABLAT
FD5h
T0CON
FB5h
(2)
F95h
TRISD(3)
F75h
PDC2L
FF4h
PRODH
FD4h
(2)
FB4h
(2)
F94h
TRISC
F74h
PDC2H
FF3h
PRODL
FD3h
OSCCON
FB3h
(2)
F93h
TRISB
F73h
PDC3L(3)
FF2h
INTCON
FD2h
LVDCON
FB2h
(2)
F92h
TRISA
F72h
PDC3H(3)
WDTCON
FB1h
(2)
F91h
PR5H
F71h
SEVTCMPL
FF1h
INTCON2
FD1h
FF0h
INTCON3
FD0h
RCON
FB0h
SPBRGH
F90h
PR5L
F70h
SEVTCMPH
FEFh
INDF0(1)
FCFh
TMR1H
FAFh
SPBRG
F8Fh
(2)
F6Fh
PWMCON0
FEEh
POSTINC0(1)
FCEh
TMR1L
FAEh
RCREG
F8Eh
(2)
F6Eh
PWMCON1
FEDh POSTDEC0(1)
FCDh
T1CON
FADh
TXREG
F8Dh
LATE(3)
F6Dh
DTCON
FECh
PREINC0(1)
FCCh
TMR2
FACh
TXSTA
F8Ch
LATD(3)
F6Ch
FLTCONFIG
FEBh
PLUSW0(1)
FCBh
PR2
FABh
RCSTA
F8Bh
LATC
F6Bh
OVDCOND
FEAh
FSR0H
FCAh
T2CON
FAAh BAUDCON
F8Ah
LATB
F6Ah
OVDCONS
FE9h
FSR0L
FC9h
SSPBUF
FA9h
F89h
LATA
F69h
CAP1BUFH
EEADR
FE8h
WREG
FC8h
SSPADD
FA8h
EEDATA
F88h
TMR5H
F68h
CAP1BUFL
FE7h
INDF1(1)
FC7h
SSPSTAT
FA7h
EECON2
F87h
TMR5L
F67h
CAP2BUFH
FE6h POSTINC1(1)
FC6h
SSPCON
FA6h
EECON1
F86h
(2)
F66h
CAP2BUFL
FE5h
POSTDEC1(1)
FC5h
(2)
FA5h
IPR3
F85h
(2)
F65h
CAP3BUFH
FE4h
PREINC1(1)
FC4h
ADRESH
FA4h
PIR3
F84h
PORTE
F64h
CAP3BUFL
FE3h
PLUSW1(1)
FC3h
ADRESL
FA3h
PIE3
F83h
PORTD(3)
F63h
CAP1CON
FE2h
FSR1H
FC2h
ADCON0
FA2h
IPR2
F82h
PORTC
F62h
CAP2CON
FE1h
FSR1L
FC1h
ADCON1
FA1h
PIR2
F81h
PORTB
F61h
CAP3CON
FE0h
BSR
FC0h
ADCON2
FA0h
PIE2
F80h
PORTA
F60h
DFLTCON
Note 1:
2:
3:
DS39616D-page 69
PIC18F2331/2431/4331/4431
TABLE 6-2:
File Name
Bit 6
Bit 5
TOSU
TOSH
TOSL
STKUNF
PCLATU
bit 21(3)
PCL
TBLPTRU
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR, BOR
---0 0000
0000 0000
0000 0000
STKPTR
PCLATH
Bit 4
SP4
SP3
SP2
SP1
SP0
00-0 0000
---0 0000
0000 0000
0000 0000
bit 21(3)
--00 0000
TBLPTRH
0000 0000
TBLPTRL
0000 0000
TABLAT
0000 0000
PRODH
xxxx xxxx
PRODL
INTCON
xxxx xxxx
GIE/GIEH
PEIE/GIEL
TMR0IE
INT0IE
RBIE
TMR0IF
INTCON2
RBPU
INTEDG0
INTEDG1
INTCON3
INT2IP
INT1IP
INT0IF
RBIF
INTEDG2
TMR0IP
RBIP
1111 -1-1
INT2IE
INT1IE
INT2IF
INT1IF
11-0 0-00
0000 000x
INDF0
Uses contents of FSR0 to address data memory value of FSR0 not changed (not a physical register)
N/A
POSTINC0
Uses contents of FSR0 to address data memory value of FSR0 post-incremented (not a physical register)
N/A
POSTDEC0
Uses contents of FSR0 to address data memory value of FSR0 post-decremented (not a physical register)
N/A
PREINC0
Uses contents of FSR0 to address data memory value of FSR0 pre-incremented (not a physical register)
N/A
PLUSW0
Uses contents of FSR0 to address data memory value of FSR0 offset by W (not a physical register)
FSR0H
N/A
---- xxxx
FSR0L
xxxx xxxx
WREG
Working Register
xxxx xxxx
INDF1
Uses contents of FSR1 to address data memory value of FSR1 not changed (not a physical register)
N/A
POSTINC1
Uses contents of FSR1 to address data memory value of FSR1 post-incremented (not a physical register)
N/A
POSTDEC1
Uses contents of FSR1 to address data memory value of FSR1 post-decremented (not a physical register)
N/A
PREINC1
Uses contents of FSR1 to address data memory value of FSR1 pre-incremented (not a physical register)
N/A
PLUSW1
Uses contents of FSR1 to address data memory value of FSR1 offset by W (not a physical register)
FSR1H
FSR1L
N/A
---- 0000
BSR
xxxx xxxx
---- 0000
INDF2
Uses contents of FSR2 to address data memory value of FSR2 not changed (not a physical register)
N/A
POSTINC2
Uses contents of FSR2 to address data memory value of FSR2 post-incremented (not a physical register)
N/A
POSTDEC2
Uses contents of FSR2 to address data memory value of FSR2 post-decremented (not a physical register)
N/A
PREINC2
Uses contents of FSR2 to address data memory value of FSR2 pre-incremented (not a physical register)
N/A
PLUSW2
Uses contents of FSR2 to address data memory value of FSR2 offset by W (not a physical register)
FSR2H
FSR2L
TMR0H
TMR0L
Legend:
Note 1:
2:
3:
4:
5:
N/A
---- 0000
STATUS
T0CON
TMR0ON
T016BIT
xxxx xxxx
N
OV
DC
---x xxxx
0000 0000
xxxx xxxx
T0CS
T0SE
PSA
T0PS2
T0PS1
T0PS0
1111 1111
x = unknown, u = unchanged, - = unimplemented, q = value depends on condition. Shaded cells are unimplemented.
RA6 and associated bits are configured as port pins in RCIO, ECIO and INTIO2 (with port function on RA6) Oscillator modes only and read
0 in all other oscillator modes.
RA7 and associated bits are configured as port pins in INTIO2 Oscillator mode only and read 0 in all other modes.
Bit 21 of the PC is only available in Test mode and Serial Programming modes.
These registers and/or bits are not implemented on the PIC18F2331/2431 devices and read as 0.
The RE3 port bit is only available for PIC18F4331/4431 devices when the MCLRE fuse (CONFIG3H<7>) is programmed to 0; otherwise, RE3
reads 0. This bit is read-only.
DS39616D-page 70
PIC18F2331/2431/4331/4431
TABLE 6-2:
File Name
OSCCON
IDLEN
IRCF2
IRCF1
IRCF0
OSTS
IOFS
SCS1
SCS0
0000 q000
LVDCON
IRVST
LVDEN
LVDL3
LVDL2
LVDL1
LVDL0
--00 0101
WDTCON
WDTW
SWDTEN
0--- ---0
IPEN
RI
TO
PD
POR
BOR
0--1 11q0
RCON
Bit 5
TMR1H
TMR1L
T1CON
RD16
T1RUN
TMR2
Timer2 Register
PR2
T2CON
Bit 4
Bit 3
Bit 2
Bit 1
xxxx xxxx
xxxx xxxx
T1CKPS1
T1CKPS0
T1OSCEN
T1SYNC
TMR1CS
0000 0000
1111 1111
TOUTPS3
TOUTPS2
TOUTPS1
TOUTPS0
TMR2ON
T2CKPS1
SSPADD
SSP Address Register in I2C Slave mode. SSP Baud Rate Reload Register in I2C Master mode.
SSPCON
TMR1ON
0000 0000
SSPBUF
SSPSTAT
Bit 0
Value on
POR, BOR
Bit 7
T2CKPS0
-000 0000
xxxx xxxx
0000 0000
SMP
CKE
D/A
R/W
UA
BF
0000 0000
WCOL
SSPOV
SSPEN
CKP
SSPM3
SSPM2
SSPM1
SSPM0
0000 0000
ADRESH
ADRESL
xxxx xxxx
xxxx xxxx
ADCON0
ACONV
ACSCH
ACMOD1
ACMOD0
GO/DONE
ADON
--00 0000
ADCON1
VCFG1
VCFG0
FIFOEN
BFEMT
BFOVFL
ADPNT1
ADPNT0
00-0 0000
ADCON2
ADFM
ACQT3
ACQT2
ACQT1
ACQT0
ADCS2
ADCS1
ADCS0
0000 0000
ADCON3
ADRS1
ADRS0
SSRC4
SSRC3
SSRC2
SSRC1
SSRC0
00-0 0000
GDSEL1
GDSEL0
GBSEL1
GBSEL0
GCSEL1
GCSEL0
GASEL1
GASEL0
0000 0000
ADCHS
CCPR1H
CCPR1L
CCP1CON
DC1B1
CCPR2H
CCPR2L
xxxx xxxx
xxxx xxxx
DC1B0
CCP1M3
CCP1M2
CCP1M1
CCP1M0
--00 0000
xxxx xxxx
xxxx xxxx
CCP2CON
DC2B1
DC2B0
CCP2M3
CCP2M2
CCP2M1
CCP2M0
--00 0000
ANSEL1
ANS8(4)
---- ---1
ANSEL0
ANS7(4)
ANS6(4)
ANS5(4)
ANS4
ANS3
ANS2
ANS1
ANS0
1111 1111
(4)
T5CON
T5SEN
RESEN
QEICON
VELM
QERR
T5MOD
T5PS1
T5PS0
T5SYNC
TMR5CS
TMR5ON
0000 0000
UP/DOWN
QEIM2
QEIM1
QEIM0
PDEC1
PDEC0
0000 0000
SPBRGH
0000 0000
SPBRG
0000 0000
RCREG
0000 0000
TXREG
0000 0000
TXSTA
CSRC
TX9
TXEN
SYNC
SENDB
BRGH
TRMT
TX9D
0000 0010
RCSTA
SPEN
RX9
SREN
CREN
ADDEN
FERR
OERR
RX9D
0000 000X
RCIDL
SCKP
BRG16
WUE
ABDEN
-1-1 0-00
BAUDCON
Legend:
Note 1:
2:
3:
4:
5:
x = unknown, u = unchanged, - = unimplemented, q = value depends on condition. Shaded cells are unimplemented.
RA6 and associated bits are configured as port pins in RCIO, ECIO and INTIO2 (with port function on RA6) Oscillator modes only and read
0 in all other oscillator modes.
RA7 and associated bits are configured as port pins in INTIO2 Oscillator mode only and read 0 in all other modes.
Bit 21 of the PC is only available in Test mode and Serial Programming modes.
These registers and/or bits are not implemented on the PIC18F2331/2431 devices and read as 0.
The RE3 port bit is only available for PIC18F4331/4431 devices when the MCLRE fuse (CONFIG3H<7>) is programmed to 0; otherwise, RE3
reads 0. This bit is read-only.
DS39616D-page 71
PIC18F2331/2431/4331/4431
TABLE 6-2:
File Name
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR, BOR
EEADR
0000 0000
EEDATA
0000 0000
EECON2
EECON1
0000 0000
EEPGD
CFGS
FREE
WRERR
WREN
WR
RD
xx-0 x000
IPR3
PTIP
IC3DRIP
IC2QEIP
IC1IP
TMR5IP
---1 1111
PIR3
PTIF
IC3DRIF
IC2QEIF
IC1IF
TMR5IF
---0 0000
PIE3
PTIE
IC3DRIE
IC2QEIE
IC1IE
TMR5IE
---0 0000
IPR2
OSCFIP
EEIP
LVDIP
CCP2IP
1--1 -1-1
PIR2
OSCFIF
EEIF
LVDIF
CCP2IF
0--0 -0-0
PIE2
OSCFIE
EEIE
LVDIE
CCP2IE
0--0 -0-0
IPR1
ADIP
RCIP
TXIP
SSPIP
CCP1IP
TMR2IP
TMR1IP
-111 1111
PIR1
ADIF
RCIF
TXIF
SSPIF
CCP1IF
TMR2IF
TMR1IF
-000 0000
PIE1
ADIE
RCIE
TXIE
SSPIE
CCP1IE
TMR2IE
TMR1IE
-000 0000
OSCTUNE
TUN5
TUN4
TUN3
TUN2
TUN1
TUN0
--00 0000
ADCON3
ADRS1
ADRS0
SSRC4
SSRC3
SSRC2
SSRC1
SSRC0
00-0 0000
ADCHS
GDSEL1
GDSEL0
GBSEL1
GBSEL0
GCSEL1
GCSEL0
GASEL1
GASEL0
0000 0000
TRISE(4)
---- -111
TRISD(4)
1111 1111
TRISC
1111 1111
TRISB
TRISA
TRISA6(1)
1111 1111
PR5H
PR5L
LATE(4)
1111 1111
1111 1111
1111 1111
---- -xxx
LATD(4)
xxxx xxxx
LATC
xxxx xxxx
LATB
LATA
LATA6(1)
TMR5H
TMR5L
PORTE
xxxx xxxx
LATA Data Output Register
xxxx xxxx
xxxx xxxx
xxxx xxxx
RE3(4,5)
RE2(4)
RE1(4)
RE0(4)
---- xxxx
PORTD(4)
RD7
RD6
RD5
RD4
RD3
RD2
RD1
RD0
xxxx xxxx
PORTC
RC7
RC6
RC5
RC4
RC3
RC2
RC1
RC0
xxxx xxxx
PORTB
RB7
RB6
RB5
RB4
RB3
RB2
RB1
RB0
xxxx xxxx
PORTA
RA7(2)
RA6(1)
RA5
RA4
RA3
RA2
RA1
RA0
xx0x 0000
PTCON0
PTOPS3
PTOPS2
PTOPS1
PTOPS0
PTCKPS1
PTCKPS0
PTMOD1
PTMOD0
0000 0000
PTCON1
PTEN
PTDIR
00-- ----
PTMRL
PTMRH
PTPERL
UNUSED
PWM Time Base Period Register (lower 8 bits)
PTPERH
Legend:
Note 1:
2:
3:
4:
5:
0000 0000
PWM Time Base Register (upper 4 bits)
UNUSED
---- 0000
1111 1111
---- 1111
x = unknown, u = unchanged, - = unimplemented, q = value depends on condition. Shaded cells are unimplemented.
RA6 and associated bits are configured as port pins in RCIO, ECIO and INTIO2 (with port function on RA6) Oscillator modes only and read
0 in all other oscillator modes.
RA7 and associated bits are configured as port pins in INTIO2 Oscillator mode only and read 0 in all other modes.
Bit 21 of the PC is only available in Test mode and Serial Programming modes.
These registers and/or bits are not implemented on the PIC18F2331/2431 devices and read as 0.
The RE3 port bit is only available for PIC18F4331/4431 devices when the MCLRE fuse (CONFIG3H<7>) is programmed to 0; otherwise, RE3
reads 0. This bit is read-only.
DS39616D-page 72
PIC18F2331/2431/4331/4431
TABLE 6-2:
File Name
PDC0L
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PDC0H
PDC1L
0000 0000
UNUSED
--00 0000
PDC1H
PDC2L
0000 0000
UNUSED
--00 0000
PDC2H
PDC3L(4)
0000 0000
UNUSED
--00 0000
PDC3H(4)
SEVTCMPL
0000 0000
UNUSED
--00 0000
SEVTCMPH
Value on
POR, BOR
0000 0000
PWM Special Event Compare Register (upper 4 bits)
UNUSED
---- 0000
PWMCON0
PWMEN2
PWMEN1
PWMEN0
PMOD3
PMOD2
PMOD1
PMOD0
-111 0000
PWMCON1
SEVOPS3
SEVOPS2
SEVOPS1
SEVOPS0
SEVTDIR
UDIS
OSYNC
0000 0-00
DTCON
DTPS1
DTPS0
DT5
DT4
DT3
DT2
DT1
DT0
0000 0000
FLTCONFIG
BRFEN
FLTBS(4)
FLTBMOD(4)
FLTBEN(4)
FLTCON
FLTAS
FLTAMOD
FLTAEN
0000 0000
OVDCOND
POVD7(4)
POVD6(4)
POVD5
POVD4
POVD3
POVD2
POVD1
POVD0
1111 1111
OVDCONS
POUT7(4)
POUT6(4)
POUT5
POUT4
POUT3
POUT2
POUT1
POUT0
0000 0000
CAP1BUFH/
VELRH
xxxx xxxx
CAP1BUFL/
VELRL
xxxx xxxx
CAP2BUFH/
POSCNTH
xxxx xxxx
CAP2BUFL/
POSCNTL
xxxx xxxx
CAP3BUFH/
MAXCNTH
Capture 3 Register High Byte/QEI Max. Count Limit Register High Byte
xxxx xxxx
CAP3BUFL/
MAXCNTL
Capture 3 Register Low Byte/QEI Max. Count Limit Register Low Byte
xxxx xxxx
CAP1CON
CAP1REN
CAP1M3
CAP1M2
CAP1M1
CAP1M0
-0-- 0000
CAP2CON
CAP2REN
CAP2M3
CAP2M2
CAP2M1
CAP2M0
-0-- 0000
CAP3CON
CAP3REN
CAP3M3
CAP3M2
CAP3M1
CAP3M0
-0-- 0000
DFLTCON
FLT4EN
FLT3EN
FLT2EN
FLT1EN
FLTCK2
FLTCK1
FLTCK0
-000 0000
Legend:
Note 1:
2:
3:
4:
5:
x = unknown, u = unchanged, - = unimplemented, q = value depends on condition. Shaded cells are unimplemented.
RA6 and associated bits are configured as port pins in RCIO, ECIO and INTIO2 (with port function on RA6) Oscillator modes only and read
0 in all other oscillator modes.
RA7 and associated bits are configured as port pins in INTIO2 Oscillator mode only and read 0 in all other modes.
Bit 21 of the PC is only available in Test mode and Serial Programming modes.
These registers and/or bits are not implemented on the PIC18F2331/2431 devices and read as 0.
The RE3 port bit is only available for PIC18F4331/4431 devices when the MCLRE fuse (CONFIG3H<7>) is programmed to 0; otherwise, RE3
reads 0. This bit is read-only.
DS39616D-page 73
PIC18F2331/2431/4331/4431
6.6
STATUS Register
REGISTER 6-2:
U-0
STATUS REGISTER
U-0
U-0
R/W-x
N
R/W-x
R/W-x
R/W-x
R/W-x
DC(1)
C(2)
OV
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
-n = Value at POR
1 = Bit is set
0 = Bit is cleared
x = Bit is unknown
bit 7-5
Unimplemented: Read as 0
bit 4
N: Negative bit
This bit is used for signed arithmetic (2s complement). It indicates whether the result was negative
(ALU MSB = 1).
1 = Result was negative
0 = Result was positive
bit 3
bit 2
Z: Zero bit
1 = The result of an arithmetic or logic operation is zero
0 = The result of an arithmetic or logic operation is not zero
bit 1
bit 0
C: Carry/Borrow bit(2)
For ADDWF, ADDLW, SUBLW and SUBWF instructions:
1 = A carry-out from the Most Significant bit of the result occurred
0 = No carry-out from the Most Significant bit of the result occurred
Note 1:
2:
For Borrow, the polarity is reversed. A subtraction is executed by adding the 2s complement of the second
operand. For rotate (RRF, RLF) instructions, this bit is loaded with either bit 4 or bit 3 of the source register.
For Borrow, the polarity is reversed. A subtraction is executed by adding the 2s complement of the
second operand. For rotate (RRF, RLF) instructions, this bit is loaded with either the high or low-order bit
of the source register.
DS39616D-page 74
PIC18F2331/2431/4331/4431
6.7
Inherent
Literal
Direct
Indirect
6.7.1
6.7.3
INHERENT AND LITERAL
ADDRESSING
6.7.2
DIRECT ADDRESSING
INDIRECT ADDRESSING
EXAMPLE 6-5:
NEXT
LFSR
CLRF
BTFSS
BRA
CONTINUE
DS39616D-page 75
PIC18F2331/2431/4331/4431
6.7.3.1
6.7.3.2
FIGURE 6-7:
INDIRECT ADDRESSING
000h
Bank 0
ADDWF, INDF1, 1
100h
Bank 1
200h
300h
FSR1H:FSR1L
7
x x x x 1 1 1 0
Bank 2
Bank 3
through
Bank 13
1 1 0 0 1 1 0 0
E00h
Bank 14
F00h
FFFh
Bank 15
Data Memory
DS39616D-page 76
PIC18F2331/2431/4331/4431
The PLUSW register can be used to implement a form
of Indexed Addressing in the data memory space. By
manipulating the value in the W register, users can
reach addresses that are fixed offsets from pointer
addresses. In some applications, this can be used to
implement some powerful program control structure,
such as software stacks, inside of data memory.
6.7.3.3
DS39616D-page 77
PIC18F2331/2431/4331/4431
NOTES:
DS39616D-page 78
PIC18F2331/2431/4331/4431
7.0
7.2
EECON1
EECON2
EEDATA
EEADR
7.1
EEADR
DS39616D-page 79
PIC18F2331/2431/4331/4431
REGISTER 7-1:
R/W-x
R/W-x
U-0
R/W-0
R/W-x
R/W-0
R/S-0
R/S-0
EEPGD
CFGS
FREE
WRERR(1)
WREN
WR
RD
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
-n = Value at POR
1 = Bit is set
0 = Bit is cleared
x = Bit is unknown
bit 7
bit 6
bit 5
Unimplemented: Read as 0
bit 4
bit 3
bit 2
bit 1
bit 0
Note 1:
When a WRERR occurs, the EEPGD and CFGS bits are not cleared. This allows tracing of the error
condition.
DS39616D-page 80
PIC18F2331/2431/4331/4431
7.3
7.4
EXAMPLE 7-1:
MOVLW
MOVWF
BCF
BSF
MOVF
7.5
Write Verify
7.6
EXAMPLE 7-2:
Required
Sequence
;
;
;
;
;
MOVLW
MOVWF
MOVLW
MOVWF
BCF
BCF
BSF
BCF
MOVLW
MOVWF
MOVLW
MOVWF
BSF
BTFSC
DATA_EE_ADDR
EEADR
DATA_EE_DATA
EEDATA
EECON1, EEPGD
EECON1, CFGS
EECON1, WREN
INTCON, GIE
55h
EECON2
0AAh
EECON2
EECON1, WR
EECON1, WR
;
;
;
;
;
;
;
;
;
;
;
;
;
;
GOTO
BSF
$-2
INTCON, GIE
;
; Enable interrupts
DS39616D-page 81
PIC18F2331/2431/4331/4431
7.7
7.8
7.9
The data EEPROM is a high-endurance, byteaddressable array that has been optimized for the
storage of frequently changing information (e.g.,
program variables or other data that are updated
often). Frequently changing values will typically be
updated more often than Specification D124. If this is
not the case, an array refresh must be performed. For
this reason, variables that change infrequently (such as
constants, IDs, calibration, etc.) should be stored in
Flash program memory.
A simple data EEPROM refresh routine is shown in
Example 7-3.
Note:
If data EEPROM is only used to store constants and/or data that changes rarely, an
array refresh is likely not required. See
Specification D124.
EXAMPLE 7-3:
CLRF
BCF
BCF
BCF
BSF
EEADR
EECON1,
EECON1,
INTCON,
EECON1,
BSF
MOVLW
MOVWF
MOVLW
MOVWF
BSF
BTFSC
BRA
INCFSZ
BRA
EECON1, RD
55h
EECON2
0AAh
EECON2
EECON1, WR
EECON1, WR
$-2
EEADR, F
LOOP
BCF
BSF
EECON1, WREN
INTCON, GIE
CFGS
EEPGD
GIE
WREN
LOOP
Required
Sequence
DS39616D-page 82
;
;
;
;
;
;
;
;
;
;
;
;
;
Start at address 0
Set for memory
Set for Data EEPROM
Disable interrupts
Enable writes
Loop to refresh array
Read current address
Write 55h
Write 0AAh
Set WR bit to begin write
Wait for write to complete
; Increment address
; Not zero, do it again
; Disable writes
; Enable interrupts
PIC18F2331/2431/4331/4431
TABLE 7-1:
Name
INTCON
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reset
Values on
page
GIE/GIEH
PEIE/GIEL
TMR0IE
INT0IE
RBIE
TMR0IF
INT0IF
RBIF
54
EEADR
56
EEDATA
56
EECON2
56
EECON1
EEPGD
CFGS
FREE
WRERR
WREN
WR
RD
56
IPR2
OSCFIP
EEIP
LVDIP
CCP2IP
57
PIR2
OSCFIF
EEIF
LVDIF
CCP2IF
57
PIE2
OSCFIE
EEIE
LVDIE
CCP2IE
57
Legend: = unimplemented, read as 0. Shaded cells are not used during Flash/EEPROM access.
DS39616D-page 83
PIC18F2331/2431/4331/4431
NOTES:
DS39616D-page 84
PIC18F2331/2431/4331/4431
8.0
8.1
FIGURE 8-1:
Program Memory
Table Pointer(1)
TBLPTRU
TBLPTRH
TBLPTRL
Program Memory
(TBLPTR)
Note 1:
DS39616D-page 85
PIC18F2331/2431/4331/4431
FIGURE 8-2:
TBLPTRU
TBLPTRH
TABLAT
Program Memory
(TBLPTR)
Note 1:
8.2
The Table Pointer actually points to one of eight holding registers, the address of which is determined
by TBLPTRL<2:0>. The process for physically writing data to the program memory array is discussed
in Section 8.5 Writing to Flash Program Memory.
Control Registers
EECON1 register
EECON2 register
TABLAT register
TBLPTR registers
8.2.1
The FREE bit controls program memory erase operations. When the FREE bit is set, the erase operation is
initiated on the next WR command. When FREE is
clear, only writes are enabled.
A write operation is allowed when the WREN bit
(EECON1<2>) is set. On power-up, the WREN bit is
clear. The WRERR bit (EECON1<3>) is set in hardware when the WR bit (EECON1<1>) is set and
cleared when the internal programming timer expires
and the write operation is complete.
Note:
DS39616D-page 86
PIC18F2331/2431/4331/4431
REGISTER 8-1:
R/W-x
R/W-x
U-0
R/W-0
R/W-x
R/W-0
R/S-0
R/S-0
EEPGD
CFGS
FREE
WRERR(1)
WREN
WR
RD
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
-n = Value at POR
1 = Bit is set
0 = Bit is cleared
x = Bit is unknown
bit 7
bit 6
bit 5
Unimplemented: Read as 0
bit 4
bit 3
bit 2
bit 1
bit 0
Note 1:
When a WRERR occurs, the EEPGD and CFGS bits are not cleared. This allows tracing of the error
condition.
DS39616D-page 87
PIC18F2331/2431/4331/4431
8.2.2
8.2.4
8.2.3
The TBLPTR is used by the TBLRD and TBLWT instructions. These instructions can update the TBLPTR in
one of four ways based on the table operation. These
operations are shown in Table 8-1. These operations
on the TBLPTR only affect the low-order 21 bits.
TABLE 8-1:
Example
TBLRD*
TBLWT*
TBLRD*+
TBLWT*+
TBLRD*TBLWT*-
TBLRD+*
TBLWT+*
FIGURE 8-3:
21
16
15
TBLPTRH
TABLE ERASE/WRITE
TBLPTR<21:6>
TBLPTRL
TABLE WRITE
TBLPTR<5:0>
DS39616D-page 88
PIC18F2331/2431/4331/4431
8.3
FIGURE 8-4:
Program Memory
TBLPTR = xxxxx1
Instruction Register
(IR)
EXAMPLE 8-1:
FETCH
TBLRD
TBLPTR = xxxxx0
TABLAT
Read Register
MOVLW
MOVWF
MOVLW
MOVWF
MOVLW
MOVWF
CODE_ADDR_UPPER
TBLPTRU
CODE_ADDR_HIGH
TBLPTRH
CODE_ADDR_LOW
TBLPTRL
READ_WORD
TBLRD*+
MOVF
MOVWF
TBLRD*+
MOVF
MOVWF
TABLAT,W
WORD_EVEN
TABLAT,W
WORD_ODD
DS39616D-page 89
PIC18F2331/2431/4331/4431
8.4
8.4.1
When initiating an erase sequence from the microcontroller itself, a block of 64 bytes of program memory
is erased. The Most Significant 16 bits of the
TBLPTR<21:6> point to the block being erased;
TBLPTR<5:0> are ignored.
2.
3.
4.
5.
6.
7.
8.
9.
EXAMPLE 8-2:
CODE_ADDR_UPPER
TBLPTRU
CODE_ADDR_HIGH
TBLPTRH
CODE_ADDR_LOW
TBLPTRL
BSF
BCF
BSF
BSF
BCF
MOVLW
MOVWF
MOVLW
MOVWF
BSF
NOP
BSF
EECON1,
EECON1,
EECON1,
EECON1,
INTCON,
55h
EECON2
0AAh
EECON2
EECON2,
;
;
;
;
;
ERASE_ROW
Required
Sequence
DS39616D-page 90
EEPGD
CFGS
WREN
FREE
GIE
; write 55H
WR
INTCON, GIE
; write 0AAH
; start erase (CPU stall)
; re-enable interrupts
PIC18F2331/2431/4331/4431
The programming block size is 4 words or 8 bytes.
Word or byte programming is not supported.
8.5
FIGURE 8-5:
Note:
8
TBLPTR = xxxxx0
TBLPTR = xxxxx1
Holding Register
8
TBLPTR = xxxxx2
Holding Register
Holding Register
8
TBLPTR = xxxxx7
Holding Register
Program Memory
DS39616D-page 91
PIC18F2331/2431/4331/4431
8.5.1
7.
8.
9.
10.
11.
12.
13.
14.
15.
16.
DS39616D-page 92
PIC18F2331/2431/4331/4431
EXAMPLE 8-3:
MOVLW
MOVWF
MOVLW
MOVWF
MOVLW
MOVWF
MOVLW
MOVWF
MOVLW
MOVWF
MOVLW
MOVWF
D'64'
COUNTER
BUFFER_ADDR_HIGH
FSR0H
BUFFER_ADDR_LOW
FSR0L
CODE_ADDR_UPPER
TBLPTRU
CODE_ADDR_HIGH
TBLPTRH
CODE_ADDR_LOW
TBLPTRL
TBLRD*+
MOVF
MOVWF
DECFSZ
BRA
TABLAT,W
POSTINC0
COUNTER
READ_BLOCK
MOVLW
MOVWF
MOVLW
MOVWF
MOVLW
MOVWF
MOVLW
MOVWF
DATA_ADDR_HIGH
FSR0H
DATA_ADDR_LOW
FSR0L
NEW_DATA_LOW
POSTINC0
NEW_DATA_HIGH
INDF0
; 6 LSB = 0
READ_BLOCK
;
;
;
;
;
MODIFY_WORD
; point to buffer
ERASE_BLOCK
MOVLW
CODE_ADDR_UPPER
MOVWF
TBLPTRU
MOVLW
CODE_ADDR_HIGH
MOVWF
TBLPTRH
MOVLW
CODE_ADDR_LOW
MOVWF
TBLPTRL
BCF
EECON1, CFGS
BSF
EECON1, EEPGD
BSF
EECON1, WREN
BSF
EECON1, FREE
BCF
INTCON, GIE
MOVLW
55h
MOVWF
EECON2
MOVLW
0AAh
MOVWF
EECON2
BSF
EECON1, WR
NOP
BSF
INTCON, GIE
WRITE_BUFFER_BACK
MOVLW
8
MOVWF
COUNTER_HI
MOVLW
BUFFER_ADDR_HIGH
MOVWF
FSR0H
MOVLW
BUFFER_ADDR_LOW
MOVWF
FSR0L
PROGRAM_LOOP
MOVLW
8
MOVWF
COUNTER
WRITE_WORD_TO_HREGS
MOVF
POSTINC0,F
MOVWF
TABLAT
TBLWT+*
DECFSZ COUNTER
GOTO
WRITE_WORD_TO_HREGS
; 6 LSB = 0
;
;
;
;
;
;
;
; write 0AAh
; start erase (CPU stall)
; re-enable interrupts
; number of write buffer groups of 8 bytes
; point to buffer
;
;
;
;
;
;
DS39616D-page 93
PIC18F2331/2431/4331/4431
EXAMPLE 8-3:
PROGRAM_MEMORY
BCF
MOVLW
MOVWF
MOVLW
MOVWF
BSF
NOP
BSF
DECFSZ
GOTO
BCF
8.5.2
INTCON, GIE
55h
EECON2
0AAh
EECON2
EECON1, WR
; disable interrupts
; required sequence
; write 55h
INTCON, GIE
COUNTER_HI
PROGRAM_LOOP
EECON1, WREN
; re-enable interrupts
; loop until done
; write 0AAh
; start program (CPU stall)
WRITE VERIFY
8.5.3
8.6
UNEXPECTED TERMINATION OF
WRITE OPERATION
TABLE 8-2:
Name
Bit 7
Bit 6
TBLPTRU
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reset
Values
on Page:
54
54
54
TABLAT
54
INTCON
INT0IE
RBIE
TMR0IF
INT0IF
RBIF
54
56
EECON1
EEPGD
CFGS
FREE
WRERR
WREN
WR
RD
56
IPR2
OSCFIP
EEIP
LVDIP
CCP2IP
57
PIR2
OSCFIF
EEIF
LVDIF
CCP2IF
57
PIE2
OSCFIE
EEIE
LVDIE
CCP2IE
57
Legend: = unimplemented, read as 0. Shaded cells are not used during Flash/EEPROM access.
Note 1: Bit 21 of the PC is only available in Test mode and Serial Programming modes.
DS39616D-page 94
PIC18F2331/2431/4331/4431
9.0
8 x 8 HARDWARE MULTIPLIER
9.1
Introduction
9.2
EXAMPLE 9-1:
MOVF
MULWF
A comparison of various hardware and software multiply operations, along with the savings in memory and
execution time, is shown in Table 9-1.
TABLE 9-1:
8 x 8 UNSIGNED MULTIPLY
ROUTINE
ARG1, W
ARG2
EXAMPLE 9-2:
;
; ARG1 * ARG2 ->
; PRODH:PRODL
8 x 8 SIGNED MULTIPLY
ROUTINE
MOVF
MULWF
ARG1, W
ARG2
BTFSC
SUBWF
ARG2, SB
PRODH, F
MOVF
BTFSC
SUBWF
ARG2, W
ARG1, SB
PRODH, F
;
;
;
;
;
PERFORMANCE COMPARISON
Routine
8 x 8 Unsigned
8 x 8 Signed
16 x 16 Unsigned
16 x 16 Signed
Operation
Program
Memory
(Words)
Cycles
(Max)
13
Hardware Multiply
33
Hardware Multiply
Multiply Method
Time
@ 40 MHz
@ 10 MHz
@ 4 MHz
69
6.9 s
27.6 s
69 s
100 ns
400 ns
1 s
91
9.1 s
36.4 s
91 s
600 ns
2.4 s
6 s
21
242
24.2 s
96.8 s
242 s
24
24
2.4 s
9.6 s
24 s
52
254
25.4 s
102.6 s
254 s
36
36
3.6 s
14.4 s
36 s
DS39616D-page 95
PIC18F2331/2431/4331/4431
Example 9-3 shows the sequence to do a 16 x 16
unsigned multiply. Equation 9-1 shows the algorithm
that is used. The 32-bit result is stored in four registers,
RES<3:0>.
EQUATION 9-1:
RES<3:0>
=
=
16 x 16 UNSIGNED
MULTIPLICATION
ALGORITHM
ARG1H:ARG1L ARG2H:ARG2L
(ARG1H ARG2H 216) +
(ARG1H ARG2L 28) +
(ARG1L ARG2H 28) +
(ARG1L ARG2L)
EXAMPLE 9-3:
EQUATION 9-2:
RES<3:0>
= ARG1H:ARG1L ARG2H:ARG2L
= (ARG1H ARG2H 216) +
(ARG1H ARG2L 28) +
(ARG1L ARG2H 28) +
(ARG1L ARG2L)+
(-1 ARG2H<7> ARG1H:ARG1L 216) +
(-1 ARG1H<7> ARG2H:ARG2L 216)
EXAMPLE 9-4:
16 x 16 UNSIGNED
MULTIPLY ROUTINE
MOVF
MULWF
ARG1L, W
ARG2L
MOVFF
MOVFF
PRODH, RES1
PRODL, RES0
MOVF
MULWF
ARG1H, W
ARG2H
MOVFF
MOVFF
PRODH, RES3
PRODL, RES2
MOVF
MULWF
ARG1L, W
ARG2H
MOVF
ADDWF
MOVF
ADDWFC
CLRF
ADDWFC
PRODL, W
RES1, F
PRODH, W
RES2, F
WREG
RES3, F
MOVF
MULWF
ARG1H, W
ARG2L
MOVF
ADDWF
MOVF
ADDWFC
CLRF
ADDWFC
PRODL, W
RES1, F
PRODH, W
RES2, F
WREG
RES3, F
MOVF
MULWF
16 x 16 SIGNED MULTIPLY
ROUTINE
ARG1L, W
ARG2L
MOVFF
MOVFF
MOVF
MULWF
ARG1H, W
ARG2H
MOVFF
MOVFF
MOVF
MULWF
ARG1L,W
ARG2H
MOVF
ADDWF
MOVF
ADDWFC
CLRF
ADDWFC
PRODL, W
RES1, F
PRODH, W
RES2, F
WREG
RES3, F
MOVF
MULWF
ARG1H, W
ARG2L
MOVF
ADDWF
MOVF
ADDWFC
CLRF
ADDWFC
PRODL, W
RES1, F
PRODH, W
RES2, F
WREG
RES3, F
BTFSS
BRA
MOVF
SUBWF
MOVF
SUBWFB
ARG2H, 7
SIGN_ARG1
ARG1L, W
RES2
ARG1H, W
RES3
; ARG2H:ARG2L neg?
; no, check ARG1
;
;
;
ARG1H, 7
CONT_CODE
ARG2L, W
RES2
ARG2H, W
RES3
; ARG1H:ARG1L neg?
; no, done
;
;
;
;
; ARG1H * ARG2H ->
; PRODH:PRODL
;
;
16 x 16 SIGNED
MULTIPLICATION
ALGORITHM
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
DS39616D-page 96
Add cross
products
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
SIGN_ARG1
BTFSS
BRA
MOVF
SUBWF
MOVF
SUBWFB
;
CONT_CODE
:
PIC18F2331/2431/4331/4431
10.0
INTERRUPTS
RCON
INTCON
INTCON2
INTCON3
PIR1, PIR2, PIR3
PIE1, PIE2, PIE3
IPR1, IPR2, IPR3
It is recommended that the Microchip header files supplied with MPLAB IDE be used for the symbolic bit
names in these registers. This allows the assembler/
compiler to automatically take care of the placement of
these bits within the specified register.
In general, each interrupt source has three bits to
control its operation. The functions of these bits are:
Flag bit to indicate that an interrupt event
occurred
Enable bit that allows program execution to
branch to the interrupt vector address when the
flag bit is set
Priority bit to select high priority or low priority
(most interrupt sources have priority bits)
The interrupt priority feature is enabled by setting the
IPEN bit (RCON<7>). When interrupt priority is
enabled, there are two bits which enable interrupts
globally. Setting the GIEH bit (INTCON<7>) enables all
interrupts that have the priority bit set (high priority).
Setting the GIEL bit (INTCON<6>) enables all
interrupts that have the priority bit cleared (low priority).
When the interrupt flag, enable bit and appropriate
global interrupt enable bit are set, the interrupt will
vector immediately to address 000008h or 000018h
depending on the priority bit setting. Individual
interrupts can be disabled through their corresponding
enable bits.
DS39616D-page 97
PIC18F2331/2431/4331/4431
FIGURE 10-1:
INTERRUPT LOGIC
TMR0IF
TMR0IE
TMR0IP
RBIF
RBIE
RBIP
INT0IF
INT0IE
Wake-up if in
Power-Managed Mode
Interrupt to CPU
Vector to Location
0008h
INT1IF
INT1IE
INT1IP
INT2IF
INT2IE
INT2IP
TXIF
TXIE
TXIP
GIE/GIEH
ADIF
ADIE
ADIP
IPEN
IPEN
PEIE/GIEL
RCIF
RCIE
RCIP
IPEN
Additional Peripheral Interrupts
High-Priority Interrupt Generation
Low-Priority Interrupt Generation
TXIF
TXIE
TXIP
ADIF
ADIE
ADIP
RCIF
RCIE
RCIP
TMR0IF
TMR0IE
TMR0IP
RBIF
RBIE
RBIP
Interrupt to CPU
Vector to Location
0018h
PEIE/GIEL
INT0IF
INT0IE
INT1IF
DS39616D-page 98
PIC18F2331/2431/4331/4431
10.1
INTCON Registers
Note:
REGISTER 10-1:
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-x
GIE/GIEH
PEIE/GIEL
TMR0IE
INT0IE
RBIE
TMR0IF
INT0IF
RBIF
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
-n = Value at POR
1 = Bit is set
0 = Bit is cleared
x = Bit is unknown
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
DS39616D-page 99
PIC18F2331/2431/4331/4431
REGISTER 10-2:
R/W-1
R/W-1
R/W-1
R/W-1
U-0
R/W-1
U-0
R/W-1
RBPU
INTEDG0
INTEDG1
INTEDG2
TMR0IP
RBIP
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
-n = Value at POR
1 = Bit is set
0 = Bit is cleared
bit 7
bit 6
bit 5
bit 4
bit 3
Unimplemented: Read as 0
bit 2
bit 1
Unimplemented: Read as 0
bit 0
Note:
x = Bit is unknown
Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding
enable bit or the global enable bit. User software should ensure the appropriate interrupt flag bits are clear
prior to enabling an interrupt. This feature allows for software polling.
DS39616D-page 100
PIC18F2331/2431/4331/4431
REGISTER 10-3:
R/W-1
R/W-1
U-0
R/W-0
R/W-0
U-0
R/W-0
R/W-0
INT2IP
INT1IP
INT2IE
INT1IE
INT2IF
INT1IF
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
-n = Value at POR
1 = Bit is set
0 = Bit is cleared
bit 7
bit 6
bit 5
Unimplemented: Read as 0
bit 4
bit 3
bit 2
Unimplemented: Read as 0
bit 1
bit 0
Note:
x = Bit is unknown
Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding
enable bit or the global enable bit. User software should ensure the appropriate interrupt flag bits are clear
prior to enabling an interrupt. This feature allows for software polling.
DS39616D-page 101
PIC18F2331/2431/4331/4431
10.2
PIR Registers
The PIR registers contain the individual flag bits for the
peripheral interrupts. Due to the number of peripheral
interrupt sources, there are three Peripheral Interrupt
Request (Flag) Registers (PIR1, PIR2 and PIR3).
Note 1: Interrupt flag bits are set when an interrupt condition occurs, regardless of the
state of its corresponding enable bit or the
Global Interrupt Enable bit, GIE
(INTCON<7>).
2: User software should ensure the appropriate interrupt flag bits are cleared prior
to enabling an interrupt and after servicing
that interrupt.
REGISTER 10-4:
U-0
R/W-0
R-0
R-0
R/W-0
R/W-0
R/W-0
R/W-0
ADIF
RCIF
TXIF
SSPIF
CCP1IF
TMR2IF
TMR1IF
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
-n = Value at POR
1 = Bit is set
0 = Bit is cleared
x = Bit is unknown
bit 7
Unimplemented: Read as 0
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
DS39616D-page 102
PIC18F2331/2431/4331/4431
REGISTER 10-5:
R/W-0
U-0
U-0
R/W-0
U-0
R/W-0
U-0
R/W-0
OSCFIF
EEIF
LVDIF
CCP2IF
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
-n = Value at POR
1 = Bit is set
0 = Bit is cleared
x = Bit is unknown
bit 7
bit 6-5
Unimplemented: Read as 0
bit 4
bit 3
Unimplemented: Read as 0
bit 2
bit 1
Unimplemented: Read as 0
bit 0
DS39616D-page 103
PIC18F2331/2431/4331/4431
REGISTER 10-6:
U-0
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
PTIF
IC3DRIF
IC2QEIF
IC1IF
TMR5IF
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
-n = Value at POR
1 = Bit is set
0 = Bit is cleared
x = Bit is unknown
bit 7-5
Unimplemented: Read as 0
bit 4
bit 3
bit 2
bit 1
bit 0
DS39616D-page 104
PIC18F2331/2431/4331/4431
10.3
PIE Registers
REGISTER 10-7:
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
ADIE
RCIE
TXIE
SSPIE
CCP1IE
TMR2IE
TMR1IE
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
-n = Value at POR
1 = Bit is set
0 = Bit is cleared
bit 7
Unimplemented: Read as 0
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
x = Bit is unknown
DS39616D-page 105
PIC18F2331/2431/4331/4431
REGISTER 10-8:
R/W-0
U-0
U-0
R/W-0
U-0
R/W-0
U-0
R/W-0
OSCFIE
EEIE
LVDIE
CCP2IE
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
-n = Value at POR
1 = Bit is set
0 = Bit is cleared
bit 7
bit 6-5
Unimplemented: Read as 0
bit 4
bit 3
Unimplemented: Read as 0
bit 2
bit 1
Unimplemented: Read as 0
bit 0
DS39616D-page 106
x = Bit is unknown
PIC18F2331/2431/4331/4431
REGISTER 10-9:
U-0
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
PTIE
IC3DRIE
IC2QEIE
IC1IE
TMR5IE
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
-n = Value at POR
1 = Bit is set
0 = Bit is cleared
bit 7-5
Unimplemented: Read as 0
bit 4
bit 3
bit 2
bit 1
bit 0
x = Bit is unknown
DS39616D-page 107
PIC18F2331/2431/4331/4431
10.4
IPR Registers
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
ADIP
RCIP
TXIP
SSPIP
CCPIP
TMR2IP
TMR1IP
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
-n = Value at POR
1 = Bit is set
0 = Bit is cleared
bit 7
Unimplemented: Read as 0
bit 6
bit 5
bit 4
x = Bit is unknown
1 = High priority
0 = Low priority
bit 3
bit 2
bit 1
bit 0
DS39616D-page 108
PIC18F2331/2431/4331/4431
REGISTER 10-11: IPR2: PERIPHERAL INTERRUPT PRIORITY REGISTER 2
R/W-1
U-0
U-0
R/W-1
U-0
R/W-1
U-0
R/W-1
OSCFIP
EEIP
LVDIP
CCP2IP
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
-n = Value at POR
1 = Bit is set
0 = Bit is cleared
bit 7
bit 6-5
Unimplemented: Read as 0
bit 4
bit 3
Unimplemented: Read as 0
bit 2
bit 1
Unimplemented: Read as 0
bit 0
x = Bit is unknown
DS39616D-page 109
PIC18F2331/2431/4331/4431
REGISTER 10-12: IPR3: PERIPHERAL INTERRUPT PRIORITY REGISTER 3
U-0
U-0
U-0
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
PTIP
IC3DRIP
IC2QEIP
IC1IP
TMR5IP
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
-n = Value at POR
1 = Bit is set
0 = Bit is cleared
bit 7-5
Unimplemented: Read as 0
bit 4
bit 3
bit 2
bit 1
bit 0
DS39616D-page 110
x = Bit is unknown
PIC18F2331/2431/4331/4431
10.5
RCON Register
U-0
U-0
R/W-1
R-1
R-1
R/W-0
R/W-0
IPEN
RI
TO
PD
POR
BOR
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
-n = Value at POR
1 = Bit is set
0 = Bit is cleared
bit 7
bit 6-5
Unimplemented: Read as 0
bit 4
bit 3
bit 2
bit 1
bit 0
x = Bit is unknown
DS39616D-page 111
PIC18F2331/2431/4331/4431
10.6
10.7
EXAMPLE 10-1:
MOVWF
MOVFF
MOVFF
;
; USER
;
MOVFF
MOVF
MOVFF
TMR0 Interrupt
10.8
PORTB Interrupt-on-Change
10.9
W_TEMP
STATUS, STATUS_TEMP
BSR, BSR_TEMP
ISR CODE
BSR_TEMP, BSR
W_TEMP, W
STATUS_TEMP, STATUS
DS39616D-page 112
; Restore BSR
; Restore WREG
; Restore STATUS
PIC18F2331/2431/4331/4431
11.0
I/O PORTS
11.1
FIGURE 11-1:
RD LAT
Data
Bus
WR LAT
or PORT
Q
I/O Pin(1)
CK
Data Latch
D
WR TRIS
PORTA is an 8-bit wide, bidirectional port. The corresponding data direction register is TRISA. Setting a
TRISA bit (= 1) will make the corresponding PORTA pin
an input (i.e., put the corresponding output driver in a
high-impedance mode). Clearing a TRISA bit (= 0) will
make the corresponding PORTA pin an output (i.e., put
the contents of the output latch on the selected pin).
Reading the PORTA register reads the status of the
pins, whereas writing to it, will write to the port latch.
The Data Latch register (LATA) is also memory mapped.
Read-modify-write operations on the LATA register read
and write the latched output value for PORTA.
The RA<4:2> pins are multiplexed with three input
capture pins and Quadrature Encoder Interface pins.
Pins, RA6 and RA7, are multiplexed with the main
oscillator pins. They are enabled as oscillator or I/O
pins by the selection of the main oscillator in
Configuration Register 1H (see Section 23.1
Configuration Bits for details). When they are not
used as port pins, RA6 and RA7 and their associated
TRIS and LAT bits are read as 0.
The other PORTA pins are multiplexed with analog
inputs, the analog VREF+ and VREF- inputs and the comparator voltage reference output. The operation of pins
RA<3:0> and RA5 as A/D Converter inputs is selected
by clearing/setting the control bits in the ANSEL0 and
ANSEL1 registers.
Note 1: On a Power-on Reset, RA<5:0> are
configured as analog inputs and read as 0.
CK
TRIS Latch
Input
Buffer
RD TRIS
ENEN
EXAMPLE 11-1:
CLRF
RD PORT
CLRF
Note 1:
MOVLW
MOVWF
MOVLW
MOVWF
PORTA
;
;
;
LATA
;
;
;
0x3F
;
ANSEL0 ;
0xCF
;
;
;
TRISA
;
;
INITIALIZING PORTA
Initialize PORTA by
clearing output
data latches
Alternate method
to clear output
data latches
Configure A/D
for digital inputs
Value used to
initialize data
direction
Set RA<3:0> as inputs
RA<5:4> as outputs
DS39616D-page 113
PIC18F2331/2431/4331/4431
TABLE 11-1:
Pin
RA0/AN0
RA1/AN1
RA2/AN2/VREF-/
CAP1/INDX
RA3/AN3/VREF+/
CAP2/QEA
RA4/AN4/CAP3/
QEB
RA5/AN5/LVDIN
OSC2/CLKO/RA6
OSC1/CLKI/RA7
Legend:
Function
TRIS
Setting
I/O
I/O
Type
RA0
DIG
TTL
AN0
ANA
RA1
DIG
TTL
AN1
ANA
RA2
DIG
Description
LATA<0> data output; not affected by analog input.
TTL
AN2
ANA
VREF-
ANA
CAP1
ST
INDX
ST
RA3
DIG
TTL
AN3
ANA
VREF+
ANA
CAP2
ST
QEA
ST
RA4
DIG
ST
AN4
ANA
CAP3
ST
QEB
ST
RA5
DIG
TTL
AN5
ANA
LVDIN
ANA
OSC2
ANA
CLKO
DIG
RA6
DIG
LATA<6> data output. Enabled in RCIO, INTIO2 and ECIO modes only.
TTL
PORTA<6> data input. Enabled in RCIO, INTIO2 and ECIO modes only.
OSC1
ANA
CLKI
ANA
RA7
DIG
TTL
DIG = Digital level output; TTL = TTL input buffer; ST = Schmitt Trigger input buffer; ANA = Analog level input/output;
x = Dont care (TRIS bit does not affect port direction or is overridden for this option).
DS39616D-page 114
PIC18F2331/2431/4331/4431
TABLE 11-2:
Name
PORTA
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reset Values
on Page:
RA7(1)
RA6(1)
RA5
RA4
RA3
RA2
RA1
RA0
57
(1)
(1)
LATA
LATA7
LATA6
TRISA
TRISA7(1)
57
57
ADCON1
VCFG1
VCFG0
FIFOEN
BFEMT
BFOVFL
ADPNT1
ADPNT0
56
ANSEL0
ANS7(2)
ANS6(2)
ANS5(2)
ANS4
ANS3
ANS2
ANS1
ANS0
56
ANSEL1
ANS8(2)
56
DS39616D-page 115
PIC18F2331/2431/4331/4431
11.2
PORTB is an 8-bit wide, bidirectional port. The corresponding Data Direction register is TRISB. Setting a
TRISB bit (= 1) will make the corresponding PORTB
pin an input (i.e., put the corresponding output driver in
a high-impedance mode). Clearing a TRISB bit (= 0)
will make the corresponding PORTB pin an output (i.e.,
put the contents of the output latch on the selected pin).
The Data Latch register (LATB) is also memory
mapped. Read-modify-write operations on the LATB
register read and write the latched output value for
PORTB.
EXAMPLE 11-2:
CLRF
PORTB
CLRF
LATB
MOVLW
0xCF
MOVWF
TRISB
INITIALIZING PORTB
;
;
;
;
;
;
;
;
;
;
;
;
Initialize PORTB by
clearing output
data latches
Alternate method
to clear output
data latches
Value used to
initialize data
direction
Set RB<3:0> as inputs
RB<5:4> as outputs
RB<7:6> as inputs
DS39616D-page 116
Four of the PORTB pins (RB<7:4>) have an interrupton-change feature. Only pins configured as inputs can
cause this interrupt to occur (i.e., any RB<7:4> pin
configured as an output is excluded from the interrupton-change comparison). The input pins (of RB<7:4>)
are compared with the old value latched on the last
read of PORTB. The mismatch outputs of RB<7:4>
are ORed together to generate the RB port change
interrupt with flag bit, RBIF (INTCON<0>).
This interrupt can wake the device from Sleep. The
user, in the Interrupt Service Routine, can clear the
interrupt in the following manner:
a)
b)
c)
PIC18F2331/2431/4331/4431
TABLE 11-3:
Pin
RB0/PWM0
RB1/PWM1
RB2/PWM2
RB3/PWM3
RB4/KBI0/PWM5
TRIS
Setting
I/O
I/O
Type
RB0
DIG
TTL
PWM0
DIG
PWM Output 0.
RB1
DIG
TTL
PWM1
DIG
PWM Output 1.
RB2
DIG
TTL
PWM2
DIG
PWM Output 2.
RB3
DIG
TTL
PWM3
DIG
PWM Output 3.
RB4
DIG
TTL
TTL
Interrupt-on-change pin.
KBI0
RB5/KBI1/
PWM4/PGM
RB6/KBI2/PGC
RB7/KBI3/PGD
Legend:
Note 1:
2:
3:
Description
PWM5
DIG
PWM Output 5.
RB5
DIG
TTL
KBI1
TTL
Interrupt-on-change pin.
PWM4(3)
DIG
PGM(2)
ST
RB6
DIG
TTL
KBI2
TTL
Interrupt-on-change pin.
PGC
ST
Serial execution (ICSP) clock input for ICSP and ICD operation.(1)
RB7
DIG
TTL
KBI3
TTL
Interrupt-on-change pin.
PGD
DIG
ST
DIG = Digital level output; TTL = TTL input buffer; ST = Schmitt Trigger input buffer; ANA = Analog level input/output;
x = Dont care (TRIS bit does not affect port direction or is overridden for this option).
All other pin functions are disabled when ICSP or ICD is enabled.
Single-Supply Programming must be enabled.
RD5 is the alternate pin for PWM4.
DS39616D-page 117
PIC18F2331/2431/4331/4431
TABLE 11-4:
Name
PORTB
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reset Values
on Page:
RB7
RB6
RB5
RB4
RB3
RB2
RB1
RB0
57
LATB
57
TRISB
57
INTCON
GIE/GIEH
PEIE/GIEL
TMR0IE
INT0IE
INTCON2
RBPU
INTEDG0
INTEDG1
INTCON3
INT2IP
INT1IP
Legend:
RBIE
TMR0IF
INT0IF
RBIF
54
INTEDG2
TMR0IP
RBIP
54
INT2IE
INT1IE
INT2IF
INT1IF
54
DS39616D-page 118
PIC18F2331/2431/4331/4431
11.3
PORTC is an 8-bit wide, bidirectional port. The corresponding Data Direction register is TRISC. Setting a
TRISC bit (= 1) will make the corresponding PORTC
pin an input (i.e., put the corresponding output driver in
a high-impedance mode). Clearing a TRISC bit (= 0)
will make the corresponding PORTC pin an output (i.e.,
put the contents of the output latch on the selected pin).
The Data Latch register (LATC) is also memory
mapped. Read-modify-write operations on the LATC
register read and write the latched output value for
PORTC.
PORTC is multiplexed with several peripheral functions
(Table 11-5). The pins have Schmitt Trigger input
buffers.
When enabling peripheral functions, care should be
taken in defining TRIS bits for each PORTC pin. Some
peripherals override the TRIS bit to make a pin an output,
while other peripherals override the TRIS bit to make a
pin an input. The user should refer to the corresponding
peripheral section for the correct TRIS bit settings.
EXAMPLE 11-3:
Note:
CLRF
PORTC
CLRF
LATC
MOVLW
0xCF
MOVWF
TRISC
INITIALIZING PORTC
;
;
;
;
;
;
;
;
;
;
;
;
Initialize PORTC by
clearing output
data latches
Alternate method
to clear output
data latches
Value used to
initialize data
direction
Set RC<3:0> as inputs
RC<5:4> as outputs
RC<7:6> as inputs
DS39616D-page 119
PIC18F2331/2431/4331/4431
TABLE 11-5:
Pin
TRIS
Setting
I/O
I/O
Type
RC0
DIG
ST
ANA
RC0/T1OSO/
T1CKI
T1OSO
RC1/T1OSI/
CCP2/FLTA
RC2/CCP1/FLTB
RC3/T0CKI/
T5CKI/INT0
RC4/INT1/SDI/
SDA
ST
DIG
ST
T1OSI
ANA
CCP2
DIG
CCP2 compare and PWM output; takes priority over port data.
ST
FLTA
ST
RC2
DIG
ST
CCP1
DIG
ST
FLTB
ST
RC3
DIG
Note 1:
ST
T0CKI(1)
ST
T5CKI(1)
ST
INT0
ST
External Interrupt 0.
RC4
DIG
ST
INT1
ST
External Interrupt 1.
SDI(1)
ST
(1)
DIG
I2C data output (SSP module); takes priority over port data.
I C
DIG
ST
RC5
INT2
ST
SCK(1)
DIG
SPI clock output (SSP module); takes priority over port data.
ST
DIG
I2C clock output (SSP module); takes priority over port data.
I2C
I2C clock input (SSP module); input type depends on module setting.
DIG
ST
TX
DIG
CK
DIG
ST
ST
RC6
SS
Legend:
RC1
SCL(1)
RC6/TX/CK/SS
T1CKI
SDA
RC5/INT2/SCK/
SCL
Description
DIG = Digital level output; TTL = TTL input buffer; ST = Schmitt Trigger input buffer; ANA = Analog level input/output;
x = Dont care (TRIS bit does not affect port direction or is overridden for this option).
RD0 is the alternate pin for T0CKI/T5CKI; RD2 is the alternate pin for SDI/SDA; RD3 is the alternate pin for SCK/SCL;
RD1 is the alternate pin for SDO.
DS39616D-page 120
PIC18F2331/2431/4331/4431
TABLE 11-5:
Pin
Function
TRIS
Setting
I/O
I/O
Type
RC7/RX/DT/SDO
RC7
DIG
ST
RX
ST
DT
DIG
ST
DIG
SDO(1)
Legend:
Note 1:
Description
LATC<7> data output.
DIG = Digital level output; TTL = TTL input buffer; ST = Schmitt Trigger input buffer; ANA = Analog level input/output;
x = Dont care (TRIS bit does not affect port direction or is overridden for this option).
RD0 is the alternate pin for T0CKI/T5CKI; RD2 is the alternate pin for SDI/SDA; RD3 is the alternate pin for SCK/SCL;
RD1 is the alternate pin for SDO.
TABLE 11-6:
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reset Values
on Page:
PORTC
RC7
RC6
RC5
RC4
RC3
RC2
RC1
RC0
57
LATC
57
TRISC
57
INTCON
GIE/GIEH PEIE/GIEL
INTCON2
RBPU
INTEDG0
INTCON3
INT2IP
INT1IP
TMR0IE
INT0IE
INTEDG1 INTEDG2
INT2IE
RBIE
TMR0IF
TMR0IP
INT1IE
INT0IF
RBIF
54
RBIP
54
INT2IF
INT1IF
54
DS39616D-page 121
PIC18F2331/2431/4331/4431
11.4
Note:
DS39616D-page 122
EXAMPLE 11-4:
CLRF
PORTD
CLRF
LATD
MOVLW
0xCF
MOVWF
TRISD
INITIALIZING PORTD
;
;
;
;
;
;
;
;
;
;
;
;
Initialize PORTD by
clearing output
data latches
Alternate method
to clear output
data latches
Value used to
initialize data
direction
Set RD<3:0> as inputs
RD<5:4> as outputs
RD<7:6> as inputs
PIC18F2331/2431/4331/4431
TABLE 11-7:
Pin
TRIS
Setting
I/O
I/O
Type
RD0
DIG
ST
T0CKI(1)
ST
T5CKI(1)
ST
RD1
DIG
ST
SDO(1)
DIG
RD2
DIG
RD0/T0CKI/
T5CKI
RD1/SDO
RD2/SDI/SDA
ST
SDI(1)
ST
SDA(1)
DIG
I2C data output (SSP module); takes priority over port data.
I C
DIG
ST
DIG
SPI clock output (SSP module); takes priority over port data.
ST
DIG
I2C clock output (SSP module); takes priority over port data.
I C
I2C clock input (SSP module); input type depends on module setting.
RD4
DIG
ST
FLTA(2)
ST
RD5
DIG
RD3/SCK/SCL
RD3
SCK(1)
SCL
RD4/FLTA
RD5/PWM4
(1)
ST
PWM4(3)
DIG
RD6
DIG
ST
PWM6
DIG
RD7
DIG
ST
DIG
RD6/PWM6
RD7/PWM7
PWM7
Legend:
Note 1:
2:
3:
DIG = Digital level output; TTL = TTL input buffer; ST = Schmitt Trigger input buffer;
x = Dont care (TRIS bit does not affect port direction or is overridden for this option).
RC3 is the alternate pin for T0CKI/T5CKI; RC4 is the alternate pin for SDI/SDA; RC5 is the alternate pin for SCK/SCL;
RC7 is the alternate pin for SDO.
RC1 is the alternate pin for FLTA.
RB5 is the alternate pin for PWM4.
TABLE 11-8:
Name
PORTD
Description
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reset Values
on Page:
RD7
RD6
RD5
RD4
RD3
RD2
RD1
RD0
57
LATD
57
TRISD
57
DS39616D-page 123
PIC18F2331/2431/4331/4431
11.5
Note:
REGISTER 11-1:
EXAMPLE 11-5:
CLRF
PORTE
CLRF
LATE
MOVLW
MOVWF
BCF
MOVLW
0x3F
ANSEL0
ANSEL1, 0
0x03
MOVWF
TRISE
11.5.1
INITIALIZING PORTE
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
Initialize PORTE by
clearing output
data latches
Alternate method
to clear output
data latches
Configure A/D
for digital inputs
Value used to
initialize data
direction
Set RE<0> as input
RE<1> as output
RE<2> as input
TRISE REGISTER
U-0
U-0
U-0
U-0
U-0
R/W-1
R/W-1
R/W-1
TRISE2
TRISE1
TRISE0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
-n = Value at POR
1 = Bit is set
0 = Bit is cleared
bit 7-3
Unimplemented: Read as 0
bit 2
bit 1
bit 0
DS39616D-page 124
x = Bit is unknown
PIC18F2331/2431/4331/4431
TABLE 11-9:
Pin
Function
TRIS
Setting
I/O
I/O
Type
RE0
DIG
ST
AN6
ANA
RE1
DIG
ST
AN7
ANA
RE2
DIG
ST
RE0/AN6
RE1/AN7
RE2/AN8
MCLR/VPP/RE3(1)
Legend:
Note 1:
2:
AN8
ANA
MCLR
ST
VPP
ANA
RE3
(2)
ST
Description
LATE<0> data output; not affected by analog input.
PORTE<0> data input; disabled when analog input is enabled.
DIG = Digital level output; TTL = TTL input buffer; ST = Schmitt Trigger input buffer; ANA = Analog level input/output;
x = Dont care (TRIS bit does not affect port direction or is overridden for this option).
All PORTE pins are only implemented on 40/44-pin devices.
RE3 does not have a corresponding TRIS bit to control data direction.
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reset Values
on Page:
PORTE
RE3(1)
RE2
RE1
RE0
57
LATE
57
TRISE
57
ANS4
ANS3
ANS2
ANS1
ANS0
56
ANS8(2)
56
Name
ANSEL0
ANSEL1
DS39616D-page 125
PIC18F2331/2431/4331/4431
NOTES:
DS39616D-page 126
PIC18F2331/2431/4331/4431
12.0
TIMER0 MODULE
REGISTER 12-1:
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
TMR0ON
T016BIT
T0CS
T0SE
PSA
T0PS2
T0PS1
T0PS0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
-n = Value at POR
1 = Bit is set
0 = Bit is cleared
x = Bit is unknown
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2-0
DS39616D-page 127
PIC18F2331/2431/4331/4431
FIGURE 12-1:
0
1
1
Programmable
Prescaler
T0CKI pin
T0SE
T0CS
Sync with
Internal
Clocks
(2 TCY Delay)
T0PS<2:0>
PSA
Note:
Set
TMR0IF
on Overflow
TMR0L
Upon Reset, Timer0 is enabled in 8-bit mode with clock input from T0CKI max. prescale.
FIGURE 12-2:
FOSC/4
T0CKI pin
T0SE
T0CS
Programmable
Prescaler
Sync with
Internal
Clocks
TMR0
High Byte
TMR0L
Set
TMR0IF
on Overflow
(2 TCY Delay)
Read TMR0L
T0PS<2:0>
Write TMR0L
PSA
TMR0H
8
8
Internal Data Bus
Note:
Upon Reset, Timer0 is enabled in 8-bit mode with clock input from T0CKI max. prescale.
DS39616D-page 128
PIC18F2331/2431/4331/4431
12.1
12.2.1
Timer0 Operation
12.2
Prescaler
TABLE 12-1:
Name
The prescaler assignment is fully under software control (i.e., it can be changed on-the-fly during program
execution).
12.3
Timer0 Interrupt
12.4
Bit 6
TMR0L
TMR0H
INTCON
SWITCHING PRESCALER
ASSIGNMENT
GIE/GIEH
PEIE/GIEL
T0CON
TMR0ON
T016BIT
TRISA
TRISA7(1)
TRISA6(1)
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reset Values
on Page:
55
55
TMR0IE
INT0IE
RBIE
TMR0IF
INT0IF
RBIF
54
T0CS
T0SE
PSA
T0PS2
T0PS1
T0PS0
55
57
DS39616D-page 129
PIC18F2331/2431/4331/4431
NOTES:
DS39616D-page 130
PIC18F2331/2431/4331/4431
13.0
TIMER1 MODULE
REGISTER 13-1:
R/W-0
RD16
R/W-0
T1RUN
T1CKPS1
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
T1CKPS0
T1OSCEN
T1SYNC
TMR1CS
TMR1ON
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
-n = Value at POR
1 = Bit is set
0 = Bit is cleared
x = Bit is unknown
bit 7
bit 6
bit 5-4
bit 3
bit 2
bit 1
bit 0
DS39616D-page 131
PIC18F2331/2431/4331/4431
13.1
When TMR1CS = 0, Timer1 increments every instruction cycle. When TMR1CS = 1, Timer1 increments on
every rising edge of the external clock input or the
Timer1 oscillator, if enabled.
Timer1 Operation
FIGURE 13-1:
T1OSO/T1CKI
1
FOSC/4
Internal
Clock
T1OSI
Synchronize
Prescaler
1, 2, 4, 8
Detect
0
2
T1OSCEN(1)
Sleep Input
TMR1CS
Timer1
On/Off
T1CKPS<1:0>
T1SYNC
TMR1ON
Clear TMR1
(CCP Special Event Trigger)
Set
TMR1IF
on Overflow
TMR1
High Byte
TMR1L
Note 1: When enable bit, T1OSCEN, is cleared, the inverter and feedback resistor are turned off to eliminate power drain.
FIGURE 13-2:
Timer1 Oscillator
1
T1OSO/T1CKI
1
FOSC/4
Internal
Clock
T1OSI
Synchronize
Prescaler
1, 2, 4, 8
Detect
0
2
T1OSCEN(1)
Sleep Input
TMR1CS
Timer1
On/Off
T1CKPS<1:0>
T1SYNC
TMR1ON
Clear TMR1
(CCP Special Event Trigger)
TMR1
High Byte
TMR1L
Set
TMR1IF
on Overflow
Read TMR1L
Write TMR1L
8
TMR1H
8
8
Internal Data Bus
Note 1: When enable bit, T1OSCEN, is cleared, the inverter and feedback resistor are turned off to eliminate power drain.
DS39616D-page 132
PIC18F2331/2431/4331/4431
13.2
Timer1 Oscillator
13.3
FIGURE 13-3:
EXTERNAL COMPONENTS
FOR THE TIMER1 LP
OSCILLATOR
C1
27 pF
T1OSI
T1OSO
PIC18FXXXX
XTAL
32.768 kHz
C2
27 pF
See the notes with Table 13-1 for additional
information about capacitor selection.
Note:
TABLE 13-1:
Osc Type
LP
C1
27
pF(1)
C2
27 pF(1)
DS39616D-page 133
PIC18F2331/2431/4331/4431
13.4
Timer1 Interrupt
13.5
Timer1 must be configured for either Timer or Synchronized Counter mode to take advantage of this feature.
If Timer1 is running in Asynchronous Counter mode,
this Reset operation may not work.
In the event that a write to Timer1 coincides with a
Special Event Trigger from CCP1, the write will take
precedence.
In this mode of operation, the CCPR1H:CCPR1L register pair effectively becomes the Period register for
Timer1.
13.6
DS39616D-page 134
13.7
PIC18F2331/2431/4331/4431
EXAMPLE 13-1:
RTCinit
MOVLW
MOVWF
CLRF
MOVLW
MOVWF
CLRF
CLRF
MOVLW
MOVWF
BSF
RETURN
0x80
TMR1H
TMR1L
b'00001111'
T1CON
secs
mins
.12
hours
PIE1, TMR1IE
BSF
BCF
INCF
MOVLW
CPFSGT
RETURN
CLRF
INCF
MOVLW
CPFSGT
RETURN
CLRF
INCF
MOVLW
CPFSGT
RETURN
MOVLW
MOVWF
RETURN
TMR1H, 7
PIR1, TMR1IF
secs, F
.59
secs
RTCisr
TABLE 13-2:
Name
INTCON
secs
mins, F
.59
mins
mins
hours, F
.23
hours
;
;
;
;
;
;
;
;
No, done
Clear seconds
Increment minutes
60 minutes elapsed?
;
;
;
;
No, done
clear minutes
Increment hours
24 hours elapsed?
; No, done
; Reset hours to 1
.01
hours
; Done
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reset Values
on Page:
INT0IE
RBIE
TMR0IF
INT0IF
RBIF
54
PIR1
ADIF
RCIF
TXIF
SSPIF
CCP1IF
TMR2IF
TMR1IF
57
PIE1
ADIE
RCIE
TXIE
SSPIE
CCP1IE
TMR2IE
TMR1IE
57
ADIP
RCIP
TXIP
SSPIP
CCP1IP
TMR2IP
TMR1IP
57
IPR1
TMR1L
55
TMR1H
55
T1CON
RD16
T1RUN
55
Legend: = unimplemented, read as 0. Shaded cells are not used by the Timer1 module.
DS39616D-page 135
PIC18F2331/2431/4331/4431
14.0
TIMER2 MODULE
14.1
Timer2 Operation
REGISTER 14-1:
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
TOUTPS3
TOUTPS2
TOUTPS1
TOUTPS0
TMR2ON
T2CKPS1
T2CKPS0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
-n = Value at POR
1 = Bit is set
0 = Bit is cleared
bit 7
Unimplemented: Read as 0
bit 6-3
bit 2
bit 1-0
DS39616D-page 136
x = Bit is unknown
PIC18F2331/2431/4331/4431
14.2
Timer2 Interrupt
14.3
Output of TMR2
FIGURE 14-1:
T2OUTPS<3:0>
1:1 to 1:16
Postscaler
Set TMR2IF
T2CKPS<1:0>
TMR2/PR2
Match
Reset
FOSC/4
TMR2
TMR2 Output
(to PWM or SSP)
Comparator
PR2
8
TABLE 14-1:
Name
INTCON
Bit 7
Bit 6
GIE/GIEH PEIE/GIEL
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reset Values
on Page:
TMR0IE
INT0IE
RBIE
TMR0IF
INT0IF
RBIF
54
PIR1
ADIF
RCIF
TXIF
SSPIF
CCP1IF
TMR2IF
TMR1IF
57
PIE1
ADIE
RCIE
TXIE
SSPIE
CCP1IE
TMR2IE
TMR1IE
57
ADIP
RCIP
TXIP
SSPIP
CCP1IP
TMR2IP
TMR1IP
57
IPR1
TMR2
T2CON
PR2
Timer2 Register
55
55
55
Legend: = unimplemented, read as 0. Shaded cells are not used by the Timer2 module.
DS39616D-page 137
PIC18F2331/2431/4331/4431
NOTES:
DS39616D-page 138
PIC18F2331/2431/4331/4431
15.0
TIMER5 MODULE
REGISTER 15-1:
R/W-0
T5SEN
Timer5 is a general purpose timer/counter that incorporates additional features for use with the Motion
Feedback Module (see Section 17.0 Motion Feedback Module). It may also be used as a general
purpose timer or a Special Event Trigger delay timer.
When used as a general purpose timer, it can be
configured to generate a delayed Special Event Trigger
(e.g., an ADC Special Event Trigger) using a
preprogrammed period delay.
Timer5 is controlled through the Timer5 Control register
(T5CON), shown in Register 15-1. The timer can be
enabled or disabled by setting or clearing the control bit
TMR5ON (T5CON<0>).
A block diagram of Timer5 is shown in Figure 15-1.
R/W-0
R/W-0
(1)
T5MOD
RESEN
R/W-0
T5PS1
R/W-0
R/W-0
R/W-0
R/W-0
T5PS0
T5SYNC(2)
TMR5CS
TMR5ON
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
-n = Value at POR
1 = Bit is set
0 = Bit is cleared
bit 7
bit 6
bit 5
bit 4-3
bit 2
bit 1
bit 0
Note 1:
2:
x = Bit is unknown
DS39616D-page 139
PIC18F2331/2431/4331/4431
FIGURE 15-1:
T5CKI
1
FOSC/4
Internal
Clock
Synchronize
Detect
Prescaler
1, 2, 4, 8
0
2
Sleep Input
Timer5
On/Off
TMR5CS
T5PS<1:0>
T5SYNC
TMR5ON
8
TMR5H
8
Write TMR5L
Read TMR5L
Special Event
Trigger Input
from IC1
Timer5 Reset
(external)
TMR5
1
TMR5L
Timer5 Reset
16
0
Reset
Logic
Comparator
16
PR5
8
PR5L
Set TMR5IF
Special Event
Trigger Output
15.1
Special
Event
Logic
Timer5 Operation
TMR5
High Byte
PR5H
The Timer5 may be used as a general purpose timer and as the time base resource to
the Motion Feedback Module (Input
Capture or Quadrature Encoder Interface).
DS39616D-page 140
PIC18F2331/2431/4331/4431
In Synchronous Counter mode configuration, the timer
is clocked by the external clock (T5CKI) with the
optional prescaler. The external T5CKI is selected by
setting the TMR5CS bit (TMR5CS = 1); the internal
clock is selected by clearing TMR5CS. The external
clock is synchronized to the internal clock by clearing
the T5SYNC bit. The input on T5CKI is sampled on
every Q2 and Q4 of the internal clock. The low to rise
transition is decoded on three adjacent samples and
the Timer5 is incremented on the next Q1. The T5CKI
minimum pulse-width high and low time must be
greater than TCY/2.
In Asynchronous Counter mode configuration, Timer5
is clocked by the external clock (T5CKI) with the
optional prescaler. In this mode, T5CKI is not synchronized to the internal clock. By setting TMR5CS, the
external input clock (T5CKI) can be used as the counter sampling clock. When T5SYNC is set, the external
clock is not synchronized to the internal device clock.
The timer count is not reset automatically when the
module is disabled. The user may write the Counter
register to initialize the counter.
Note:
15.1.1
15.2
15.2.1
16-BIT READ-MODIFY-WRITE
15.3
Timer5 Prescaler
DS39616D-page 141
PIC18F2331/2431/4331/4431
15.4
Noise Filter
15.5
Timer5 Interrupt
15.7.1
15.7.2
15.7.3
15.6
15.7
DS39616D-page 142
15.8
TMR5ON
T5SEN
TMR5CS
T5SYNC
15.8.1
PIC18F2331/2431/4331/4431
TABLE 15-1:
Name
INTCON
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reset Values
on Page:
INT0IE
RBIE
TMR0IF
INT0IF
RBIF
54
IPR3
PTIP
IC3DRIP IC2QEIP
IC1IP
TMR5IP
56
PIE3
PTIE
IC3DRIE IC2QEIE
IC1IE
TMR5IE
56
PTIF
IC3DRIF IC2QEIF
IC1IF
TMR5IF
56
PIR3
TMR5H
57
TMR5L
57
PR5H
57
PR5L
57
T5SEN
RESEN
T5MOD
T5PS1
CAP1CON
CAP1REN
DFLTCON
FLT4EN
FLT3EN
FLT2EN
T5CON
T5PS0
56
CAP1M0
59
FLT1EN
FLTCK0
59
FLTCK2
FLTCK1
Legend: = unimplemented. Shaded cells are not used by the Timer5 module.
DS39616D-page 143
PIC18F2331/2431/4331/4431
NOTES:
DS39616D-page 144
PIC18F2331/2431/4331/4431
16.0
CAPTURE/COMPARE/PWM
(CCP) MODULES
TABLE 16-1:
16.1
CCP1 Module
16.2
CCP Mode
Timer Resources
Capture
Compare
PWM
Timer1
Timer1
Timer2
CCP2 Module
Capture/Compare/PWM Register 2 (CCPR2) is comprised of two 8-bit registers: CCPR2L (low byte) and
CCPR2H (high byte). The CCP2CON register controls
the operation of CCP2. All are readable and writable.
REGISTER 16-1:
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
DCxB1
DCxB0
CCPxM3
CCPxM2
CCPxM1
CCPxM0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
-n = Value at POR
1 = Bit is set
0 = Bit is cleared
x = Bit is unknown
bit 7-6
Unimplemented: Read as 0
bit 5-4
bit 3-0
DS39616D-page 145
PIC18F2331/2431/4331/4431
16.3
16.3.3
Capture Mode
16.3.2
Timer1 must be running in Timer mode or Synchronized Counter mode to be used with the capture
feature. In Asynchronous Counter mode, the capture
operation may not work.
FIGURE 16-1:
16.3.4
16.3.1
SOFTWARE INTERRUPT
CCP PRESCALER
EXAMPLE 16-1:
CHANGING BETWEEN
CAPTURE PRESCALERS
CLRF
MOVLW
CCP1CON
NEW_CAPT_PS
MOVWF
CCP1CON
;
;
;
;
;
;
Prescaler
1, 4, 16
CCPR1L
TMR1
Enable
CCP1 Pin
and
Edge Detect
TMR1H
TMR1L
CCPR2H
CCPR2L
CCP1CON<3:0>
Qs
Set CCP2IF Flag bit
Prescaler
1, 4, 16
TMR1
Enable
CCP2 Pin
and
Edge Detect
Qs
DS39616D-page 146
TMR1H
TMR1L
CCP2CON<3:0>
PIC18F2331/2431/4331/4431
16.4
16.4.2
Compare Mode
Timer1 must be running in Timer mode or Synchronized Counter mode if the CCP module is using the
compare feature. In Asynchronous Counter mode, the
compare operation may not work.
16.4.3
is driven high
is driven low
toggles output (high-to-low or low-to-high)
remains unchanged (interrupt only)
16.4.1
16.4.4
FIGURE 16-2:
S
R
TRISC<2>
Output Enable
Output
Logic
Match
Comparator
CCP1CON<3:0>
Mode Select
TMR1H
TMR1L
Q
RC1/CCP2 Pin
TRISC<1>
Output Enable
S
R
Output
Logic
CCP2CON<3:0>
Mode Select
Match
Comparator
CCPR2H CCPR2L
DS39616D-page 147
PIC18F2331/2431/4331/4431
TABLE 16-2:
Name
INTCON
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reset Values
on Page:
INT0IE
RBIE
TMR0IF
INT0IF
RBIF
54
PIR1
ADIF
RCIF
TXIF
SSPIF
CCP1IF
TMR2IF
TMR1IF
57
PIE1
ADIE
RCIE
TXIE
SSPIE
CCP1IE
TMR2IE
TMR1IE
57
ADIP
RCIP
TXIP
SSPIP
CCP1IP
TMR2IP
TMR1IP
57
IPR1
TRISC
57
TMR1L
55
TMR1H
55
T1CON
RD16
T1RUN
55
CCPR1L
56
CCPR1H
56
CCP1CON
DC1B1
DC1B0
CCPR2L
CCPR2H
DC2B1
PIR2
OSCFIF
PIE2
OSCFIE
IPR2
OSCFIP
CCP2CON
CCP1M3
56
56
56
DC2B0
CCP2M3
56
EEIF
LVDIF
CCP2IF
57
EEIE
LVDIE
CCP2IE
57
EEIP
LVDIP
CCP2IP
57
Legend: = unimplemented, read as 0. Shaded cells are not used by Capture, Compare and Timer1.
DS39616D-page 148
PIC18F2331/2431/4331/4431
16.5
16.5.1
PWM Mode
Note:
FIGURE 16-3:
EQUATION 16-1:
PWM Period = [(PR2) + 1] 4 TOSC
(TMR2 Prescale Value)
PWM frequency is defined as 1/[PWM period]. When
TMR2 is equal to PR2, the following three events occur
on the next increment cycle:
TMR2 is cleared
The CCP1 pin is set (if PWM duty cycle = 0%, the
CCP1 pin will not be set)
The PWM duty cycle is copied from CCPR1L into
CCPR1H
Note:
CCP1CON<5:4>
16.5.2
CCPR1H (Slave)
Comparator
Q
RC2/CCP1
TMR2
(Note 1)
S
TRISC<2>
Comparator
Clear Timer,
CCP1 pin and
latch D.C.
PR2
Note 1:
FIGURE 16-4:
PWM PERIOD
EQUATION 16-2:
PWM Duty Cycle = (CCPR1L:CCP1CON<5:4>)
TOSC (TMR2 Prescale Value)
CCPR1L and CCP1CON<5:4> can be written to at any
time, but the duty cycle value is not copied into
CCPR1H until a match between PR2 and TMR2 occurs
(i.e., the period is complete). In PWM mode, CCPR1H
is a read-only register.
PWM OUTPUT
Period
Duty Cycle
TMR2 = PR2
TMR2 = Duty Cycle
TMR2 = PR2
DS39616D-page 149
PIC18F2331/2431/4331/4431
The CCPR1H register and a 2-bit internal latch are
used to double buffer the PWM duty cycle. This double
buffering is essential for glitchless PWM operation.
When the CCPR1H and 2-bit latch match TMR2,
concatenated with an internal 2-bit Q clock or two bits
of the TMR2 prescaler, the CCP1 pin is cleared. The
maximum PWM resolution (bits) for a given PWM
frequency is given by the following equation:
16.5.3
EQUATION 16-3:
4.
log FOSC
FPWM
PWM Resolution (max) =
bits
log(2)
Note:
1.
2.
3.
5.
PWM Frequency
2.44 kHz
9.77 kHz
39.06 kHz
156.25 kHz
312.50 kHz
416.67 kHz
16
FFh
FFh
FFh
3Fh
1Fh
17h
10
10
10
6.58
TABLE 16-4:
INTCON
TABLE 16-3:
Name
Bit 6
GIE/GIEH PEIE/GIEL
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reset Values
on Page:
TMR0IE
INT0IE
RBIE
TMR0IF
INT0IF
RBIF
54
PIR1
ADIF
RCIF
TXIF
SSPIF
CCP1IF
TMR2IF
TMR1IF
57
PIE1
ADIE
RCIE
TXIE
SSPIE
CCP1IE
TMR2IE
TMR1IE
57
ADIP
RCIP
TXIP
SSPIP
CCP1IP
TMR2IP
TMR1IP
57
IPR1
TRISC
57
TMR2
Timer2 Register
55
PR2
55
T2CON
CCPR1L
CCPR1H
CCP1CON
DC1B1
DC1B0
55
56
56
56
CCPR2L
56
CCPR2H
56
CCP2CON
DC2B1
DC2B0
56
Legend: x = unknown, u = unchanged, - = unimplemented, read as 0. Shaded cells are not used by PWM and
Timer2.
DS39616D-page 150
PIC18F2331/2431/4331/4431
17.0
TABLE 17-1:
Submodule
Mode(s)
Features
IC (3x)
Synchronous
Input Capture
QEI
QEI
Velocity
Measurement
Timer
TMR5
Function
3x Input Capture (edge
capture, pulse width, period
measurement, capture on
change)
Special Event Triggers the
A/D Conversion on the CAP1
Input
DS39616D-page 151
PIC18F2331/2431/4331/4431
FIGURE 17-1:
TMR5IF
TMR5
Reset
Control
Timer Reset
Timer5
TMR5<15:0>
8
Filter
Data Bus<7:0>
TCY
T5CKI
Filter
Prescaler
IC3
Filter
CAP2/QEA
Prescaler
IC2
Filter
CAP1/INDX
Prescaler
TMR5<15:0>
CAP3/QEB
TCY
IC3IF
8
IC2IF
IC1
Clock
Divider
IC1IF
Special Event Trigger Reset
8
Postscaler
QEB
Velocity Event
Timer Reset
QEA
Direction
Position Counter
Clock
QEIF
QEI
Control
Logic
INDX
CHGIF
8
QEI Logic
CHGIF
IC3DRIF
IC3IF
QEI
Mode
Decoder
QEIF
IC2QEIF
IC2IF
DS39616D-page 152
PIC18F2331/2431/4331/4431
17.1
Input Capture
FIGURE 17-2:
CAP1 Pin
Noise
Filter
Prescaler
1, 4, 16
and
Mode
Select
CAP1BUF/VELR(1)
Clock
3
FLTCK<2:0>
4
CAP1M<3:0> Q Clocks
IC1IF
IC1_TR
1
MUX
0
Clock/
Reset/
Interrupt
Decode
Logic
Special
Event Trigger
Reset
Reset
Control
Timer5 Logic
CAP1BUF_clk
First Event
Reset
velcap(2) VELM
Timer
Reset
Control
Timer5 Reset
CAP1M<3:0>
CAPxREN
Q Clocks
Reset
TMR5
Note 1:
2:
DS39616D-page 153
PIC18F2331/2431/4331/4431
FIGURE 17-3:
CAPxBUF(1,2,3)
CAP2/3 Pin
Noise
Filter
Prescaler
1, 4, 16
and
Mode
Select
Capture
Clock
TMR5
Enable
3
FLTCK<2:0>
4
CAP1M<3:0>(1) Q Clocks
TMR5
ICxIF(1)
Capture Clock/
Reset/
Interrupt
Decode
Logic
Q Clocks
CAPxBUF_clk(1)
Reset
Timer
Reset
Control
TMR5 Reset
CAPxM<3:0>(1)
CAPxREN(2)
Note 1:
2:
3:
DS39616D-page 154
PIC18F2331/2431/4331/4431
The three input capture channels are controlled
through the Input Capture Control registers,
CAP1CON, CAP2CON and CAP3CON. Each channel
is configured independently with its dedicated register.
The implementation of the registers is identical except
for the Special Event Trigger (see Section 17.1.8
Special Event Trigger (CAP1 Only)). The typical
Capture Control register is shown in Register 17-1.
REGISTER 17-1:
Note:
U-0
R/W-0
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
CAPxREN
CAPxM3
CAPxM2
CAPxM1
CAPxM0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
-n = Value at POR
1 = Bit is set
0 = Bit is cleared
x = Bit is unknown
bit 7
Unimplemented: Read as 0
bit 6
bit 5-4
Unimplemented: Read as 0
bit 3-0
Note 1:
Special Event Trigger is only available on CAP1. For CAP2 and CAP3, this configuration is unused.
DS39616D-page 155
PIC18F2331/2431/4331/4431
When in Counter mode, the counter must be
configured as the synchronous counter only
(T5SYNC = 0). When configured in Asynchronous
mode, the IC module will not work properly.
Note 1: Input capture prescalers are reset
(cleared) when the input capture module
is disabled (CAPxM = 0000).
2: When the Input Capture mode is
changed, without first disabling the
module and entering the new Input Capture mode, a false interrupt (or Special
Event Trigger on IC1) may be generated.
The user should either: (1) disable the
input capture before entering another
mode, or (2) disable IC interrupts to avoid
false interrupts during IC mode changes.
17.1.1
Note:
FIGURE 17-4:
OSC
0012
TMR5(1)
0013
0014
0015
0000
0001
0002
0000
0001
0002
CAP1 Pin(2)
ABCD
CAP1BUF(3)
0016
0003
Note 5
TMR5 Reset(4)
Instruction
Execution
Note 1:
MOVWF CAP1CON
0002
TMR5 is a synchronous time base input to the input capture; prescaler = 1:1. It increments on the Q1 rising edge.
2:
IC1 is configured in Edge Capture mode (CAP1M<3:0> = 0010) with the time base reset upon edge capture
(CAP1REN = 1) and no noise filter.
3:
TMR5 value is latched by CAP1BUF on TCY. In the event that a write to TMR5 coincides with an input capture event,
the write will always take precedence. All Input Capture Buffers, CAP1BUF, CAP2BUF and CAP3BUF, are updated
with the incremented value of the time base on the next TCY clock edge when the capture event takes place (see
Note 4 when Reset occurs).
4:
TMR5 Reset is normally an asynchronous Reset signal to TMR5. When used with the input capture, it is active
immediately after the time base value is captured.
5:
TMR5 Reset pulse is disabled by clearing the CAP1REN bit (e.g., BCF CAP1CON, CAP1REN).
DS39616D-page 156
PIC18F2331/2431/4331/4431
17.1.2
17.1.3
PULSE-WIDTH MEASUREMENT
MODE
FIGURE 17-5:
0012
TMR5(1)
0013
0014
0015
0000
0001
0002
0000
0001
0002
CAP1 Pin(2)
CAP1BUF(3)
0015
0001
0002
TMR5 Reset(4,5)
Instruction
Execution(2)
Note 1:
MOVWF CAP1CON
TMR5 is a synchronous time base input to the input capture; prescaler = 1:1. It increments on every Q1 rising edge.
2:
IC1 is configured in Pulse-Width Measurement mode (CAP1M<3:0> = 0111, rising to falling pulse-width
measurement). No noise filter on CAP1 input is used. The MOVWF instruction loads CAP1CON when W = 0111.
3:
TMR5 value is latched by CAP1BUF on TCY rising edge. In the event that a write to TMR5 coincides with an input capture event, the write will always take precedence. All Input Capture Buffers, CAP1BUF, CAP2BUF and CAP3BUF, are
updated with the incremented value of the time base on the next TCY clock edge when the capture event takes place
(see Note 4 when Reset occurs).
4:
TMR5 Reset is normally an asynchronous Reset signal to TMR5. When used in Pulse-Width Measurement mode, it
is always present on the edge that first initiates the pulse-width measurement (i.e., when configured in the rising to
falling Pulse-Width Measurement mode); it is active on each rising edge detected. In the falling to rising Pulse-Width
Measurement mode, it is active on each falling edge detected.
5:
TMR5 Reset pulse is activated on the capture edge. The CAP1REN bit has no bearing in this mode.
DS39616D-page 157
PIC18F2331/2431/4331/4431
17.1.3.1
17.1.4
State 2
State 3
State 4
State 5
State 6
FIGURE 17-6:
CAP1
CAP2
CAP3
0FFFh
Time Base(1)
0000h
CAP1BUF(2)
CAP2BUF(2)
CAP3BUF(2)
Time Base Reset(1)
Note 1:
TMR5 can be selected as the time base for input capture. The time base can be optionally reset when the Capture
Reset Enable bit is set (CAPxREN = 1).
2:
Detailed CAPxBUF event timing (all modes reflect the same capture and Reset timing) is shown in Figure 17-4. There
are six commutation BLDC Hall effect sensor states shown. The other two remaining states (i.e., 000h and 111h) are
invalid in the normal operation. They remain to be decoded by the CPU firmware in BLDC motor application.
DS39616D-page 158
PIC18F2331/2431/4331/4431
17.1.5
17.1.6
2.
FIGURE 17-7:
TIMER5 RESET
Note:
17.1.7
IC INTERRUPTS
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
OSC
CAP1 Pin
IC1IF
TMR5 Reset
TMR5
XXXX
0000
0001
TMR5ON(1)
Note 1:
Timer5 is only reset and enabled (assuming TMR5ON = 0 and T5MOD = 1) when the Special Event Trigger Reset is
enabled for the Timer5 Reset input. The TMR5ON bit is asserted and Timer5 is reset on the Q1 rising edge following
the event capture. With the Special Event Trigger Reset disabled, Timer5 cannot be reset by the Special Event Trigger
Reset on the CAP1 input. In order for the Special Event Trigger Reset to work as the Reset trigger to Timer5, IC1 must
be configured in the Special Event Trigger mode (CAP1M<3:0> = 1110 or 1111).
DS39616D-page 159
PIC18F2331/2431/4331/4431
17.1.8
17.1.9
TABLE 17-2:
CAP1M<3:0>
Description
1110
1111
17.1.10
TABLE 17-3:
Timer
Reset Timer
on Capture
TMR5
optional(1)
TMR5
optional(1)
TMR5
always
TMR5
optional(1)
TMR5
optional(2)
TMR5
optional(1)
TMR5
optional(1)
TMR5
always
TMR5
optional(1)
TMR5
optional(1)
TMR5
optional(1)
TMR5
always
TMR5
optional(1)
Pin
CAPxM
0101
Period Measurement
0110-0111 Pulse-Width
Measurement
1000
Period Measurement
0110-0111 Pulse-Width
Measurement
1000
Period Measurement
0110-0111 Pulse-Width
Measurement
1000
Note 1:
2:
Description
DS39616D-page 160
PIC18F2331/2431/4331/4431
Quadrature Encoder Interface
FIGURE 17-8:
17.2
QEI Module
Direction Change
Timer Reset
Velocity Event
Set CHGIF
Reset Timer5
Velocity Capture
Postscaler
8
Set UP/DOWN
Filter
QEB
QEA
CAP3/QEB
Direction
Clock
CAP2BUF/POSCNT
8
Reset on Match
INDX
Comparator
Filter
Set IC2QEIF
CAP2/QEA
CAP3BUF/MAXCNT
Filter
QEI
Control
Logic
Position Counter
CAP1/INDX
8
DS39616D-page 161
PIC18F2331/2431/4331/4431
17.2.1
QEI CONFIGURATION
The QEI module shares its input pins with the Input
Capture (IC) module. The inputs are mutually
exclusive; only the IC module or the QEI module (but
not both) can be enabled at one time. Also, because
the IC and QEI are multiplexed to the same input pins,
the programmable noise filters can be dedicated to one
module only.
REGISTER 17-2:
R/W-0
VELM
Note:
R/W-0
QERR
(1)
R-0
UP/DOWN
R/W-0
QEIM2
R/W-0
(2,3)
QEIM1
(2,3)
R/W-0
QEIM0
(2,3)
R/W-0
R/W-0
PDEC1
PDEC0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
-n = Value at POR
1 = Bit is set
0 = Bit is cleared
x = Bit is unknown
bit 7
bit 6
bit 5
bit 4-2
bit 1-0
Note 1:
2:
3:
4:
DS39616D-page 162
PIC18F2331/2431/4331/4431
17.2.2
QEI MODES
17.2.3
TABLE 17-4:
QEI MODES
QEIM<2:0>
Mode/
Reset
000
001
010
Description
QEI disabled.(1)
011
Unused.
100
Unused.
101
110
111
Note 1:
17.2.2.1
Unused.
17.2.2.2
QEI OPERATION
17.2.3.1
In the first step, the active edges of QEA and QEB are
detected, and the phase relationship between them is
determined. The position counter is changed based on
the selected QEI mode.
In QEI x2 Update mode, the position counter
increments or decrements on every QEA edge based
on the phase relationship of the QEA and QEB signals.
In QEI x4 Update mode, the position counter
increments or decrements on every QEA and QEB
edge based on the phase relationship of the QEA and
QEB signals. For example, if QEA leads QEB, the
position counter is incremented by 1. If QEB lags
QEA, the position counter is decremented by 1.
17.2.3.2
Direction of Count
TABLE 17-5:
Current
Signal
Detected
DIRECTION OF ROTATION
Previous Signal
Detected
Rising
Falling
Pos.
Cntrl.(1)
x
x
DEC
QEA Falling
x
x
QEB Rising
x
Note 1:
DEC
INC
QEB Falling
INC
INC
x
DEC
INC
DEC
DS39616D-page 163
PIC18F2331/2431/4331/4431
17.2.3.3
The position counter will continue to increment or decrement until one of the following events takes place.
The type of event and the direction of rotation when it
happens determines if a register Reset or update
occurs.
1.
2.
17.2.4
QEI INTERRUPTS
17.2.5
EQUATION 17-1:
FPOS = 4D RPM
60
Note:
DS39616D-page 164
PIC18F2331/2431/4331/4431
FIGURE 17-9:
TCY
QEA Pin
TQEI = 16 TCY(1)
QEB Pin
QEA Input
TGD = 3 TCY
QEB Input
Note 1:
FIGURE 17-10:
Reverse
QEA
QEB
Count (+/-)
+1 +1 +1 +1 +1 +1 +1 +1 +1 +1 +1 +1
-1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
MAXCNT
1517
1516
1515
1514
1519
1518
1520
1522
1521
1523
1525
1524
1526
1527
0003
0002
0001
0000
0004
0003
0002
0000
0001
1525
1526
1527
1524
1521
1522
1523
1520
POSCNT(1)
MAXCNT=1527
Note 6
IC2QEIF
Note 2
Note 2
UP/DOWN
Q4(3)
Q4(3)
Position
Counter Load
Q1(5)
Q1(4)
IC3DRIF
Q1(5)
Note 1:
The POSCNT register is shown in QEI x4 Update mode (POSCNT increments on every rising and every falling edge
of QEA and QEB input signals). Asynchronous external QEA and QEB inputs are synchronized to the TCY clock by
the input sampling FF in the noise filter (see Figure 17-14).
2:
When POSCNT = MAXCNT, POSCNT is reset to 0 on the next QEA rising edge. POSCNT is set to MAXCNT when
POSCNT = 0 (when decrementing), which occurs on the next QEA falling edge.
3:
4:
Position counter is loaded with 0 (which is a rollover event in this case) on POSCNT = MAXCNT.
5:
6:
DS39616D-page 165
PIC18F2331/2431/4331/4431
FIGURE 17-11:
Reverse
Note 2
Note 2
QEA
QEB
Count (+/-)
-1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
+1 +1 +1 +1 +1 +1 +1 +1 +1 +1 +1 +1
MAXCNT
1515
1514
1517
1516
1519
1518
1520
1522
1521
1525
1524
1523
1527
1526
0001
0000
0002
0003
0004
0003
0000
0001
0002
1526
1527
1524
1525
1521
1522
1523
1520
POSCNT(1)
MAXCNT = 1527
INDX
Note 6
IC2QEIF
UP/DOWN
Q4(3)
Position
Counter Load
Q1(4)
Q4(3)
Q1(5)
Note 1:
POSCNT register is shown in QEI x4 Update mode (POSCNT increments on every rising and every falling edge of
QEA and QEB input signals).
2:
When an INDX Reset pulse is detected, POSCNT is reset to 0 on the next QEA or QEB edge. POSCNT is set to
MAXCNT when POSCNT = 0 (when decrementing), which occurs on the next QEA or QEB edge. a similar Reset
sequence occurs for the reverse direction, except that the INDX signal is recognized on its falling edge. The Reset
is generated on the next QEA or QEB edge.
3:
4:
The position counter is loaded with 0000h (i.e., Reset) on the next QEA or QEB edge when the INDX is high.
5:
The position counter is loaded with a MAXCNT value (e.g., 1527h) on the next QEA or QEB edge following the
INDX falling edge input signal detect).
6:
DS39616D-page 166
PIC18F2331/2431/4331/4431
17.2.6
17.2.6.1
VELOCITY MEASUREMENT
TABLE 17-6:
VELOCITY PULSES
QEIM<2:0>
001
010
101
110
FIGURE 17-12:
QEI
Control
Logic
TMR5 Reset
TMR5
Clock
TCY
16
CAP3/QEB
Noise Filters
Velocity Mode
Velocity Event
Velocity Capture
IC1
(VELR Register)
QEB
QEA
CAP2/QEA
Postscaler
INDX
Direction
Clock
Position
Counter
CAP1/INDX
DS39616D-page 167
PIC18F2331/2431/4331/4431
FIGURE 17-13:
Reverse
QEA
QEB
vel_out
velcap
VELR(2)
Old Value
1529
0003
0004
0001
0002
0008
0009
0000
0006
0007
0005
0003
0004
0001
0002
0000
1527
1528
1529
1530
1531
1532
1533
1534
1535
1536
1525
1526
1523
1524
1522
1520
1521
TMR5(2)
1537
cnt_reset(3)
Q1
Q1
Q1
IC1IF(4)
CAP1REN
Instr.
Execution BCF T5CON, VELM BCF PIE2, IC1IE
MOVWF QEICON(5)
Note 1:
Timing shown is for QEIM<2:0> = 101, 110 or 111 (x4 Update mode enabled) and the velocity postscaler divide ratio
is set to divide-by-4 (PDEC<1:0> = 01).
2:
The VELR register latches the TMR5 count on the velcap capture pulse. Timer5 must be set to the Synchronous Timer
or Counter mode. In this example, it is set to the Synchronous Timer mode, where the TMR5 prescaler divide ratio = 1
(i.e., Timer5 Clock = TCY).
3:
The TMR5 counter is reset on the next Q1 clock cycle following the velcap pulse. The TMR5 value is unaffected
when the Velocity Measurement mode is first enabled (VELM = 0). The velocity postscaler values must be
reconfigured to their previous settings when re-entering Velocity Measurement mode. While making speed
measurements of very slow rotational speeds (e.g., servo-controller applications), the Velocity Measurement mode
may not provide sufficient precision. The Pulse-Width Measurement mode may have to be used to provide the
additional precision. In this case, the input pulse is measured on the CAP1 input pin.
4:
IC1IF interrupt is enabled by setting IC1IE as follows: BSF PIE2, IC1IE. Assume IC1E bit is placed in the PIE2
(Peripheral Interrupt Enable 2) register in the target device. The actual IC1IF bit is written on the Q2 rising edge.
5:
The post decimation value is changed from PDEC = 01 (decimate by 4) to PDEC = 00 (decimate by 1).
17.2.6.2
Velocity Postscaler
17.2.6.3
DS39616D-page 168
PIC18F2331/2431/4331/4431
17.3
Noise Filters
REGISTER 17-3:
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
FLT4EN
FLT3EN(1)
FLT2EN(1)
FLT1EN(1)
FLTCK2
FLTCK1
FLTCK0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
-n = Value at POR
1 = Bit is set
0 = Bit is cleared
bit 7
Unimplemented: Read as 0
bit 6
bit 5
bit 4
bit 3
bit 2-0
Note 1:
Note:
x = Bit is unknown
The noise filter output enables are functional in both QEI and IC Operating modes.
The noise filter is intended for random high-frequency filtering and not continuous high-frequency filtering.
DS39616D-page 169
PIC18F2331/2431/4331/4431
FIGURE 17-14:
TCY
Noise Glitch(3)
Noise Glitch(3)
Pin(1)
CAP1/INDX
(input to filter)
CAP1/INDX Input(2)
(output from filter) TGD = 3 TCY
Note 1:
17.4
Only the CAP1/INDX pin input is shown for simplicity. Similar event timing occurs on the CAP2/QEA and
CAP3/QEB pins.
2:
3:
TABLE 17-7:
Interrupt
Flag
IC1IF
17.5
17.5.1
Since the input capture can operate only when its time
base is configured in a Synchronous mode, the input
capture will not capture any events. This is because the
devices internal clock has been stopped and any internal timers in Synchronous modes will not increment.
The prescaler will continue to count the events (not
synchronized).
When the specified capture event occurs, the CAPx
interrupt will be set. The Capture Buffer register will be
updated upon wake-up from sleep to the current TMR5
value. If the CAPx interrupt is enabled, the device will
wake-up from Sleep. This effectively enables all input
capture channels to be used as the external interrupts.
17.5.2
QEI Mode
Position Measurement
Update
Direction Change
DS39616D-page 170
PIC18F2331/2431/4331/4431
TABLE 17-8:
Name
INTCON
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reset Values
on Page:
TMR0IE
INT0IE
RBIE
TMR0IF
INT0IF
RBIF
54
Bit 6
GIE/GIEH PEIE/GIEL
IPR3
PTIP
IC3DRIP IC2QEIP
IC1IP
TMR5IP
56
PIE3
PTIE
IC3DRIE IC2QEIE
IC1IE
TMR5IE
56
PTIF
IC3DRIF IC2QEIF
IC1IF
TMR5IF
56
PIR3
TMR5H
57
TMR5L
57
PR5H
57
PR5L
57
T5CON
T5SEN
RESEN
T5MOD
T5PS1
T5PS0
57
CAP1BUFH/
VELRH
58
CAP1BUFL/
VELRL
58
CAP2BUFH/
POSCNTH
58
CAP2BUFL/
POSCNTL
58
CAP3BUFH/
MAXCNTH
Capture 3 Register High Byte/QEI Max. Count Limit Register High Byte(1)
58
CAP3BUFL/
MAXCNTL
Capture 3 Register Low Byte/QEI Max. Count Limit Register Low Byte(1)
58
CAP1CON
CAP1REN
59
CAP2CON
CAP2REN
59
CAP3CON
CAP3REN
59
DFLTCON
FLT4EN
FLT3EN
VELM
QERR
QEICON
FLT2EN FLT1EN
UP/DOWN QEIM2
QEIM1
FLTCK2
FLTCK1
FLTCK0
59
QEIM0
PDEC1
PDEC0
56
Legend: = unimplemented. Shaded cells are not used by the Motion Feedback Module.
Note 1: Register name and function determined by which submodule is selected (IC/QEI, respectively). See
Section 17.1.10 Other Operating Modes for more information.
DS39616D-page 171
PIC18F2331/2431/4331/4431
NOTES:
DS39616D-page 172
PIC18F2331/2431/4331/4431
18.0
DS39616D-page 173
PIC18F2331/2431/4331/4431
FIGURE 18-1:
PWMCON0
PWM Enable and Mode
PWMCON1
8
DTCON
Dead-Time Control
FLTCONFIG
OVDCON<D/S>
PDC3 Buffer
PDC3
Comparator
PWM
Generator 2
PTMR
Channel 3
Dead-Time Generator
and Override Logic(2)
PWM7(2)
Channel 2
Dead-Time Generator
and Override Logic
PWM5
Comparator
PWM
Generator 1
PTPER
PWM
Generator 0
PTPER Buffer
Channel 1
Dead-Time Generator
and Override Logic
PWM6(2)
Output
Driver
Block
Channel 0
Dead-Time Generator
and Override Logic
PWM4
PWM3
PWM2
PWM1
PWM0
FLTA
PTCON
FLTB(2)
Comparator
SEVTDIR
SEVTCMP
Note 1:
2:
Special Event
Postscaler
PTDIR
Only PWM Generator 3 is shown in detail. The other generators are identical; their details are omitted for clarity.
PWM Generator 3 and its logic, PWM Channels 6 and 7, and FLTB and its associated logic are not implemented on
PIC18F2331/2431 devices.
DS39616D-page 174
PIC18F2331/2431/4331/4431
FIGURE 18-2:
Dead-Band
Generator
PWM1
LPOL
Fault B Pin
Note:
In Complementary mode, the even channel cannot be forced active by a Fault or override event when the odd channel is active.
The even channel is always the complement of the odd channel and is inactive, with dead time inserted, before the odd channel
is driven to its active state.
FIGURE 18-3:
HPOL
PWM0
LPOL
DS39616D-page 175
PIC18F2331/2431/4331/4431
18.1
Control Registers
18.2
Module Functionality
18.3
DS39616D-page 176
PIC18F2331/2431/4331/4431
FIGURE 18-4:
PTMR Clock
Timer Reset
Up/Down
Comparator
Zero Match
Period Match
Comparator
PTMOD1
Timer
Direction
Control
PTDIR
Duty Cycle Load
PTPER
Period Load
PTPER Buffer
Update Disable (UDIS)
FOSC/4
Prescaler
1:1, 1:4, 1:16, 1:64
Zero Match
Zero Match
Period Match
PTMOD1
PTMOD0
Clock
Control
PTMR Clock
PTEN
Postscaler
1:1-1:16
Interrupt
Control
PTIF
Period Match
PTMOD1
PTMOD0
Free-Running mode
Single-Shot mode
Continuous Up/Down Count mode
Continuous Up/Down Count mode with interrupts
for double updates
DS39616D-page 177
PIC18F2331/2431/4331/4431
REGISTER 18-1:
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
PTOPS3
PTOPS2
PTOPS1
PTOPS0
PTCKPS1
PTCKPS0
PTMOD1
PTMOD0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
-n = Value at POR
1 = Bit is set
0 = Bit is cleared
x = Bit is unknown
bit 7-4
bit 3-2
bit 1-0
REGISTER 18-2:
R/W-0
R-0
U-0
U-0
U-0
U-0
U-0
U-0
PTEN
PTDIR
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
-n = Value at POR
1 = Bit is set
0 = Bit is cleared
bit 7
bit 6
bit 5-0
Unimplemented: Read as 0
DS39616D-page 178
x = Bit is unknown
PIC18F2331/2431/4331/4431
REGISTER 18-3:
U-0
R/W-1(1)
R/W-1(1)
PWMEN2
PWMEN1
R/W-1(1)
PWMEN0
R/W-0
(3)
PMOD3
R/W-0
R/W-0
R/W-0
PMOD2
PMOD1
PMOD0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
-n = Value at POR
1 = Bit is set
0 = Bit is cleared
x = Bit is unknown
bit 7
Unimplemented: Read as 0
bit 6-4
bit 3-0
Note 1:
2:
3:
Reset condition of the PWMEN bits depends on the PWMPIN Configuration bit.
When PWMEN<2:0> = 101, PWM<5:0> outputs are enabled for PIC18F2331/2431 devices; PWM<7:0>
outputs are enabled for PIC18F4331/4431 devices.
When PWMEN<2:0> = 111, PWM Outputs 1, 3 and 5 are enabled in PIC18F2331/2431 devices; PWM
Outputs 1, 3, 5 and 7 are enabled in PIC18F4331/4431 devices.
Unimplemented in PIC18F2331/2431 devices; maintain these bits clear.
DS39616D-page 179
PIC18F2331/2431/4331/4431
REGISTER 18-4:
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
U-0
R/W-0
R/W-0
SEVOPS3
SEVOPS2
SEVOPS1
SEVOPS0
SEVTDIR
UDIS
OSYNC
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
-n = Value at POR
1 = Bit is set
0 = Bit is cleared
x = Bit is unknown
bit 7-4
bit 3
bit 2
Unimplemented: Read as 0
bit 1
bit 0
18.3.1
FREE-RUNNING MODE
In the Free-Running mode, the PWM Time Base registers (PTMRL and PTMRH) will begin counting upwards
until the value in the PWM Time Base Period register,
PTPER (PTPERL and PTPERH), is matched. The
PTMR registers will be reset on the following input
clock edge and the time base will continue counting
upwards as long as the PTEN bit remains set.
18.3.2
SINGLE-SHOT MODE
18.3.3
DS39616D-page 180
Note:
18.3.4
PIC18F2331/2431/4331/4431
18.3.5
TABLE 18-1:
PWM Frequency
Edge-Aligned
PWM Frequency
Center-Aligned
1:1
2441 Hz
1221 Hz
1:4
610 Hz
305 Hz
1:16
153 Hz
76 Hz
1:64
38 Hz
19 Hz
18.4
18.4.1
INTERRUPTS IN FREE-RUNNING
MODE
FIGURE 18-5:
A: PRESCALER = 1:1
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
FOSC/4
1
PTMR
FFEh
FFFh
000h
001h
002h
PTMR_INT_REQ
PTIF bit
B: PRESCALER = 1:4
Q4
Qc
Qc
Qc
Qc
Qc
Qc
Qc
Qc
Qc
Q4
Qc
Qc
Qc
Qc
Qc
Qc
Qc
Qc
Qc
Qc
Qc
1
PTMR
FFEh
FFFh
000h
001h
002h
PTMR_INT_REQ
PTIF bit
Note 1:
PWM Time Base Period register, PTPER, is loaded with the value, FFFh, for this example.
DS39616D-page 181
PIC18F2331/2431/4331/4431
18.4.2
INTERRUPTS IN SINGLE-SHOT
MODE
18.4.3
FIGURE 18-6:
INTERRUPTS IN CONTINUOUS
UP/DOWN COUNT MODE
A: PRESCALER = 1:1
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
FOSC/4
2
PTMR
FFEh
FFFh
000h
000h
000h
PTMR_INT_REQ
PTIF bit
B: PRESCALER = 1:4
Q4
Qc
Qc
Qc
Qc
Qc
Qc
Qc
Qc
Qc
Q4
Qc
Qc
Qc
Qc
Qc
Qc
Qc
Qc
Qc
Qc
Qc
2
PTMR
FFEh
1
000h
FFFh
1
000h
000h
PTMR_INT_REQ
PTIF bit
Note 1:
2:
DS39616D-page 182
PIC18F2331/2431/4331/4431
FIGURE 18-7:
A: PRESCALER = 1:1
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
FOSC/4
PTMR
002h
001h
000h
001h
002h
PTDIR bit
PTMR_INT_REQ
1
1
PTIF bit
B: PRESCALER = 1:4
Qc
Qc
Q4
Qc
Qc
Qc
002h
PTMR
Qc
Qc
Qc
Qc
001h
Q4
Qc
Qc
Qc
Qc
Qc
Qc
001h
000h
Qc
Qc
Qc
Qc
Qc
002h
PTDIR bit
1
PTMR_INT_REQ
PTIF bit
Note 1:
DS39616D-page 183
PIC18F2331/2431/4331/4431
18.4.4
Note:
2.
FIGURE 18-8:
A: PRESCALER = 1:1
Case 1: PTMR Counting Upwards
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
OSC1
2
PTMR
3FDh
3FEh
3FFh
3FEh
3FDh
PTDIR bit
PTMR_INT_REQ
1
1
PTIF bit
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
OSC1
PTMR
002h
001h
000h
001h
002h
PTDIR bit
PTMR_INT_REQ
1
PTIF bit
Note 1:
2:
DS39616D-page 184
PIC18F2331/2431/4331/4431
18.5
PWM Period
EQUATION 18-4:
FOSC
log FPWM
Resolution =
log(2)
TABLE 18-2:
(PTPER + 1) x PTMRPS
TPWM =
FOSC/4
EQUATION 18-2:
TPWM =
EQUATION 18-3:
PWM FREQUENCY
1
PWM Frequency =
PWM Period
PTPER
PWM
PWM
Value Resolution Frequency
FOSC
MIPS
40 MHz
10
0FFFh
14 bits
2.4 kHz
40 MHz
10
07FFh
13 bits
4.9 kHz
40 MHz
10
03FFh
12 bits
9.8 kHz
40 MHz
10
01FFh
11 bits
19.5 kHz
40 MHz
10
FFh
10 bits
39.0 kHz
40 MHz
10
7Fh
9 bits
78.1 kHz
40 MHz
10
3Fh
8 bits
156.2 kHz
40 MHz
10
1Fh
7 bits
312.5 kHz
40 MHz
10
0Fh
6 bits
625 kHz
25 MHz
6.25
0FFFh
14 bits
1.5 kHz
25 MHz
6.25
03FFh
12 bits
6.1 kHz
25 MHz
6.25
FFh
10 bits
24.4 kHz
10 MHz
2.5
0FFFh
14 bits
610 Hz
10 MHz
2.5
03FFh
12 bits
2.4 kHz
10 MHz
2.5
FFh
10 bits
9.8 kHz
5 MHz
1.25
0FFFh
14 bits
305 Hz
5 MHz
1.25
03FFh
12 bits
1.2 kHz
5 MHz
1.25
FFh
10 bits
4.9 kHz
4 MHz
0FFFh
14 bits
244 Hz
4 MHz
03FFh
12 bits
976 Hz
4 MHz
FFh
10 bits
3.9 kHz
Note:
EQUATION 18-1:
PWM RESOLUTION
DS39616D-page 185
PIC18F2331/2431/4331/4431
FIGURE 18-9:
6
5
4
4
3
FIGURE 18-10:
4
3
3
2
2
1
1
0
6
5
4
3
2
1
0
DS39616D-page 186
PIC18F2331/2431/4331/4431
18.6
18.6.1
FIGURE 18-11:
PTMRL<7:0>
PTMR<11:0>
PTMRH<3:0>
PTMRL<7:0>
Unused
Q Clocks(1)
<1:0>
Comparator
Unused
PDCxH<5:0>
PDCxL<7:0>
PDCx<13:0>
PDCxH<7:0>
PDCxL<7:0>
DS39616D-page 187
PIC18F2331/2431/4331/4431
18.6.2
FIGURE 18-13:
18.6.3
EDGE-ALIGNED PWM
FIGURE 18-12:
EDGE-ALIGNED PWM
New Duty Cycle Latched
PTPER
PDCx
(old)
PTMR
Value
PDCx
(new)
0
Duty Cycle
Active at
Beginning
of Period
Period
PWM Output
PTMR Value
DS39616D-page 188
PIC18F2331/2431/4331/4431
FIGURE 18-14:
PWM Output
PTMR Value
18.6.4
CENTER-ALIGNED PWM
FIGURE 18-15:
PTPER
Duty
Cycle
PTMR
Value
0
Start of
First
PWM
Period
Duty Cycle
Period
Period
DS39616D-page 189
PIC18F2331/2431/4331/4431
PWM5
3-Phase
Load
PWM4
PWM3
+V
PWM2
FIGURE 18-16:
PWM1
COMPLEMENTARY PWM
OPERATION
PWM0
18.6.5
DS39616D-page 190
PIC18F2331/2431/4331/4431
18.7
18.7.1
Dead-Time Generators
FIGURE 18-17:
DEAD-TIME CONTROL UNIT BLOCK DIAGRAM FOR ONE PWM OUTPUT PAIR
Dead Time
Select Bits
FOSC
DEAD-TIME INSERTION
Zero Compare
Clock Control
and Prescaler
Dead Time
Prescale
Dead-Time Register
Duty Cycle
Compare Input
FIGURE 18-18:
td
PDC1
Compare
Output
PWM1
PWM0
DS39616D-page 191
PIC18F2331/2431/4331/4431
REGISTER 18-5:
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
DTPS1
DTPS0
DT5
DT4
DT3
DT2
DT1
DT0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
-n = Value at POR
1 = Bit is set
0 = Bit is cleared
bit 7-6
bit 5-0
18.7.2
DEAD-TIME RANGES
18.7.3
2.
3.
4.
DS39616D-page 192
x = Bit is unknown
PIC18F2331/2431/4331/4431
The actual dead time is calculated from the DTCON
register as follows:
Dead Time = Dead-Time Value/(FOSC/Prescaler)
Table 18-3 shows example dead-time ranges as a
function of the input clock prescaler selected and the
device operating frequency.
TABLE 18-3:
EXAMPLE DEAD-TIME
RANGES
10
FOSC/2
50 ns
3.2 s
40
10
FOSC/4
100 ns
6.4 s
40
10
FOSC/8
200 ns
12.8 s
40
10
FOSC/16
400 ns
25.6 s
32
FOSC/2
62.5 ns
4 s
32
FOSC/4
125 ns
8 s
32
FOSC/8
250 ns
16 s
32
FOSC/16
500 ns
32 s
25
6.25
FOSC/2
80 ns
5.12 s
25
6.25
FOSC/4
160 ns
10.2 s
25
6.25
FOSC/8
320 ns
20.5 s
25
6.25
FOSC/16
640 ns
41 s
20
FOSC/2
100 ns
6.4 s
20
FOSC/4
200 ns
12.8 s
20
FOSC/8
400 ns
25.6 s
20
FOSC/16
800 ns
51.2 s
18.7.4
DEAD-TIME DISTORTION
18.8
10
2.5
FOSC/2
200 ns
12.8 s
10
2.5
FOSC/4
400 ns
25.6 s
10
2.5
FOSC/8
800 ns
51.2 s
10
2.5
FOSC/16
1.6 s
102.4 s
1.25
FOSC/2
400 ns
25.6 s
1.25
FOSC/4
800 ns
51.2 s
18.8.1
5
5
1.25
FOSC/8
1.6 s
102.4 s
1.25
FOSC/16
3.2 s
204.8 s
FOSC/2
0.5 s
32 s
FOSC/4
1 s
64 s
FOSC/8
2 s
128 s
FOSC/16
4 s
256 s
In the Independent PWM mode, each duty cycle generator is connected to both PWM output pins in a given
PWM output pair. The odd and even PWM output pins
are driven with a single PWM duty cycle generator.
PWM1 and PWM0 are driven by the PWM channel
which uses the PDC0 register to set the duty cycle,
PWM3 and PWM2 with PDC1, PWM5 and PWM4 with
PDC2, and PWM7 and PWM6 with PDC3 (see
Figure 18-3 and Register 18-4).
DS39616D-page 193
PIC18F2331/2431/4331/4431
18.8.2
FIGURE 18-19:
CENTER CONNECTED
LOAD
+V
PWM1
Load
PWM0
18.9
DS39616D-page 194
18.10.1
18.10.2
OVERRIDE SYNCHRONIZATION
PIC18F2331/2431/4331/4431
FIGURE 18-20:
POUT0
POUT1
4
PWM1
2
PWM0
DS39616D-page 195
PIC18F2331/2431/4331/4431
18.10.3
REGISTER 18-6:
The PWM Duty Cycle registers may be used in conjunction with the OVDCOND and OVDCONS registers.
The Duty Cycle registers control the average voltage
across the load and the OVDCOND and OVDCONS
registers control the commutation sequence.
Figure 18-22 shows the waveforms, while Table 18-4
and Table 18-5 show the OVDCOND and OVDCONS
register values used to generate the signals.
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
POVD7(1)
POVD6(1)
POVD5
POVD4
POVD3
POVD2
POVD1
POVD0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
-n = Value at POR
1 = Bit is set
0 = Bit is cleared
bit 7-0
Note 1:
x = Bit is unknown
REGISTER 18-7:
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
POUT7(1)
POUT6(1)
POUT5
POUT4
POUT3
POUT2
POUT1
POUT0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
-n = Value at POR
1 = Bit is set
0 = Bit is cleared
bit 7-0
Note 1:
2:
x = Bit is unknown
DS39616D-page 196
PIC18F2331/2431/4331/4431
FIGURE 18-21:
FIGURE 18-22:
PWM5
PWM4
PWM7
PWM3
PWM2
PWM6
PWM1
PWM0
PWM5
PWM4
TABLE 18-4:
State
PWM3
00000000b
00100100b
00000000b
00100001b
00000000b
00001001b
00000000b
00011000b
00000000b
00010010b
00000000b
00000110b
TABLE 18-5:
PWM2
PWM1
PWM0
State
OVDCOND (POVD)
OVDCONS (POUT)
11000011b
00000000b
11110000b
00000000b
00111100b
00000000b
00001111b
00000000b
DS39616D-page 197
PIC18F2331/2431/4331/4431
18.11 PWM Output and Polarity Control
18.11.2
HPOL
LPOL
PWMPIN
18.11.1
All PWM I/O pins are general purpose I/O. When a pair
of pins are enabled for PWM output, the PORT and
TRIS registers controlling the pins are disabled. Refer
to Figure 18-23 for details.
FIGURE 18-23:
D
CK
VDD
Data Latch
WR TRIS
CK
I/O Pin
VSS
TRIS Latch
TTL or
Schmitt
Trigger
RD TRIS
Q
D
EN
RD PORT
Note:
DS39616D-page 198
I/O pin has protection diodes to VDD and VSS. PWM polarity selection logic not shown for clarity.
PIC18F2331/2431/4331/4431
18.11.3
18.12.1
18.12.2
DS39616D-page 199
PIC18F2331/2431/4331/4431
18.12.3
DS39616D-page 200
18.12.4
PIC18F2331/2431/4331/4431
REGISTER 18-8:
R/W-0
BRFEN
R/W-0
(1)
FLTBS
R/W-0
R/W-0
(1)
FLTBMOD
(1)
FLTBEN
R/W-0
(2)
FLTCON
R/W-0
R/W-0
R/W-0
FLTAS
FLTAMOD
FLTAEN
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
-n = Value at POR
1 = Bit is set
0 = Bit is cleared
x = Bit is unknown
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Note 1:
2:
DS39616D-page 201
PIC18F2331/2431/4331/4431
18.13 PWM Update Lockout
For a complex PWM application, the user may need to
write up to four Duty Cycle registers and the PWM Time
Base Period register, PTPER, at a given time. In some
applications, it is important that all buffer registers be
written before the new duty cycle and period values are
loaded for use by the module.
A PWM update lockout feature may optionally be
enabled so the user may specify when new duty cycle
buffer values are valid. The PWM update lockout
feature is enabled by setting the control bit, UDIS, in
the PWMCON1 register. This bit affects all Duty Cycle
Buffer registers and the PWM Time Base Period
register, PTPER.
To perform a PWM update lockout:
1.
2.
3.
4.
18.14.1
18.14.2
DS39616D-page 202
PIC18F2331/2431/4331/4431
TABLE 18-6:
Name
INTCON
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reset
Values
on Page:
GIE/GIEH
PEIE/GIEL
TMR0IE
INT0IE
RBIE
TMR0IF
INT0IF
RBIF
54
IPR3
PTIP
IC3DRIP
IC2QEIP
IC1IP
TMR5IP
56
PIE3
PTIE
IC3DRIE
IC2QEIE
IC1IE
TMR5IE
56
IC3DRIF
IC2QEIF
IC1IF
TMR5IF
56
58
PTIF
PTCON0
PTOPS3
PTOPS2
PTOPS1
PTOPS0
PTCON1
PTEN
PTDIR
PIR3
PTMRL(1)
PTMRH(1)
58
UNUSED
PTPERL(1)
58
58
PTPERH(1)
UNUSED
58
SEVTCMPH
PWMCON0
PWMCON1
DTCON
58
PWM Special Event Compare Register
(upper 4 bits)
UNUSED
58
PWMEN2
PWMEN1
PWMEN0
PMOD3(2)
PMOD2
PMOD1
PMOD0
58
SEVOPS3 SEVOPS2
SEVOPS1
SEVOPS0
SEVTDIR
UDIS
OSYNC
58
DT5
DT4
DT3
DT2
DT1
DT0
58
FLTBMOD(2)
FLTBEN(2)
DTPS1
DTPS0
(2)
FLTCONFIG
BRFEN
FLTCON
FLTAS
OVDCOND
POVD7(2)
POVD6(2)
POVD5
POVD4
POVD3
POVD2
POVD1
POVD0
OVDCONS
POUT7(2)
POUT6(2)
POUT5
POUT4
POUT3
POUT2
POUT1
POUT0
(1)
PDC0L
PDC0H(1)
(1)
PDC1L
PDC1H(1)
PDC2L(1)
PDC2H(1)
PDC3L(1,2)
PDC3H(1,2)
Legend:
Note 1:
2:
58
FLTBS
FLTAMOD FLTAEN
58
58
58
58
58
58
58
58
58
58
58
= Unimplemented, read as 0. Shaded cells are not used with the power control PWM.
Double-buffered register pairs. Refer to text for explanation of how these registers are read and written to.
Unimplemented in PIC18F2331/2431 devices; maintain these bits clear. Reset values shown are for
PIC18F4331/4431 devices.
DS39616D-page 203
PIC18F2331/2431/4331/4431
NOTES:
DS39616D-page 204
PIC18F2331/2431/4331/4431
19.0
19.1
19.2
SPI Mode
This section contains register definitions and operational characteristics of the SPI module. Additional
information on the SPI module can be found in the
PIC Mid-Range MCU Family Reference Manual
(DS33023).
SPI mode allows 8 bits of data to be synchronously
transmitted and received simultaneously. To accomplish
communication, typically three pins are used:
Serial Data Out (SDO)
Serial Data In (SDI)
Serial Clock (SCK)
Additionally, a fourth pin may be used when in a Slave
mode of operation:
Slave Select (SS)
When initializing the SPI, several options need to be
specified. This is done by programming the appropriate
control bits in the SSPCON (SSPCON<5:0>) and
SSPSTAT<7:6> registers. These control bits allow the
following to be specified:
DS39616D-page 205
PIC18F2331/2431/4331/4431
REGISTER 19-1:
R/W-0
R/W-0
R-0
R-0
R-0
R-0
R-0
R-0
SMP
CKE
D/A
R/W
UA
BF
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
-n = Value at POR
1 = Bit is set
0 = Bit is cleared
x = Bit is unknown
bit 7
bit 6
CKE: SPI Clock Edge Select bit (Figure 19-2, Figure 19-3 and Figure 19-4)
SPI mode, CKP = 0:
1 = Data transmitted on rising edge of SCK
0 = Data transmitted on falling edge of SCK
SPI mode, CKP = 1:
1 = Data transmitted on falling edge of SCK
0 = Data transmitted on rising edge of SCK
I2 C mode:
This bit must be maintained clear.
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
DS39616D-page 206
PIC18F2331/2431/4331/4431
REGISTER 19-2:
R/W-0
WCOL
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 7
R/W-0
SSPOV(1)
R/W-0
SSPEN(2)
W = Writable bit
1 = Bit is set
R/W-0
CKP
R/W-0
SSPM3(3)
R/W-0
SSPM2(3)
R/W-0
SSPM1(3)
R/W-0
SSPM0(3)
bit 0
bit 6
bit 5
bit 4
Note 1:
2:
3:
In Master mode, the overflow bit is not set since each new reception (and transmission) is initiated by
writing to the SSPBUF register.
When enabled, these pins must be properly configured as inputs or outputs.
Bit combinations not specifically listed here are either reserved or implemented in I2C mode only.
DS39616D-page 207
PIC18F2331/2431/4331/4431
REGISTER 19-2:
bit 3-0
Note 1:
2:
3:
In Master mode, the overflow bit is not set since each new reception (and transmission) is initiated by
writing to the SSPBUF register.
When enabled, these pins must be properly configured as inputs or outputs.
Bit combinations not specifically listed here are either reserved or implemented in I2C mode only.
DS39616D-page 208
PIC18F2331/2431/4331/4431
FIGURE 19-1:
Write
SSPBUF Reg
SSPSR Reg
SDI
SDO
Shift
Clock
bit 0
Peripheral OE
SS Control
Enable
SS
Edge
Select
2
Clock Select
SSPM<3:0>
4
Edge
Select
SCK
TRISC<3>
TMR2 Output
2
Prescaler
4, 16, 64
TCY
DS39616D-page 209
PIC18F2331/2431/4331/4431
FIGURE 19-2:
SCK (CKP = 0,
CKE = 0)
SCK (CKP = 0,
CKE = 1)
SCK (CKP = 1,
CKE = 0)
SCK (CKP = 1,
CKE = 1)
SDO
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
SDI (SMP = 0)
bit 7
bit 0
SDI (SMP = 1)
bit 0
bit 7
SSPIF
FIGURE 19-3:
SS (optional)
SCK (CKP = 0)
SCK (CKP = 1)
SDO
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
SDI (SMP = 0)
bit 7
bit 0
SSPIF
DS39616D-page 210
PIC18F2331/2431/4331/4431
FIGURE 19-4:
SS
SCK (CKP = 0)
SCK (CKP = 1)
SDO
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
SDI (SMP = 0)
bit 0
bit 7
SSPIF
TABLE 19-1:
Name
INTCON
PIR1
PIE1
Bit 6
Bit 5
Bit 4
GIE/GIEH
PEIE/GIEL
TMR0IE
ADIF
RCIF
ADIE
RCIE
TRISC
SSPBUF
SSPCON
TRISA
SSPSTAT
WCOL
(1)
TRISA7
SMP
SSPOV
TRISA6(2)
CKE
SSPEN
Bit 0
Reset Values
on Page:
INT0IF
RBIF
54
TMR2IF
TMR1IF
57
TMR1IE
57
Bit 3
Bit 2
Bit 1
INT0IE
RBIE
TMR0IF
TXIF
SSPIF
CCP1IF
TXIE
SSPIE
CCP1IE
TMR2IE
57
55
CKP
SSPM3
SSPM2
SSPM1
SSPM0
55
57
R/W
UA
BF
55
Legend: = unimplemented, read as 0. Shaded cells are not used by the SSP in SPI mode.
Note 1: RA7 and associated bits are configured as port pins in INTIO2 Oscillator mode only and read 0 in all other
oscillator modes.
2: RA6 and associated bits are configured as port pins in RCIO, ECIO and INTIO2 (with port function on RA6)
Oscillator modes only and read 0 in all other oscillator modes.
DS39616D-page 211
PIC18F2331/2431/4331/4431
19.3
SSP I2 C Operation
FIGURE 19-5:
MSb
LSb
Match Detect
Addr Match
SSPADD Reg
Start and
Stop bit Detect
Set, Reset
S, P bits
(SSPSTAT Reg)
DS39616D-page 212
SLAVE MODE
In Slave mode, the SCL and SDA pins must be configured as inputs (TRISC<5:4> or TRISD<3:2> set). The
SSP module will override the input state with the output
data when required (slave-transmitter).
SSPSR Reg
Note 1:
19.3.1
Shift
Clock
SDI/SDA(1)
Write
SSPBUF Reg
SCK/SCL(1)
The SSPCON register allows control of the I 2C operation. Four mode selection bits (SSPCON<3:0>) allow
one of the following I 2C modes to be selected:
PIC18F2331/2431/4331/4431
19.3.1.1
Addressing
TABLE 19-2:
3.
4.
5.
6.
7.
8.
9.
SSPSR SSPBUF
Generate ACK
Pulse
BF
SSPOV
Yes
Yes
Yes
No
No
Yes
No
No
Yes
No
No
Yes
0
Note:
Shaded cells show the conditions where the user software did not properly clear the overflow condition.
DS39616D-page 213
PIC18F2331/2431/4331/4431
19.3.1.2
Reception
FIGURE 19-6:
Receiving Address
SDA
SCL
R/W = 0
ACK
A7 A6 A5 A4 A3 A2 A1
S
SSPIF (PIR1<3>)
BF (SSPSTAT<0>)
Receiving Data
ACK
D7 D6 D5 D4 D3 D2 D1 D0
1
Receiving Data
ACK
D7 D6 D5 D4 D3 D2 D1 D0
1
Cleared in software
P
Bus master
terminates
transfer
SSPOV (SSPCON<6>)
SSPOV bit is set because the SSPBUF register is still full
ACK is not sent
DS39616D-page 214
PIC18F2331/2431/4331/4431
19.3.1.3
Transmission
FIGURE 19-7:
Receiving Address
SDA
SCL
A7
As a slave-transmitter, the ACK pulse from the masterreceiver is latched on the rising edge of the ninth SCL
input pulse. If the SDA line was high (not ACK), then the
data transfer is complete. When the ACK is latched by
the slave, the slave logic is reset and the slave then
monitors for another occurrence of the Start bit. If the
SDA line was low (ACK), the transmit data must be
loaded into the SSPBUF register, which also loads the
SSPSR register. Then pin, SCK/SCL, should be enabled
by setting bit CKP.
R/W = 1
A6
A5
A4
A3
A2
A1
1
2
Data in
sampled
SSPIF (PIR1<3>)
Transmitting Data
ACK
D7
1
SCL held low
while CPU
responds to SSPIF
ACK
D6
D5
D4
D3
D2
D1
D0
Cleared in software
BF (SSPSTAT<0>)
SSPBUF is written in software
CKP (SSPCON<4>)
Set bit after writing to SSPBUF
(SSPBUF must be written to
before the CKP bit can be set)
DS39616D-page 215
PIC18F2331/2431/4331/4431
19.3.2
MASTER MODE
19.3.3
In Master mode, the SCL and SDA lines are manipulated by clearing the corresponding TRISC<5:4> or
TRISD<3:2> bits. The output level is always low,
regardless of the value(s) in PORTC<5:4> or
PORTD<3:2>. So when transmitting data, a 1 data bit
must have the TRISC<4> bit set (input) and a 0 data
bit must have the TRISC<4> bit cleared (output). The
same scenario is true for the SCL line with the
TRISC<4> or TRISD<2> bit. Pull-up resistors must be
provided externally to the SCL and SDA pins for proper
operation of the I2C module.
Start condition
Stop condition
Data transfer byte transmitted/received
Master mode of operation can be done with either the
Slave mode Idle (SSPM<3:0> = 1011) or with the
Slave active. When both Master and Slave modes are
enabled, the software needs to differentiate the
source(s) of the interrupt.
TABLE 19-3:
Name
INTCON
PIR1
PIE1
SSPBUF
SSPADD
MULTI-MASTER MODE
Bit 6
Bit 5
Bit 4
GIE/GIEH
PEIE/GIEL
TMR0IE
ADIF
RCIF
ADIE
RCIE
Bit 1
Bit 0
Reset Values
on Page:
Bit 3
Bit 2
INT0IE
RBIE
TMR0IF
INT0IF
RBIF
54
TXIF
SSPIF
CCP1IF
TMR2IF
TMR1IF
57
TXIE
SSPIE
CCP1IE
TMR2IE
TMR1IE
57
(I2
55
C mode)
55
SSPCON
WCOL
SSPOV
SSPEN
CKP
SSPM3
SSPM2
SSPM1
SSPM0
55
SSPSTAT
(1)
CKE(1)
D/A
R/W
UA
BF
55
SMP
TRISC(2)
TRISD(2)
57
57
2C
mode.
Legend: = unimplemented, read as 0. Shaded cells are not used by the SSP module in I
Note 1: Maintain these bits clear in I2C mode.
2: Depending upon the setting of SSPMX in CONFIG3H, these pins are multiplexed to PORTC or PORTD.
DS39616D-page 216
PIC18F2331/2431/4331/4431
20.0
ENHANCED UNIVERSAL
SYNCHRONOUS
ASYNCHRONOUS RECEIVER
TRANSMITTER (EUSART)
20.1
Asynchronous Operation in
Power-Managed Modes
The factory calibrates the internal oscillator block output (INTOSC) for 8 MHz (see Table 26-6). However,
this frequency may drift as VDD or temperature
changes, and this directly affects the asynchronous
baud rate. Two methods may be used to adjust the
baud rate clock, but both require a reference clock
source of some kind.
The first (preferred) method uses the OSCTUNE
register to adjust the INTOSC output back to 8 MHz.
Adjusting the value in the OSCTUNE register allows for
fine resolution changes to the system clock source (see
Section 3.6.4 INTOSC Frequency Drift for more
information).
The other method adjusts the value in the Baud Rate
Generator (BRG). There may not be fine enough
resolution when adjusting the Baud Rate Generator to
compensate for a gradual change in the peripheral
clock frequency.
DS39616D-page 217
PIC18F2331/2431/4331/4431
REGISTER 20-1:
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R-1
R/W-0
CSRC
TX9
TXEN(1)
SYNC
SENDB
BRGH
TRMT
TX9D
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
-n = Value at POR
1 = Bit is set
0 = Bit is cleared
x = Bit is unknown
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Note 1:
DS39616D-page 218
PIC18F2331/2431/4331/4431
REGISTER 20-2:
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R-0
R-0
R-x
SPEN
RX9
SREN
CREN
ADDEN
FERR
OERR
RX9D
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
-n = Value at POR
1 = Bit is set
0 = Bit is cleared
x = Bit is unknown
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
DS39616D-page 219
PIC18F2331/2431/4331/4431
REGISTER 20-3:
U-0
R-1
U-0
R/W-1
R/W-0
U-0
R/W-0
R/W-0
RCIDL
SCKP
BRG16
WUE
ABDEN
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
-n = Value at POR
1 = Bit is set
0 = Bit is cleared
x = Bit is unknown
bit 7
Unimplemented: Read as 0
bit 6
bit 5
Unimplemented: Read as 0
bit 4
bit 3
bit 2
Unimplemented: Read as 0
bit 1
bit 0
DS39616D-page 220
PIC18F2331/2431/4331/4431
20.2
20.2.1
POWER-MANAGED MODE
OPERATION
20.2.2
SAMPLING
TABLE 20-1:
Configuration Bits
BRG/EUSART Mode
8-Bit/Asynchronous
FOSC/[64 (n + 1)]
SYNC
BRG16
BRGH
8-Bit/Asynchronous
16-Bit/Asynchronous
16-Bit/Asynchronous
8-Bit/Synchronous
16-Bit/Synchronous
FOSC/[16 (n + 1)]
FOSC/[4 (n + 1)]
DS39616D-page 221
PIC18F2331/2431/4331/4431
EXAMPLE 20-1:
For a device with FOSC of 16 MHz, desired baud rate of 9600, Asynchronous mode, 8-bit BRG:
Desired Baud Rate = FOSC/(64 ([SPBRGH:SPBRG] + 1))
Solving for SPBRGH:SPBRG:
X = ((FOSC/Desired Baud Rate)/64) 1
= ((16000000/9600)/64) 1
= [25.042] = 25
Calculated Baud Rate = 16000000/(64 (25 + 1))
= 9615
Error
= (Calculated Baud Rate Desired Baud Rate)/Desired Baud Rate
= (9615 9600)/9600 = 0.16%
TABLE 20-2:
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reset Values
on Page:
TXSTA
CSRC
TX9
TXEN
SYNC
SENDB
BRGH
TRMT
TX9D
56
RCSTA
SPEN
RX9
SREN
CREN
ADDEN
FERR
OERR
RX9D
56
RCIDL
SCKP
BRG16
WUE
ABDEN
56
BAUDCON
SPBRGH
56
SPBRG
56
Legend: = unimplemented, read as 0. Shaded cells are not used by the BRG.
TABLE 20-3:
BAUD
RATE
(K)
(decimal)
Actual
Rate
(K)
%
Error
1.221
2.441
1.73
255
9.615
0.16
64
19.2
19.531
1.73
57.6
56.818
115.2
125.000
(decimal)
Actual
Rate
(K)
%
Error
1.73
255
1.202
2.404
0.16
129
9.766
1.73
31
31
19.531
1.73
-1.36
10
62.500
8.51
104.167
Actual
Rate
(K)
%
Error
0.3
1.2
2.4
9.6
SPBRG
value
(decimal)
Actual
Rate
(K)
%
Error
0.16
129
1.201
-0.16
103
2.404
0.16
64
2.403
-0.16
51
9.766
1.73
15
9.615
-0.16
12
15
19.531
1.73
8.51
52.083
-9.58
-9.58
78.125
-32.18
SPBRG
value
SPBRG
value
SPBRG
value
(decimal)
(decimal)
Actual
Rate
(K)
0.16
207
0.300
-0.16
103
0.300
-0.16
51
0.16
51
1.201
-0.16
25
1.201
-0.16
12
2.404
0.16
25
2.403
-0.16
12
9.6
8.929
-6.99
19.2
20.833
8.51
Actual
Rate
(K)
%
Error
0.3
0.300
1.2
1.202
2.4
SPBRG
value
%
Error
(decimal)
Actual
Rate
(K)
%
Error
SPBRG
value
SPBRG
value
(decimal)
57.6
62.500
8.51
115.2
62.500
-45.75
DS39616D-page 222
PIC18F2331/2431/4331/4431
TABLE 20-3:
BAUD
RATE
(K)
%
Error
SPBRG
value
(decimal)
Actual
Rate
(K)
%
Error
SPBRG
value
(decimal)
%
Error
SPBRG
value
(decimal)
%
Error
SPBRG
value
(decimal)
2.4
2.441
1.73
255
2.403
-0.16
9.6
9.766
1.73
255
9.615
0.16
129
9.615
0.16
64
9.615
-0.16
207
51
19.2
19.231
0.16
129
19.231
0.16
64
19.531
1.73
31
19.230
-0.16
25
57.6
58.140
0.94
42
56.818
-1.36
21
56.818
-1.36
10
55.555
3.55
115.2
113.636
-1.36
21
113.636
-1.36
10
125.000
8.51
(decimal)
Actual
Rate
(K)
%
Error
0.16
207
1.201
0.16
103
2.403
9.615
0.16
25
19.2
19.231
0.16
57.6
62.500
115.2
125.000
(decimal)
Actual
Rate
(K)
%
Error
0.300
-0.16
207
-0.16
103
1.201
-0.16
51
-0.16
51
2.403
-0.16
25
9.615
-0.16
12
12
8.51
8.51
Actual
Rate
(K)
%
Error
0.3
1.2
1.202
2.4
2.404
9.6
SPBRG
value
SPBRG
value
SPBRG
value
(decimal)
%
Error
SPBRG
value
(decimal)
Actual
Rate
(K)
%
Error
(decimal)
Actual
Rate
(K)
SPBRG
value
%
Error
(decimal)
Actual
Rate
(K)
%
Error
SPBRG
value
SPBRG
value
(decimal)
0.3
0.300
0.00
8332
0.300
0.02
4165
0.300
0.02
2082
0.300
-0.04
1.2
1.200
0.02
2082
1.200
-0.03
1041
1.200
-0.03
520
1.201
-0.16
1665
415
2.4
2.402
0.06
1040
2.399
-0.03
520
2.404
0.16
259
2.403
-0.16
207
9.6
9.615
0.16
259
9.615
0.16
129
9.615
0.16
64
9.615
-0.16
51
19.2
19.231
0.16
129
19.231
0.16
64
19.531
1.73
31
19.230
-0.16
25
57.6
58.140
0.94
42
56.818
-1.36
21
56.818
-1.36
10
55.555
3.55
115.2
113.636
-1.36
21
113.636
-1.36
10
125.000
8.51
(decimal)
Actual
Rate
(K)
%
Error
0.04
0.16
832
207
0.300
1.201
2.404
0.16
103
9.615
0.16
25
19.2
19.231
0.16
57.6
62.500
8.51
115.2
125.000
8.51
Actual
Rate
(K)
%
Error
0.3
1.2
0.300
1.202
2.4
9.6
(decimal)
Actual
Rate
(K)
%
Error
-0.16
-0.16
415
103
0.300
1.201
-0.16
-0.16
207
51
2.403
-0.16
51
2.403
-0.16
25
9.615
-0.16
12
12
SPBRG
value
SPBRG
value
SPBRG
value
(decimal)
DS39616D-page 223
PIC18F2331/2431/4331/4431
TABLE 20-3:
BAUD
RATE
(K)
(decimal)
Actual
Rate
(K)
%
Error
0.00
33332
0.300
0.00
8332
1.200
2.400
0.02
4165
9.6
9.606
0.06
19.2
19.193
57.6
57.803
115.2
114.943
(decimal)
Actual
Rate
(K)
%
Error
0.00
16665
0.300
0.02
4165
1.200
2.400
0.02
2082
1040
9.596
-0.03
-0.03
520
19.231
0.35
172
57.471
-0.22
86
116.279
0.94
Actual
Rate
(K)
%
Error
0.3
0.300
1.2
1.200
2.4
SPBRG
value
(decimal)
Actual
Rate
(K)
%
Error
0.00
8332
0.300
-0.01
6665
0.02
2082
1.200
-0.04
1665
2.402
0.06
1040
2.400
-0.04
832
520
9.615
0.16
259
9.615
-0.16
207
0.16
259
19.231
0.16
129
19.230
-0.16
103
-0.22
86
58.140
0.94
42
57.142
0.79
34
42
113.636
-1.36
21
117.647
-2.12
16
SPBRG
value
SPBRG
value
SPBRG
value
(decimal)
(decimal)
Actual
Rate
(K)
%
Error
3332
0.300
-0.04
0.04
832
1.201
0.16
415
2.403
Actual
Rate
(K)
%
Error
0.3
0.300
0.01
1.2
1.200
2.4
2.404
SPBRG
value
(decimal)
Actual
Rate
(K)
%
Error
1665
0.300
-0.04
832
-0.16
415
1.201
-0.16
207
-0.16
207
2.403
-0.16
103
SPBRG
value
SPBRG
value
(decimal)
9.6
9.615
0.16
103
9.615
-0.16
51
9.615
-0.16
25
19.2
19.231
0.16
51
19.230
-0.16
25
19.230
-0.16
12
57.6
58.824
2.12
16
55.555
3.55
115.2
111.111
-3.55
DS39616D-page 224
PIC18F2331/2431/4331/4431
20.2.3
This allows the user to verify that no carry occurred for 8bit modes by checking for 00h in the SPBRGH register.
Refer to Table 20-4 for counter clock rates to the BRG.
While the ABD sequence takes place, the EUSART
state machine is held in Idle. The RCIF interrupt is set
once the fifth rising edge on RX is detected. The value
in the RCREG needs to be read to clear the RCIF
interrupt. RCREG content should be discarded.
Note 1: If the WUE bit is set with the ABDEN bit,
Auto-Baud Rate Detection will occur on
the byte following the Break character
(see Section 20.3.4 Auto-Wake-up on
Sync Break Character).
TABLE 20-4:
While calibrating the baud rate period, the BRG registers are clocked at 1/8th the preconfigured clock rate.
The BRG clock can be configured by the BRG16 and
BRGH bits. The BRG16 bit must be set to use both
SPBRG and SPBRGH as a 16-bit counter.
BRG16
BRGH
FOSC/512
FOSC/256
FOSC/128
FOSC/32
FIGURE 20-1:
BRG Value
XXXXh
0000h
001Ch
Start
RX Pin
Edge #1
Bit 1
Bit 0
Edge #2
Bit 3
Bit 2
Edge #3
Bit 5
Bit 4
Edge #4
Bit 7
Bit 6
Edge #5
Stop Bit
BRG Clock
Auto-Cleared
Set by user
ABDEN bit
RCIF bit
(Interrupt)
Read
RCREG
SPBRG
XXXXh
1Ch
SPBRGH
XXXXh
00h
Note 1:
The ABD sequence requires the EUSART module to be configured in Asynchronous mode and WUE = 0.
DS39616D-page 225
PIC18F2331/2431/4331/4431
20.3
20.3.1
EUSART ASYNCHRONOUS
TRANSMITTER
DS39616D-page 226
2.
3.
4.
5.
6.
7.
PIC18F2331/2431/4331/4431
FIGURE 20-2:
TXREG Register
TXIE
8
MSb
LSb
(8)
Pin Buffer
and Control
TSR Register
RC6/TX/CK/SS Pin
Interrupt
TXEN
BRG16
SPBRGH
SPEN
SPBRG
TX9
FIGURE 20-3:
Write to TXREG
BRG Output
(Shift Clock)
ASYNCHRONOUS TRANSMISSION
Word 1
RC6/TX/CK/SS
(pin)
Start bit
bit 0
bit 1
bit 7/8
Stop bit
Word 1
TXIF bit
(Interrupt Reg. Flag)
TRMT bit
(Transmit Shift
Reg. Empty Flag)
FIGURE 20-4:
1 TCY
Word 1
Transmit Shift Reg
Write to TXREG
BRG Output
(Shift Clock)
Word 1
RC6/TX/CK/SS
(pin)
TXIF bit
(Interrupt Reg. Flag)
Word 2
Start bit
bit 0
1 TCY
bit 1
Word 1
bit 7/8
Stop bit
Start bit
Word 2
bit 0
1 TCY
TRMT bit
(Transmit Shift
Reg. Empty Flag)
Word 1
Transmit Shift Reg.
Word 2
Transmit Shift Reg.
DS39616D-page 227
PIC18F2331/2431/4331/4431
TABLE 20-5:
Name
INTCON
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reset Values
on Page:
GIE/GIEH
PEIE/GIEL
TMR0IE
INT0IE
RBIE
TMR0IF
INT0IF
RBIF
54
PIR1
ADIF
RCIF
TXIF
SSPIF
CCP1IF
TMR2IF
TMR1IF
57
PIE1
ADIE
RCIE
TXIE
SSPIE
CCP1IE TMR2IE
TMR1IE
57
ADIP
RCIP
TXIP
SSPIP
CCP1IP TMR2IP
TMR1IP
57
SPEN
RX9
SREN
CREN
ADDEN
FERR
OERR
RX9D
56
IPR1
RCSTA
TXREG
TXSTA
56
CSRC
TX9
TXEN
SYNC
SENDB
BRGH
TRMT
TX9D
56
RCIDL
SCKP
BRG16
WUE
ABDEN
56
BAUDCON
SPBRGH
56
SPBRG
56
Legend: = unimplemented, read as 0. Shaded cells are not used for asynchronous transmission.
DS39616D-page 228
PIC18F2331/2431/4331/4431
20.3.2
EUSART ASYNCHRONOUS
RECEIVER
20.3.3
FIGURE 20-5:
OERR
FERR
SPBRGH
SPBRG
64
or
16
or
4
MSb
RSR Register
LSb
Stop
Start
(8)
RX9
Pin Buffer
and Control
Data
Recovery
RX9D
RC7/RX/DT/SDO
RCREG Register
FIFO
SPEN
8
Interrupt
RCIF
RCIE
Data Bus
DS39616D-page 229
PIC18F2331/2431/4331/4431
To set up an Asynchronous Transmission:
1.
2.
3.
4.
5.
FIGURE 20-6:
6.
7.
ASYNCHRONOUS RECEPTION
Start
bit bit 0
RX (Pin)
bit 1
Rcv Shift
Reg
Rcv Buffer Reg
Start
bit
bit 0
Stop
bit
Start
bit
bit 7/8
Stop
bit
Word 2
RCREG
Word 1
RCREG
Read Rcv
Buffer Reg
RCREG
bit 7/8
RCIF
(Interrupt Flag)
OERR bit
CREN
This timing diagram shows three words appearing on the RX input. The RCREG (Receive Buffer) is read after
the third word, causing the OERR (Overrun) bit to be set.
Note:
TABLE 20-6:
Name
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reset Values
on Page:
GIE/GIEH
PEIE/GIEL
TMR0IE
INT0IE
RBIE
TMR0IF
INT0IF
RBIF
54
PIR1
ADIF
RCIF
TXIF
SSPIF
CCP1IF
TMR2IF
TMR1IF
57
PIE1
ADIE
RCIE
TXIE
SSPIE
CCP1IE
TMR2IE
TMR1IE
57
IPR1
ADIP
RCIP
TXIP
SSPIP
CCP1IP
TMR2IP
TMR1IP
57
SPEN
RX9
SREN
CREN
ADDEN
FERR
OERR
RX9D
56
INTCON
RCSTA
RCREG
TXSTA
BAUDCON
56
CSRC
TX9
TXEN
SYNC
SENDB
BRGH
TRMT
TX9D
56
RCIDL
SCKP
BRG16
WUE
ABDEN
56
SPBRGH
56
SPBRG
56
Legend: = unimplemented, read as 0. Shaded cells are not used for asynchronous reception.
DS39616D-page 230
PIC18F2331/2431/4331/4431
20.3.4
20.3.4.1
FIGURE 20-7:
20.3.4.2
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
OSC1
WUE bit(1)
Auto-Cleared
RX/DT Line
RCIF
Cleared Due to User Read of RCREG
Note 1:
FIGURE 20-8:
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
Q1
Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
OSC1
WUE bit(2)
Auto-Cleared
RX/DT Line
Note 1
RCIF
Sleep Command Executed
Note 1:
2:
Sleep Ends
If the wake-up event requires long oscillator warm-up time, the auto-clear of the WUE bit can occur while the stposc signal is still active.
This sequence should not depend on the presence of Q clocks.
The EUSART remains in Idle while the WUE bit is set.
DS39616D-page 231
PIC18F2331/2431/4331/4431
20.3.5
20.3.5.1
20.3.6
FIGURE 20-9:
Write to TXREG
Dummy Write
BRG Output
(Shift Clock)
TX (Pin)
Start Bit
Bit 0
Bit 1
Bit 11
Stop Bit
Break
TXIF bit
(Interrupt Reg. Flag)
TRMT bit
(Transmit Shift
Reg. Empty Flag)
SENDB
(Transmit Shift
Reg. Empty Flag)
DS39616D-page 232
Auto-Cleared
PIC18F2331/2431/4331/4431
20.4
The Master mode indicates that the processor transmits the master clock on the CK line. Clock polarity is
selected with the SCKP bit (BAUDCON<4>). Setting
SCKP sets the Idle state on CK as high, while clearing
the bit, sets the Idle state low. This option is provided to
support Microwire devices with this module.
20.4.1
2.
FIGURE 20-10:
3.
4.
5.
6.
7.
8.
SYNCHRONOUS TRANSMISSION
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
RC7/RX/DT/
SDO Pin
bit 0
bit 1
Word 1
RC6/TX/CK/
SS Pin
(SCKP = 0)
bit 2
Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
bit 7
bit 0
bit 1
bit 7
Word 2
RC6/TX/CK/
SS pin
(SCKP = 1)
Write to
TXREG Reg
Write Word 1
Write Word 2
TXIF bit
(Interrupt Flag)
TRMT bit
TXEN bit
Note:
DS39616D-page 233
PIC18F2331/2431/4331/4431
FIGURE 20-11:
RC7/RX/DT/SDO Pin
bit 0
bit 1
bit 2
bit 6
bit 7
RC6/TX/CK/SS Pin
Write to
TXREG Reg
TXIF bit
TRMT bit
TXEN bit
TABLE 20-7:
Name
INTCON
Bit 6
GIE/GIEH PEIE/GIEL
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reset Values
on Page:
TMR0IE
INT0IE
RBIE
TMR0IF
INT0IF
RBIF
54
PIR1
ADIF
RCIF
TXIF
SSPIF
CCP1IF
TMR2IF
TMR1IF
57
PIE1
ADIE
RCIE
TXIE
SSPIE
CCP1IE
TMR2IE
TMR1IE
57
ADIP
RCIP
TXIP
SSPIP
CCP1IP
TMR2IP
TMR1IP
57
SPEN
RX9
SREN
CREN
ADDEN
FERR
OERR
RX9D
56
IPR1
RCSTA
TXREG
TXSTA
BAUDCON
56
CSRC
TX9
TXEN
SYNC
SENDB
BRGH
TRMT
TX9D
56
RCIDL
SCKP
BRG16
WUE
ABDEN
56
SPBRGH
56
SPBRG
56
Legend: = unimplemented, read as 0. Shaded cells are not used for synchronous master transmission.
DS39616D-page 234
PIC18F2331/2431/4331/4431
20.4.2
2.
FIGURE 20-12:
3.
4.
5.
6.
Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
RC7/RX/DT/SDO
Pin
bit 0
bit 1
bit 2
bit 3
bit 4
bit 5
bit 6
bit 7
RC6/TX/CK/SS
Pin
(SCKP = 0)
RC6/TX/CK/SS
Pin
(SCKP = 1)
Write to
SREN bit
SREN bit
CREN bit
RCIF bit
(Interrupt)
Read
RXREG
Note:
Timing diagram demonstrates Sync Master mode with SREN bit = 1 and BRGH bit = 0.
DS39616D-page 235
PIC18F2331/2431/4331/4431
TABLE 20-8:
Name
INTCON
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reset Values
on Page:
GIE/GIEH
PEIE/GIEL
TMR0IE
INT0IE
RBIE
TMR0IF
INT0IF
RBIF
54
PIR1
ADIF
RCIF
TXIF
SSPIF
CCP1IF
TMR2IF
TMR1IF
57
PIE1
ADIE
RCIE
TXIE
SSPIE
CCP1IE TMR2IE
TMR1IE
57
ADIP
RCIP
TXIP
SSPIP
CCP1IP TMR2IP
TMR1IP
57
SPEN
RX9
SREN
CREN
ADDEN
FERR
OERR
RX9D
56
IPR1
RCSTA
RCREG
TXSTA
BAUDCON
56
CSRC
TX9
TXEN
SYNC
SENDB
BRGH
TRMT
TX9D
56
RCIDL
SCKP
BRG16
WUE
ABDEN
56
SPBRGH
56
SPBRG
56
Legend: = unimplemented, read as 0. Shaded cells are not used for synchronous master reception.
DS39616D-page 236
PIC18F2331/2431/4331/4431
20.5
1.
20.5.1
2.
3.
4.
5.
6.
7.
8.
e)
TABLE 20-9:
Name
Bit 6
Bit 5
Bit 4
Bit 2
Bit 1
Bit 0
Reset Values
on Page:
GIE/GIEH
PEIE/GIEL
RBIE
TMR0IF
INT0IF
RBIF
54
PIR1
ADIF
RCIF
TXIF
SSPIF
CCP1IF
TMR2IF
TMR1IF
57
PIE1
ADIE
RCIE
TXIE
SSPIE
CCP1IE
TMR2IE
TMR1IE
57
IPR1
ADIP
RCIP
TXIP
SSPIP
CCP1IP
TMR2IP
TMR1IP
57
CREN
ADDEN
FERR
OERR
RX9D
56
INTCON
RCSTA
TXREG
TXSTA
BAUDCON
SPEN
TMR0IE INT0IE
Bit 3
RX9
SREN
56
CSRC
TX9
TXEN
SYNC
SENDB
BRGH
TRMT
TX9D
56
RCIDL
SCKP
BRG16
WUE
ABDEN
56
SPBRGH
56
SPBRG
56
Legend: = unimplemented, read as 0. Shaded cells are not used for synchronous slave transmission.
DS39616D-page 237
PIC18F2331/2431/4331/4431
20.5.2
2.
3.
4.
5.
6.
7.
8.
9.
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reset Values
on Page:
GIE/GIEH
PEIE/GIEL
TMR0IE
INT0IE
RBIE
TMR0IF
INT0IF
RBIF
54
TMR2IF
PIR1
ADIF
RCIF
TXIF
SSPIF
CCP1IF
TMR1IF
57
PIE1
ADIE
RCIE
TXIE
SSPIE
57
ADIP
RCIP
TXIP
SSPIP
SPEN
RX9
SREN
CREN
ADDEN
FERR
OERR
RX9D
IPR1
RCSTA
RCREG
TXSTA
56
CSRC
TX9
TXEN
SYNC
SENDB
BRGH
TRMT
TX9D
RCIDL
SCKP
BRG16
WUE
ABDEN
BAUDCON
57
56
56
56
SPBRGH
56
SPBRG
56
Legend: = unimplemented, read as 0. Shaded cells are not used for synchronous slave reception.
DS39616D-page 238
PIC18F2331/2431/4331/4431
21.0
10-BIT HIGH-SPEED
ANALOG-TO-DIGITAL
CONVERTER (A/D) MODULE
DS39616D-page 239
PIC18F2331/2431/4331/4431
REGISTER 21-1:
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
ACONV
ACSCH
ACMOD1
ACMOD0
GO/DONE
ADON
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
-n = Value at POR
1 = Bit is set
0 = Bit is cleared
x = Bit is unknown
bit 7-6
Unimplemented: Read as 0
bit 5
bit 4
bit 3-2
bit 1
bit 0
Note 1:
DS39616D-page 240
PIC18F2331/2431/4331/4431
REGISTER 21-2:
R/W-0
R/W-0
U-0
R/W-0
R-0
R-0
R-0
R-0
VCFG1
VCFG0
FIFOEN
BFEMT
BFOVL
ADPNT1
ADPNT0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
-n = Value at POR
1 = Bit is set
0 = Bit is cleared
x = Bit is unknown
bit 7-6
bit 5
Unimplemented: Read as 0
bit 4
bit 3
bit 2
bit 1-0
DS39616D-page 241
PIC18F2331/2431/4331/4431
REGISTER 21-3:
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
ADFM
ACQT3
ACQT2
ACQT1
ACQT0
ADCS2
ADCS1
ADCS0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
-n = Value at POR
1 = Bit is set
0 = Bit is cleared
x = Bit is unknown
bit 7
bit 6-3
bit 2-0
Note 1:
If the A/D RC clock source is selected, a delay of one TCY (instruction cycle) is added before the A/D clock
starts. This allows the SLEEP instruction to be executed before starting a conversion.
DS39616D-page 242
PIC18F2331/2431/4331/4431
REGISTER 21-4:
R/W-0
R/W-0
ADRS1
U-0
ADRS0
R/W-0
SSRC4
(1)
R/W-0
SSRC3
(1)
R/W-0
SSRC2
(1)
R/W-0
SSRC1
(1)
R/W-0
SSRC0(1)
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
-n = Value at POR
1 = Bit is set
0 = Bit is cleared
x = Bit is unknown
bit 7-6
ADRS<1:0>: A/D Result Buffer Depth Interrupt Select Control for Continuous Loop Mode bits
The ADRS bits are ignored in Single-Shot mode.
00 = Interrupt is generated when each word is written to the buffer
01 = Interrupt is generated when the 2nd and 4th words are written to the buffer
10 = Interrupt is generated when the 4th word is written to the buffer
11 = Unimplemented
bit 5
Unimplemented: Read as 0
bit 4-0
Note 1:
The SSRC<4:0> bits can be set such that any of the triggers will start a conversion (e.g., SSRC<4:0> = 00101
will trigger the A/D conversion sequence when RC3/INT0 or Input Capture 1 event occurs).
DS39616D-page 243
PIC18F2331/2431/4331/4431
REGISTER 21-5:
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
GDSEL1
GDSEL0
GBSEL1
GBSEL0
GCSEL1
GCSEL0
GASEL1
GASEL0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
-n = Value at POR
1 = Bit is set
0 = Bit is cleared
bit 7-6
bit 5-4
bit 3-2
bit 1-0
Note 1:
x = Bit is unknown
DS39616D-page 244
PIC18F2331/2431/4331/4431
REGISTER 21-6:
R/W-1
ANS7
R/W-1
(2)
R/W-1
(2)
ANS6
ANS5
(2)
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
ANS4
ANS3
ANS2
ANS1
ANS0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
-n = Value at POR
1 = Bit is set
0 = Bit is cleared
bit 7-0
x = Bit is unknown
Note 1:
2:
Setting a pin to an analog input disables the digital input buffer. The corresponding TRIS bit should be set
for an input and cleared for an output (analog or digital). The ANSx bits directly correspond to the ANx pins
(e.g., ANS0 = AN0, ANS1 = AN1, etc.). Unused ANSx bits are read as 0.
ANS7 through ANS5 are available only on PIC18F4331/4431 devices.
REGISTER 21-7:
U-0
U-0
U-0
U-0
U-0
U-0
U-0
R/W-1
ANS8(2)
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
-n = Value at POR
1 = Bit is set
0 = Bit is cleared
bit 7-1
Unimplemented: Read as 0
bit 0
Note 1:
2:
x = Bit is unknown
Setting a pin to an analog input disables the digital input buffer. The corresponding TRIS bit should be set
for an input and cleared for an output (analog or digital). The ANSx bits directly correspond to the ANx pins
(e.g., ANS8 = AN8, ANS9 = AN9, etc.). Unused ANSx bits are read as 0.
ANS8 is available only on PIC18F4331/4431 devices.
DS39616D-page 245
PIC18F2331/2431/4331/4431
The A/D channels are grouped into four sets of 2 or
3 channels. For the PIC18F2331/2431 devices, AN0
and AN4 are in Group A, AN1 is in Group B, AN2 is in
Group C and AN3 is in Group D. For the PIC18F4331/
4431 devices, AN0, AN4 and AN8 are in Group A, AN1
and AN5 are in Group B, AN2 and AN6 are in Group C
and AN3 and AN7 are in Group D. The selected channel in each group is selected by configuring the A/D
Channel Select Register, ADCHS.
FIGURE 21-1:
VCFG<1:0>
AVSS(2)
VREF+
VREF-
VREFH
VREFL
ADC
AN0
AN4
Analog
MUX
AN8(1)
ADRESH, ADRESL
10
AN2/VREF-
MUX
AN6(1)
ACMOD<1:0>,
GxSEL<1:0>
+
-
00
01
10
11
1
2
3
4
S/H-1
S/H
ADPNT<1:0>
4x10-Bit FIFO
AVSS
ACONV
ACSCH
ACMODx
AN1
AN5(1)
Analog
MUX
AN3/VREF+
S/H-2
AN7(1)
+
S/H
ACMOD<1:0>,
GxSEL<1:0>
Note 1:
2:
AVSS(2)
Seq.
Cntrl.
DS39616D-page 246
PIC18F2331/2431/4331/4431
21.1
21.1.1
21.1.2
CONVERSION TYPE
TABLE 21-1:
CONVERSION MODE
ACSCH ACMOD<1:0>
Description
00
01
10
11
00
01
10
11
DS39616D-page 247
PIC18F2331/2431/4331/4431
21.1.3
CONVERSION SEQUENCING
21.1.4
1.
2.
3.
4.
5.
RC3/INT0 Pin
Timer5 Overflow
Input Capture 1 (IC1)
CCP2 Compare Match
Power Control PWM Rising Edge
DS39616D-page 248
21.1.5
6.
PIC18F2331/2431/4331/4431
21.2
Note:
21.3
EQUATION 21-1:
TACQ
9 pF
100
1/2 LSb
5V Rss = 6 k
50C (system max.)
0V @ time = 0
ACQUISITION TIME
TAMP + TC + TCOFF
EQUATION 21-2:
VHOLD
or
TC
=
=
=
=
=
DS39616D-page 249
PIC18F2331/2431/4331/4431
EXAMPLE 21-1:
TACQ
TAMP + TC + TCOFF
TAMP
Negligible
TCOFF
Temperature coefficient is only required for temperatures > 25C. Below 25C, TCOFF = 0 s.
TC
TACQ
Note: If the converter module has been in Sleep mode, TAMP is 2.0 s from the time the part exits Sleep mode.
FIGURE 21-2:
Rs
ANx
RIC 1k
CPIN
VAIN
5 pF
Sampling
Switch
VT = 0.6V
VT = 0.6V
SS
RSS
ILEAKAGE
100 nA
CHOLD = 9 pF
VSS
Legend:
Note:
DS39616D-page 250
CPIN
= Input Capacitance
VT
= Threshold Voltage
ILEAKAGE = Leakage Current at the pin due to
various junctions
RIC
= Interconnect Resistance
SS
= Sampling Switch
CHOLD
= Sample/Hold Capacitance (from DAC)
RSS
= Sampling Switch Resistance
VDD
6V
5V
4V
3V
2V
5 6 7 8 9 10 11
Sampling Switch (k)
For VDD < 2.7V and temperatures below 0C, VAIN should be restricted to range: VAIN < VDD/2.
PIC18F2331/2431/4331/4431
21.4
Note:
21.5
The ADCON2 register allows the user to select an acquisition time that occurs each time an A/D conversion is
triggered.
When the GO/DONE bit is set, sampling is stopped and
a conversion begins. The user is responsible for ensuring
the required acquisition time has passed between
selecting the desired input channel and the start of
conversion. This occurs when the ACQT<3:0> bits
(ADCON2<6:3>) remain in their Reset state (0000).
TABLE 21-2:
4:
21.6
2 TOSC
4 TOSC
8 TOSC
16 TOSC
32 TOSC
64 TOSC
Internal RC Oscillator
Internal RC Oscillator/4
Operation
Note 1:
2:
3:
ADCS<2:0>
PIC18LFXX31(4)
000
4.8 MHz
666 kHz
2 TOSC
100
9.6 MHz
1.33 MHz
4 TOSC
8 TOSC
001
19.2 MHz
2.66 MHz
16 TOSC
101
38.4 MHz
5.33 MHz
010
40.0 MHz
10.65 MHz
32 TOSC
64 TOSC
110
40.0 MHz
21.33 MHz
(3)
(1)
RC/4
011
1.00 MHz
1.00 MHz(2)
(3)
(2)
RC
111
4.0 MHz
4.0 MHz(2)
The RC source has a typical TAD time of 2-6 s.
The RC source has a typical TAD time of 0.5-1.5 s.
For device frequencies above 1 MHz, the device must be in Sleep for the entire conversion or the A/D
accuracy may be out of specification unless in Single-Shot mode.
Low-power devices only.
DS39616D-page 251
PIC18F2331/2431/4331/4431
21.7
Operation in Power-Managed
Modes
21.8
DS39616D-page 252
PIC18F2331/2431/4331/4431
21.9
A/D Conversions
FIGURE 21-3:
GO/DONE bit is TAD1 TAD2 TAD3 TAD4 TAD5 TAD6 TAD7 TAD8 TAD9 TAD10 TAD11
set and holding
b6
b3
b2
b8
b9
b4
b5
b7
b0
b1
cap is
disconnected
Conversion Starts
from analog
input
Note 1:
FIGURE 21-4:
TACQT Cycles
1
TAD Cycles
4
Automatic
Acquisition
Time
TAD1 TAD2 TAD3 TAD4 TAD5 TAD6 TAD7 TAD8 TAD9 TAD10 TAD11
b6
b3
b2
b8
b9
b4
b5
b7
b0
b1
Conversion Starts
(Holding capacitor is disconnected)
A/D Triggered
GO/DONE bit cleared on the rising edge of Q1 after the first Q3
following TAD11 and result buffer is loaded.(1)
Note 1:
DS39616D-page 253
PIC18F2331/2431/4331/4431
21.9.1
FIGURE 21-5:
ADFM = 1
2107
0765
0000 00
ADRESH
0000 00
ADRESL
10-Bit Result
Right Justified
EQUATION 21-3:
ADRESH
ADRESL
10-Bit Result
Left Justified
Sequential Mode:
T = (TACQ)A + (TCON)A + [(TACQ)B 12 TAD] + (TCON)B + [(TACQ)C 12 TAD] + (TCON)C + [(TACQ)D 12 TAD] + (TCON)D
Simultaneous Mode:
T = TACQ + (TCON)A + (TCON)B + TACQ + (TCON)C + (TCON)D
DS39616D-page 254
PIC18F2331/2431/4331/4431
TABLE 21-3:
Name
INTCON
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reset Values
on Page:
INT0IE
RBIE
TMR0IF
INT0IF
RBIF
54
PIR1
ADIF
RCIF
TXIF
SSPIF
CCP1IF
TMR2IF
TMR1IF
57
PIE1
ADIE
RCIE
TXIE
SSPIE
CCP1IE
TMR2IE
TMR1IE
57
IPR1
ADIP
RCIP
TXIP
SSPIP
CCP1IP
TMR2IP
TMR1IP
57
PIR2
OSCFIF
EEIF
LVDIF
CCP2IF
57
PIE2
OSCFIE
EEIE
LVDIE
CCP2IE
57
IPR2
OSCFIP
EEIP
LVDIP
CCP2IP
57
ADRESH
56
ADRESL
56
ADCON0
ACONV
ADCON1
VCFG1
VCFG0
FIFOEN
BFEMT
ADCON2
ADFM
ACQT3
ACQT2
ACQT1
ACQT0
SSRC4
SSRC3
GO/DONE
ADON
56
BFOVFL
ADPNT1
ADPNT0
56
ADCS2
ADCS1
ADCS0
56
SSRC2
SSRC1
SSRC0
56
GASEL1
GASEL0
56
ADCON3
ADRS1
ADRS0
ADCHS
GDSEL1
GDSEL0
ANSEL0
ANS7(6)
ANS6(6)
ANS5(6)
ANS4
ANS3
ANS2
ANS1
ANS0
56
ANSEL1
ANS8(5)
56
PORTA
RA7(4)
RA6(4)
RA5
RA4
RA3
RA2
RA1
RA0
TRISA
57
57
PORTE(2)
RE3(1,3)
TRISE(3)
57
57
LATE(3)
Legend:
Note 1:
2:
3:
4:
5:
6:
RA2(3)
RA1(3)
RA0(3)
57
= unimplemented, read as 0. Shaded cells are not used for A/D conversion.
The RE3 port bit is available only as an input pin when the MCLRE bit in the CONFIG3H register is 0.
This register is not implemented on PIC18F2331/2431 devices.
These bits are not implemented on PIC18F2331/2431 devices.
These pins may be configured as port pins depending on the oscillator mode selected.
ANS5 through ANS8 are available only on the PIC18F4331/4431 devices.
Not available on 28-pin devices.
DS39616D-page 255
PIC18F2331/2431/4331/4431
NOTES:
DS39616D-page 256
PIC18F2331/2431/4331/4431
22.0
REGISTER 22-1:
U-0
R-0
IRVST
R/W-0
LVDEN
R/W-0
LVDL3(1)
R/W-1
LVDL2(1)
R/W-0
LVDL1(1)
R/W-1
LVDL0(1)
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
1 = Bit is set
bit 7-6
Unimplemented: Read as 0
bit 5
bit 4
bit 3-0
Note 1:
LVDL<3:0> bit modes, which result in a trip point below the valid operating voltage of the device, are not
tested.
DS39616D-page 257
PIC18F2331/2431/4331/4431
FIGURE 22-1:
VDD
Externally Generated
Trip Point
VDD
LVDCON
Register
LVDEN
LVDIN
16-to-1 MUX
LVDIN
LVDL<3:0>
VDIRMAG
Set
LVDIF
LVDEN
BOREN
DS39616D-page 258
Internal Voltage
Reference
PIC18F2331/2431/4331/4431
22.1
Operation
22.2
LVD Setup
22.3
Current Consumption
DS39616D-page 259
PIC18F2331/2431/4331/4431
22.4
FIGURE 22-2:
CASE 1:
Enable LVD
Internally Generated
Reference Stable
TIRVST
LVDIF cleared in software
CASE 2:
VDD
VLVD
LVDIF
Enable LVD
Internally Generated
Reference Stable
TIRVST
DS39616D-page 260
PIC18F2331/2431/4331/4431
22.5
22.7
22.6
Effects of a Reset
Voltage
FIGURE 22-3:
Applications
VA
VB
TB
Time
TABLE 22-1:
Name
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
LVDCON
IRVST
LVDEN
LVDL3
LVDL2
LVDL1
LVDL0
INTCON
GIE/GIEH
PEIE/GIEL
TMR0IE
INT0IE
RBIE
TMR0IF
INT0IF
RBIF
IPR2
OSCFIP
EEIP
LVDIP
CCP2IP
PIR2
OSCFIF
EEIF
LVDIF
CCP2IF
PIE2
OSCFIE
EEIE
LVDIE
CCP2IE
Legend: = unimplemented, read as 0. Shaded cells are unused by the LVD module.
DS39616D-page 261
PIC18F2331/2431/4331/4431
NOTES:
DS39616D-page 262
PIC18F2331/2431/4331/4431
23.0
23.1
Configuration Bits
DS39616D-page 263
PIC18F2331/2431/4331/4431
TABLE 23-1:
File Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Default/
Unprogrammed
Value
300000h CONFIG1L
---- ----
300001h CONFIG1H
IESO
FCMEN
FOSC3
FOSC2
FOSC1
FOSC0
11-- 1111
BORV0
BOREN
PWRTEN
---- 1111
WDTEN
--11 1111
300002h CONFIG2L
BORV1
300003h CONFIG2H
WINEN
WDTPS3
WDTPS2
300004h CONFIG3L
HPOL
LPOL
T1OSCMX
300006h CONFIG4L
DEBUG
300007h CONFIG4H
300008h CONFIG5L
300009h CONFIG5H
CPD
CPB
30000Ah CONFIG6L
30000Bh CONFIG6H
WRTD
30000Ch CONFIG7L
WDTPS1 WDTPS0
PWMPIN
--11 11--
FLTAMX(1)
1--1 11-1
LVP
STVREN
1--- -1-1
---- ----
CP3(1)
CP2(1)
CP1
CP0
---- 1111
11-- ----
WRT3(1)
WRT2(1)
WRT1
WRT0
---- 1111
WRTB
WRTC
111- ----
EBTR3(1)
EBTR2(1)
EBTR1
EBTR0
---- 1111
30000Dh CONFIG7H
EBTRB
-1-- ----
3FFFFEh DEVID1(2)
DEV2
DEV1
DEV0
REV4
REV3
REV2
REV1
REV0
xxxx xxxx(2)
DEVID2(2)
DEV10
DEV9
DEV8
DEV7
DEV6
DEV5
DEV4
DEV3
0000 0101
3FFFFFh
Legend:
Note 1:
2:
REGISTER 23-1:
R/P-1
R/P-1
U-0
U-0
R/P-1
R/P-1
R/P-1
R/P-1
IESO
FCMEN
FOSC3
FOSC2
FOSC1
FOSC0
bit 7
bit 0
Legend:
R = Readable bit
P = Programmable bit
bit 7
bit 6
bit 5-4
Unimplemented: Read as 0
bit 3-0
DS39616D-page 264
PIC18F2331/2431/4331/4431
REGISTER 23-2:
U-0
U-0
U-0
R/P-1
BORV1
R/P-1
BORV0
R/P-1
R/P-1
(1)
BOREN
bit 7
PWRTEN(1)
bit 0
Legend:
R = Readable bit
P = Programmable bit
Unimplemented: Read as 0
bit 3-2
bit 1
bit 0
Note 1:
Having BOREN = 1 does not automatically override the PWRTEN to 0, nor automatically enables the
Power-up Timer.
DS39616D-page 265
PIC18F2331/2431/4331/4431
REGISTER 23-3:
U-0
U-0
R/P-1
R/P-1
R/P-1
R/P-1
R/P-1
R/P-1
WINEN
WDTPS3
WDTPS2
WDTPS1
WDTPS0
WDTEN
bit 7
bit 0
Legend:
R = Readable bit
P = Programmable bit
bit 7-6
Unimplemented: Read as 0
bit 5
bit 4-1
bit 0
DS39616D-page 266
PIC18F2331/2431/4331/4431
REGISTER 23-4:
U-0
R/P-1
T1OSCMX
R/P-1
HPOL
(1)
R/P-1
LPOL
(1)
R/P-1
(3)
PWMPIN
bit 7
bit 0
Legend:
R = Readable bit
P = Programmable bit
bit 7-6
Unimplemented: Read as 0
bit 5
bit 4
HPOL: High Side Transistors Polarity bit (i.e., Odd PWM Output Polarity Control bit)(1)
1 = PWM1, 3, 5 and 7 are active-high (default)(2)
0 = PWM1, 3, 5 and 7 are active-low(2)
bit 3
LPOL: Low Side Transistors Polarity bit (i.e., Even PWM Output Polarity Control bit)(1)
1 = PWM0, 2, 4 and 6 are active-high (default)(2)
0 = PWM0, 2, 4 and 6 are active-low(2)
bit 2
bit 1-0
Unimplemented: Read as 0
Note 1:
2:
3:
Polarity control bits, HPOL and LPOL, define PWM signal output active and inactive states; PWM states
generated by the Fault inputs or PWM manual override.
PWM6 and PWM7 output channels are only available on PIC18F4331/4431 devices.
When PWMPIN = 0, PWMEN<2:0> = 101 if the device has eight PWM output pins (40 and 44-pin
devices) and PWMEN<2:0> = 100 if the device has six PWM output pins (28-pin devices). PWM output
polarity is defined by HPOL and LPOL.
DS39616D-page 267
PIC18F2331/2431/4331/4431
REGISTER 23-5:
R/P-1
MCLRE(1)
R/P-1
R/P-1
EXCLKMX(1) PWM4MX(1)
R/P-1
R/P-1
SSPMX(1)
FLTAMX(1)
bit 7
bit 0
Legend:
R = Readable bit
P = Programmable bit
bit 7
bit 6-5
Unimplemented: Read as 0
bit 4
bit 3
bit 2
bit 1
Unimplemented: Read as 0
bit 0
Note 1:
DS39616D-page 268
PIC18F2331/2431/4331/4431
REGISTER 23-6:
R/P-1
U-0
U-0
U-0
U-0
R/P-1
U-0
R/P-1
DEBUG
LVP
STVREN
bit 7
bit 0
Legend:
R = Readable bit
P = Programmable bit
bit 7
bit 6-3
Unimplemented: Read as 0
bit 2
bit 1
Unimplemented: Read as 0
bit 0
DS39616D-page 269
PIC18F2331/2431/4331/4431
REGISTER 23-7:
U-0
U-0
U-0
U-0
R/C-1
R/C-1
R/C-1
R/C-1
CP3(1,2)
CP2(1,2)
CP1(2)
CP0(2)
bit 7
bit 0
Legend:
R = Readable bit
C = Clearable bit
Unimplemented: Read as 0
bit 3
bit 2
bit 1
bit 0
Note 1:
2:
REGISTER 23-8:
R/C-1
R/C-1
U-0
U-0
U-0
U-0
U-0
U-0
CPD(1)
CPB(1)
bit 7
bit 0
Legend:
R = Readable bit
C = Clearable bit
bit 6
bit 5-0
Unimplemented: Read as 0
Note 1:
DS39616D-page 270
PIC18F2331/2431/4331/4431
REGISTER 23-9:
U-0
U-0
U-0
R/P-1
WRT3
(1,2)
R/P-1
WRT2
(1,2)
R/P-1
R/P-1
(2)
WRT1
WRT0(2)
bit 7
bit 0
Legend:
R = Readable bit
P = Programmable bit
Unimplemented: Read as 0
bit 3
bit 2
bit 1
bit 0
Note 1:
2:
R/P-1
R-1
U-0
U-0
U-0
U-0
U-0
WRTD(2)
WRTB(2)
WRTC(1,2)
bit 7
bit 0
Legend:
R = Readable bit
P = Programmable bit
bit 7
bit 6
bit 5
bit 4-0
Unimplemented: Read as 0
Note 1:
2:
This bit is read-only in normal execution mode; it can be written only in Program mode.
Refer to Figure 23-5 for block boundary addresses.
DS39616D-page 271
PIC18F2331/2431/4331/4431
REGISTER 23-11: CONFIG7L: CONFIGURATION REGISTER 7 LOW (BYTE ADDRESS 30000Ch)
U-0
U-0
U-0
U-0
R/P-1
EBTR3
(1,2,3)
R/P-1
R/P-1
(1,2,3)
EBTR2
EBTR1
(2,3)
R/P-1
EBTR0(2,3)
bit 7
bit 0
Legend:
R = Readable bit
P = Programmable bit
bit 7-4
Unimplemented: Read as 0
bit 3
bit 2
bit 1
bit 0
Note 1:
2:
3:
R/P-1
U-0
U-0
U-0
U-0
U-0
U-0
EBTRB(1,2)
bit 7
bit 0
Legend:
R = Readable bit
P = Programmable bit
bit 7
Unimplemented: Read as 0
bit 6
bit 5-0
Unimplemented: Read as 0
Note 1:
2:
Enabling the corresponding CPx bit is recommended to protect the block from external read operations.
Refer to Figure 23-5 for block boundary addresses.
DS39616D-page 272
PIC18F2331/2431/4331/4431
REGISTER 23-13: DEVID1: DEVICE ID REGISTER 1 FOR PIC18F2331/2431/4331/4431 DEVICES
R
DEV2
DEV1
DEV0
REV4
REV3
REV2
REV1
REV0
bit 7
bit 0
Legend:
R = Readable bit
P = Programmable bit
bit 7-5
bit 4-0
DEV10(1)
DEV9(1)
DEV8(1)
DEV7(1)
DEV6(1)
DEV5(1)
DEV4(1)
DEV3(1)
bit 7
bit 0
Legend:
R = Readable bit
P = Programmable bit
Note 1:
DS39616D-page 273
PIC18F2331/2431/4331/4431
23.2
FIGURE 23-1:
23.2.1
CONTROL REGISTER
SWDTEN
WDTEN
Enable WDT
INTRC Control
WDT Counter
INTRC Source
Wake-up
from Sleep
125
CLRWDT
All Device Resets
WDTPS<3:0>
Reset
WDT
Reset
WDT
4
Sleep
DS39616D-page 274
PIC18F2331/2431/4331/4431
REGISTER 23-15: WDTCON: WATCHDOG TIMER CONTROL REGISTER
R-0
U-0
U-0
U-0
U-0
U-0
U-0
R/W-0
WDTW
SWDTEN(1)
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
-n = Value at POR
1 = Bit is set
0 = Bit is cleared
bit 7
bit 6-1
Unimplemented: Read as 0
bit 0
Note 1:
If the WDTEN Configuration bit = 1, then WDT is always enabled, irrespective of this control bit. If WDTEN
Configuration bit = 0, then it is possible to turn WDT on/off with this control bit.
TABLE 23-2:
Name
CONFIG2H
RCON
WDTCON
x = Bit is unknown
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
WINEN
WDTPS3
WDTPS2
WDTPS2
WDTPS0
WDTEN
IPEN
RI
TO
PD
POR
BOR
WDTW
SWDTEN
DS39616D-page 275
PIC18F2331/2431/4331/4431
23.3
In all other power-managed modes, Two-Speed Startup is not used. The device will be clocked by the
currently selected clock source until the primary clock
source becomes available. The setting of the IESO
Configuration bit is ignored.
Two-Speed Start-up
23.3.1
While using the INTRC oscillator in Two-Speed Startup, the device still obeys the normal command
sequences for entering power-managed modes,
including serial SLEEP instructions (refer to
Section 4.1.4 Multiple Sleep Commands). In
practice, this means that user code can change the
SCS<1:0> bit settings and issue SLEEP commands
before the OST times out. This would allow an application to briefly wake-up, perform routine housekeeping
tasks and return to Sleep before the device starts to
operate from the primary oscillator.
FIGURE 23-2:
Q2
Q3
Q4
Q2 Q3 Q4 Q1 Q2 Q3 Q4
Q1
INTOSC
Multiplexer
OSC1
TOST(1)
TPLL(1)
PLL Clock
Output
3 4 5 6
Clock Transition
CPU Clock
Peripheral
Clock
Program
Counter
PC
1:
PC + 2
PC + 4
PC + 6
TOST = 1024 TOSC; TPLL = 2 ms (approx). These intervals are not shown to scale.
DS39616D-page 276
PIC18F2331/2431/4331/4431
23.4
FIGURE 23-3:
Peripheral
Clock
INTRC
Source
(32 s)
64
488 Hz
(2.048 ms)
Clock
Failure
Detected
23.4.1
23.4.2
DS39616D-page 277
PIC18F2331/2431/4331/4431
FIGURE 23-4:
Sample Clock
Oscillator
Failure
System
Clock
Output
CM Output
(Q)
Failure
Detected
OSCFIF
CM Test
Note:
23.4.3
CM Test
CM Test
The system clock is normally at a much higher frequency than the sample clock. The relative frequencies in
this example have been chosen for clarity.
FSCM INTERRUPTS IN
POWER-MANAGED MODES
23.4.4
DS39616D-page 278
PIC18F2331/2431/4331/4431
23.5
FIGURE 23-5:
8 Kbytes
(PIC18F2331/4331)
Address
Range
16 Kbytes
(PIC18F2431/4431)
0000h
0FFFh
Boot Block
Address
Range
0000h
01FFh
Boot Block
0200h
0200h
Block 0
Block 0
0FFFh
0FFFh
1000h
1000h
Block 1
Block 1
1FFFh
1FFFh
2000h
CP2, WRT2, EBTR2
Block 2
2FFFh
Unimplemented
Read 0s
3000h
Block 3
3FFFh
TABLE 23-3:
3FFFh
File Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
300008h
CONFIG5L
CP3(1)
CP2(1)
CP1
CP0
300009h
CONFIG5H
CPD
CPB
WRT1
WRT0
EBTR1
EBTR0
30000Ah
CONFIG6L
30000Bh
CONFIG6H
WRTD
WRTB
WRTC
30000Ch
CONFIG7L
30000Dh
CONFIG7H
EBTRB
WRT3
(1)
EBTR3
WRT2
(1)
(1)
(1)
EBTR2
DS39616D-page 279
PIC18F2331/2431/4331/4431
23.5.1
PROGRAM MEMORY
CODE PROTECTION
Note:
FIGURE 23-6:
Register Values
Program Memory
TBLPTR = 0002FFh
PC = 0007FEh
WRTB, EBTRB = 11
WRT0, EBTR0 = 01
TBLWT *
0007FFh
000800h
WRT1, EBTR1 = 11
000FFFh
001000h
PC = 0017FEh
WRT2, EBTR2 = 11
TBLWT *
0017FFh
001800h
WRT3, EBTR3 = 11
001FFFh
Results: All table writes are disabled to Blockn whenever WRTn = 0.
DS39616D-page 280
PIC18F2331/2431/4331/4431
FIGURE 23-7:
Register Values
Program Memory
000000h
0001FFh
000200h
TBLPTR = 0002FFh
PC = 000FFEh
WRTB, EBTRB = 11
WRT0, EBTR0 = 10
0007FFh
000800h
TBLRD *
000FFFh
001000h
WRT1, EBTR1 = 11
WRT2, EBTR2 = 11
0017FFh
001800h
WRT3, EBTR3 = 11
001FFFh
Results: All table reads from external blocks to Blockn are disabled whenever EBTRn = 0.
The TABLAT register returns a value of 0.
FIGURE 23-8:
Register Values
Program Memory
000000h
0001FFh
000200h
TBLPTR = 0002FFh
PC = 0007FEh
WRTB, EBTRB = 11
WRT0, EBTR0 = 10
TBLRD *
0007FFh
000800h
WRT1, EBTR1 = 11
000FFFh
001000h
WRT2, EBTR2 = 11
0017FFh
001800h
WRT3, EBTR3 = 11
001FFFh
DS39616D-page 281
PIC18F2331/2431/4331/4431
23.5.2
DATA EEPROM
CODE PROTECTION
23.5.3
CONFIGURATION REGISTER
PROTECTION
23.6
23.8
In-Circuit Debugger
TABLE 23-4:
23.9
Single-Supply ICSP
Programming
ID Locations
23.7
To use the In-Circuit Debugger function of the microcontroller, the design must implement In-Circuit Serial
Programming connections to MCLR/VPP, VDD, VSS,
RB7 and RB6. This will interface to the In-Circuit
Debugger module available from Microchip or one of
the third party development tool companies.
While programming, using Single-Supply Programming, VDD is applied to the MCLR/VPP pin as in normal
execution mode. To enter Programming mode, VDD is
applied to the PGM pin.
Note 1: High-voltage programming is always
available, regardless of the state of the
LVP bit or the PGM pin, by applying VIHH
to the MCLR pin.
2: When Single-Supply Programming is
enabled, the RB5 pin can no longer be
used as a general purpose I/O pin.
3: When LVP is enabled externally, pull the
PGM pin to VSS to allow normal program
execution.
If Single-Supply ICSP Programming mode will not be
used, the LVP bit can be cleared and RB5/PGM
becomes available as the digital I/O pin RB5. The LVP
bit may be set or cleared only when using standard
high-voltage programming (VIHH applied to the MCLR/
VPP pin). Once LVP has been disabled, only the
standard high-voltage programming is available and
must be used to program the device.
Memory that is not code-protected can be erased using
either a block erase, or erased row by row, then written
at any specified VDD. If code-protected memory is to be
erased, a block erase is required. If a block erase is to
be performed when using Single-Supply Programming,
the device must be supplied with VDD of 4.5V to 5.5V.
DEBUGGER RESOURCES
I/O pins:
RB6, RB7
Stack:
2 levels
Program Memory:
<1 Kbytes
Data Memory:
16 bytes
DS39616D-page 282
PIC18F2331/2431/4331/4431
24.0
Byte-oriented operations
Bit-oriented operations
Literal operations
Control operations
24.1
Read-Modify-Write Operations
DS39616D-page 283
PIC18F2331/2431/4331/4431
TABLE 24-1:
Field
Description
bbb
BSR
dest
Destination either the WREG register or the specified register file locations.
fs
12-bit register file address (0x000 to 0xFFF). This is the source address.
fd
12-bit register file address (0x000 to 0xFFF). This is the destination address.
Literal field, constant data or label (may be either an 8-bit, 12-bit or a 20-bit value).
label
Label name.
mm
The mode of the TBLPTR register for the table read and table write instructions.
Only used with table read and table write instructions:
*+
*-
+*
n
The relative address (2s complement number) for relative branch instructions, or the direct address for
Call/Branch and Return instructions.
PRODH
PRODL
Unused or Unchanged.
WREG
TBLPTR
TABLAT
TOS
Top-of-Stack.
PC
Program Counter.
PCL
PCH
PCLATH
PCLATU
GIE
WDT
Watchdog Timer.
TO
Time-out bit.
PD
Power-Down bit.
C, DC, Z, OV, N
Optional.
Contents.
Assigned to.
< >
italics
DS39616D-page 284
PIC18F2331/2431/4331/4431
FIGURE 24-1:
10
OPCODE
Example Instruction
8 7
f (FILE #)
ADDWF MYREG, W, B
12 11
OPCODE
15
f (Source FILE #)
12 11
f (Destination FILE #)
1111
12 11
9 8 7
OPCODE b (BIT #) a
f (FILE #)
OPCODE
k (literal)
MOVLW 0x7F
8 7
OPCODE
15
n<7:0> (literal)
12 11
GOTO Label
0
n<19:8> (literal)
1111
8 7
S
OPCODE
15
0
n<7:0> (literal)
12 11
CALL MYFUNC
0
n<19:8> (literal)
S = Fast bit
15
11 10
OPCODE
15
0
n<10:0> (literal)
8 7
OPCODE
BRA MYFUNC
0
n<7:0> (literal)
BC MYFUNC
DS39616D-page 285
PIC18F2331/2431/4331/4431
TABLE 24-2:
Mnemonic,
Operands
Cycles
MSb
LSb
Status
Affected
Notes
f, d, a
f, d, a
f, d, a
f, a
f, d, a
f, a
f, a
f, a
f, d, a
f, d, a
f, d, a
f, d, a
f, d, a
f, d, a
f, d, a
f, d, a
f s, f d
MOVWF
MULWF
NEGF
RLCF
RLNCF
RRCF
RRNCF
SETF
SUBFWB
f, a
f, a
f, a
f, d, a
f, d, a
f, d, a
f, d, a
f, a
f, d, a
SUBWF
SUBWFB
f, d, a
f, d, a
SWAPF
TSTFSZ
XORWF
f, d, a
f, a
f, d, a
1
1
1
1
1
1 (2 or 3)
1 (2 or 3)
1 (2 or 3)
1
1 (2 or 3)
1 (2 or 3)
1
1 (2 or 3)
1 (2 or 3)
1
1
2
C, DC, Z, OV, N
C, DC, Z, OV, N
Z, N
Z
Z, N
None
None
None
C, DC, Z, OV, N
None
None
C, DC, Z, OV, N
None
None
Z, N
Z, N
None
1, 2
1, 2
1,2
2
1, 2
4
4
1, 2
1, 2, 3, 4
1, 2, 3, 4
1, 2
1, 2, 3, 4
4
1, 2
1, 2
1
1
1
1
1
1
1
1
1
1
0010
0010
0001
0110
0001
0110
0110
0110
0000
0010
0100
0010
0011
0100
0001
0101
1100
1111
0110
0000
0110
0011
0100
0011
0100
0110
0101
01da
00da
01da
101a
11da
001a
010a
000a
01da
11da
11da
10da
11da
10da
00da
00da
ffff
ffff
111a
001a
110a
01da
01da
00da
00da
100a
01da
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
1
1
0101 11da
0101 10da
ffff
ffff
1
0011 10da
1 (2 or 3) 0110 011a
1
0001 10da
ffff
ffff
ffff
ffff None
ffff None
ffff Z, N
4
1, 2
1
1
1 (2 or 3)
1 (2 or 3)
1
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
None
None
None
None
None
1, 2
1, 2
3, 4
3, 4
1, 2
None
None
C, DC, Z, OV, N
C, Z, N
Z, N
C, Z, N
Z, N
None
C, DC, Z, OV, N
1, 2
1, 2
1, 2
1, 2
2:
3:
4:
5:
f, b, a
f, b, a
f, b, a
f, b, a
f, b, a
Bit Clear f
Bit Set f
Bit Test f, Skip if Clear
Bit Test f, Skip if Set
Bit Toggle f
1001
1000
1011
1010
0111
bbba
bbba
bbba
bbba
bbba
When a PORT register is modified as a function of itself (e.g., MOVF PORTB, 1, 0), the value used will be that
value present on the pins themselves. For example, if the data latch is 1 for a pin configured as an input and is
driven low by an external device, the data will be written back with a 0.
If this instruction is executed on the TMR0 register (and, where applicable, d = 1), the prescaler will be cleared if
assigned.
If the Program Counter (PC) is modified or a conditional test is true, the instruction requires two cycles. The
second cycle is executed as a NOP.
Some instructions are 2-word instructions. The second word of these instructions will be executed as a NOP
unless the first word of the instruction retrieves the information embedded in these 16 bits. This ensures that all
program memory locations have a valid instruction.
If the table write starts the write cycle to internal memory, the write will continue until terminated.
DS39616D-page 286
PIC18F2331/2431/4331/4431
TABLE 24-2:
Mnemonic,
Operands
Description
Cycles
MSb
LSb
Status
Affected
Notes
CONTROL OPERATIONS
BC
BN
BNC
BNN
BNOV
BNZ
BOV
BRA
BZ
CALL
n
n
n
n
n
n
n
n
n
n, s
CLRWDT
DAW
GOTO
NOP
NOP
POP
PUSH
RCALL
RESET
RETFIE
RETLW
RETURN
SLEEP
Note 1:
2:
3:
4:
5:
1 (2)
1 (2)
1 (2)
1 (2)
1 (2)
2
1 (2)
1 (2)
1 (2)
2
Branch if Carry
Branch if Negative
Branch if Not Carry
Branch if Not Negative
Branch if Not Overflow
Branch if Not Zero
Branch if Overflow
Branch Unconditionally
Branch if Zero
Call Subroutine 1st word
2nd word
Clear Watchdog Timer
Decimal Adjust WREG
Go to Address 1st word
2nd word
No Operation
No Operation
Pop Top of Return Stack (TOS)
Push Top of Return Stack (TOS)
Relative Call
Software Device Reset
Return from Interrupt Enable
k
s
1
1
1
1
2
1
2
1110
1110
1110
1110
1110
1110
1110
1101
1110
1110
1111
0000
0000
1110
1111
0000
1111
0000
0000
1101
0000
0000
0010
0110
0011
0111
0101
0001
0100
0nnn
0000
110s
kkkk
0000
0000
1111
kkkk
0000
xxxx
0000
0000
1nnn
0000
0000
nnnn
nnnn
nnnn
nnnn
nnnn
nnnn
nnnn
nnnn
nnnn
kkkk
kkkk
0000
0000
kkkk
kkkk
0000
xxxx
0000
0000
nnnn
1111
0001
2
2
1
0000 1100
0000 0000
0000 0000
kkkk
0001
0000
1
1
2
nnnn
nnnn
nnnn
nnnn
nnnn
nnnn
nnnn
nnnn
nnnn
kkkk
kkkk
0100
0111
kkkk
kkkk
0000
xxxx
0110
0101
nnnn
1111
000s
None
None
None
None
None
None
None
None
None
None
TO, PD
C, DC
None
None
None
None
None
None
All
GIE/GIEH,
PEIE/GIEL
kkkk None
001s None
0011 TO, PD
When a PORT register is modified as a function of itself (e.g., MOVF PORTB, 1, 0), the value used will be that
value present on the pins themselves. For example, if the data latch is 1 for a pin configured as an input and is
driven low by an external device, the data will be written back with a 0.
If this instruction is executed on the TMR0 register (and, where applicable, d = 1), the prescaler will be cleared if
assigned.
If the Program Counter (PC) is modified or a conditional test is true, the instruction requires two cycles. The
second cycle is executed as a NOP.
Some instructions are 2-word instructions. The second word of these instructions will be executed as a NOP
unless the first word of the instruction retrieves the information embedded in these 16 bits. This ensures that all
program memory locations have a valid instruction.
If the table write starts the write cycle to internal memory, the write will continue until terminated.
DS39616D-page 287
PIC18F2331/2431/4331/4431
TABLE 24-2:
Mnemonic,
Operands
Description
Cycles
MSb
LSb
Status
Affected
Notes
LITERAL OPERATIONS
ADDLW
ANDLW
IORLW
LFSR
k
k
k
f, k
MOVLB
MOVLW
MULLW
RETLW
SUBLW
XORLW
k
k
k
k
k
k
1
1
1
2
1
1
1
2
1
1
0000
0000
0000
1110
1111
0000
0000
0000
0000
0000
0000
1111
1011
1001
1110
0000
0001
1110
1101
1100
1000
1010
kkkk
kkkk
kkkk
00ff
kkkk
0000
kkkk
kkkk
kkkk
kkkk
kkkk
kkkk
kkkk
kkkk
kkkk
kkkk
kkkk
kkkk
kkkk
kkkk
kkkk
kkkk
C, DC, Z, OV, N
Z, N
Z, N
None
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
1000
1001
1010
1011
1100
1101
1110
1111
None
None
None
None
None
None
None
None
None
None
None
None
C, DC, Z, OV, N
Z, N
TBLRD*
TBLRD*+
TBLRD*TBLRD+*
TBLWT*
TBLWT*+
TBLWT*TBLWT+*
Note 1:
2:
3:
4:
5:
When a PORT register is modified as a function of itself (e.g., MOVF PORTB, 1, 0), the value used will be that
value present on the pins themselves. For example, if the data latch is 1 for a pin configured as an input and is
driven low by an external device, the data will be written back with a 0.
If this instruction is executed on the TMR0 register (and, where applicable, d = 1), the prescaler will be cleared if
assigned.
If the Program Counter (PC) is modified or a conditional test is true, the instruction requires two cycles. The
second cycle is executed as a NOP.
Some instructions are 2-word instructions. The second word of these instructions will be executed as a NOP
unless the first word of the instruction retrieves the information embedded in these 16 bits. This ensures that all
program memory locations have a valid instruction.
If the table write starts the write cycle to internal memory, the write will continue until terminated.
DS39616D-page 288
PIC18F2331/2431/4331/4431
24.2
Instruction Set
ADDLW
ADD Literal to W
ADDWF
ADD W to f
Syntax:
[ label ] ADDLW
Syntax:
[ label ] ADDWF
Operands:
0 f 255
d [0,1]
a [0,1]
Operation:
Status Affected:
N, OV, C, DC, Z
Operands:
0 k 255
Operation:
(W) + k W
Status Affected:
N, OV, C, DC, Z
Encoding:
0000
1111
kkkk
kkkk
Description:
Words:
Cycles:
Encoding:
0010
Q1
Q2
Q3
Q4
Words:
Read
literal k
Process
Data
Write to
W
Cycles:
0x15
Before Instruction
W
= 0x10
After Instruction
W =
0x25
ffff
ffff
Decode
ADDLW
01da
Description:
Q Cycle Activity:
Example:
f [,d [,a]]
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
register f
Process
Data
Write to
destination
Example:
ADDWF
Before Instruction
W
=
REG
=
0x17
0xC2
After Instruction
W
=
REG
=
0xD9
0xC2
REG, W
DS39616D-page 289
PIC18F2331/2431/4331/4431
ADDWFC
ANDLW
Syntax:
[ label ] ADDWFC
Syntax:
[ label ] ANDLW
Operands:
0 f 255
d [0,1]
a [0,1]
Operands:
0 k 255
Operation:
(W) .AND. k W
Status Affected:
N, Z
f [,d [,a]]
Operation:
Status Affected:
N, OV, C, DC, Z
Encoding:
0010
Description:
00da
Encoding:
ffff
ffff
Words:
Cycles:
1
Q1
Q2
Q3
Q4
Decode
Read
register f
Process
Data
Write to
destination
ADDWFC
Before Instruction
Carry bit =
REG
=
W
=
1
0x02
0x4D
After Instruction
Carry bit =
REG
=
W
=
0
0x02
0x50
DS39616D-page 290
0000
1011
kkkk
kkkk
Description:
Words:
Cycles:
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read literal
k
Process
Data
Write to
W
Example:
Q Cycle Activity:
Example:
ANDLW
Before Instruction
W
=
After Instruction
W
=
0x5F
0xA3
0x03
REG, W
PIC18F2331/2431/4331/4431
ANDWF
AND W with f
Syntax:
[ label ] ANDWF
Operands:
0 f 255
d [0,1]
a [0,1]
f [,d [,a]]
Operation:
Status Affected:
N, Z
Encoding:
0001
01da
ffff
ffff
Words:
Cycles:
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
register f
Process
Data
Write to
destination
ANDWF
Before Instruction
W
=
REG
=
After Instruction
W
=
REG
=
Branch if Carry
Syntax:
[ label ] BC
Operands:
-128 n 127
Operation:
if Carry bit is 1,
(PC) + 2 + 2n PC
Status Affected:
None
Encoding:
Description:
Example:
BC
REG, W
0x17
0xC2
0x02
0xC2
1110
Description:
0010
nnnn
nnnn
Words:
Cycles:
1(2)
Q Cycle Activity:
If Jump:
Q1
Q2
Q3
Q4
Decode
Read literal
n
Process
Data
Write to
PC
No
operation
No
operation
No
operation
No
operation
If No Jump:
Q1
Q2
Q3
Q4
Decode
Read literal
n
Process
Data
No
operation
Example:
HERE
BC
JUMP
Before Instruction
PC
address (HERE)
After Instruction
If Carry
PC
If Carry
PC
=
=
=
=
1;
address (JUMP)
0;
address (HERE + 2)
DS39616D-page 291
PIC18F2331/2431/4331/4431
BCF
Bit Clear f
Syntax:
[ label ] BCF
Operands:
0 f 255
0b7
a [0,1]
Operation:
0 f<b>
Status Affected:
None
Encoding:
1001
f,b[,a]
bbba
ffff
ffff
Words:
Cycles:
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
register f
Process
Data
Write
register f
BCF
Before Instruction
FLAG_REG = 0xC7
After Instruction
FLAG_REG = 0x47
Branch if Negative
Syntax:
[ label ] BN
Operands:
-128 n 127
Operation:
if Negative bit is 1,
(PC) + 2 + 2n PC
Status Affected:
None
Encoding:
Description:
Example:
BN
FLAG_REG, 7
1110
Description:
0110
nnnn
nnnn
Words:
Cycles:
1(2)
Q Cycle Activity:
If Jump:
Q1
Q2
Q3
Q4
Decode
Read literal
n
Process
Data
Write to
PC
No
operation
No
operation
No
operation
No
operation
If No Jump:
Q1
Q2
Q3
Q4
Decode
Read literal
n
Process
Data
No
operation
Example:
DS39616D-page 292
HERE
BN
Jump
Before Instruction
PC
address (HERE)
After Instruction
If Negative
PC
If Negative
PC
=
=
=
=
1;
address (Jump)
0;
address (HERE + 2)
PIC18F2331/2431/4331/4431
BNC
BNN
Syntax:
[ label ] BNC
Syntax:
[ label ] BNN
Operands:
-128 n 127
Operands:
-128 n 127
Operation:
if Carry bit is 0,
(PC) + 2 + 2n PC
Operation:
if Negative bit is 0,
(PC) + 2 + 2n PC
Status Affected:
None
Status Affected:
None
Encoding:
1110
Description:
0011
nnnn
nnnn
Encoding:
1110
Description:
Words:
Words:
Cycles:
1(2)
Cycles:
1(2)
Q Cycle Activity:
If Jump:
0111
nnnn
nnnn
Q Cycle Activity:
If Jump:
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Decode
Read literal
n
Process
Data
Write to
PC
Decode
Read literal
n
Process
Data
Write to
PC
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Decode
Read literal
n
Process
Data
No
operation
Decode
Read literal
n
Process
Data
No
operation
If No Jump:
If No Jump:
Example:
HERE
Before Instruction
PC
After Instruction
If Carry
PC
If Carry
PC
=
=
=
=
=
BNC
Jump
Example:
HERE
BNN
Jump
address (HERE)
Before Instruction
PC
address (HERE)
0;
address (Jump)
1;
address (HERE + 2)
After Instruction
If Negative
PC
If Negative
PC
=
=
=
=
0;
address (Jump)
1;
address (HERE + 2)
DS39616D-page 293
PIC18F2331/2431/4331/4431
BNOV
BNZ
Syntax:
[ label ] BNOV
Syntax:
[ label ] BNZ
Operands:
-128 n 127
Operands:
-128 n 127
Operation:
if Overflow bit is 0,
(PC) + 2 + 2n PC
Operation:
if Zero bit is 0,
(PC) + 2 + 2n PC
Status Affected:
None
Status Affected:
None
Encoding:
1110
Description:
0101
nnnn
nnnn
Encoding:
1110
Description:
Words:
Words:
Cycles:
1(2)
Cycles:
1(2)
Q Cycle Activity:
If Jump:
0001
nnnn
nnnn
Q Cycle Activity:
If Jump:
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Decode
Read literal
n
Process
Data
Write to
PC
Decode
Read literal
n
Process
Data
Write to PC
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Decode
Read literal
n
Process
Data
No
operation
Decode
Read literal
n
Process
Data
No
operation
If No Jump:
If No Jump:
Example:
HERE
Before Instruction
PC
After Instruction
If Overflow
PC
If Overflow
PC
DS39616D-page 294
=
=
=
=
=
BNOV Jump
Example:
HERE
BNZ
Jump
address (HERE)
Before Instruction
PC
address (HERE)
0;
address (Jump)
1;
address (HERE + 2)
After Instruction
If Zero
PC
If Zero
PC
=
=
=
=
0;
address (Jump)
1;
address (HERE + 2)
PIC18F2331/2431/4331/4431
BRA
Unconditional Branch
BSF
Syntax:
[ label ] BRA
Syntax:
[ label ] BSF
Operands:
-1024 n 1023
Operands:
0 f 255
0b7
a [0,1]
Operation:
(PC) + 2 + 2n PC
Status Affected:
None
Encoding:
1101
Description:
0nnn
nnnn
nnnn
Words:
Cycles:
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read literal
n
Process
Data
Write to
PC
No
operation
No
operation
No
operation
No
operation
HERE
BRA
Example:
Bit Set f
Operation:
1 f<b>
Status Affected:
None
Encoding:
Before Instruction
PC
address (HERE)
After Instruction
PC
address (Jump)
bbba
ffff
ffff
Description:
Words:
Cycles:
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
register f
Process
Data
Write
register f
Example:
Jump
1000
f,b[,a]
BSF
FLAG_REG, 7
Before Instruction
FLAG_REG
0x0A
After Instruction
FLAG_REG
0x8A
DS39616D-page 295
PIC18F2331/2431/4331/4431
BTFSC
BTFSS
Syntax:
Syntax:
Operands:
0 f 255
0b7
a [0,1]
Operands:
0 f 255
0b<7
a [0,1]
Operation:
skip if (f<b>) = 0
Operation:
skip if (f<b>) = 1
Status Affected:
None
Status Affected:
None
Encoding:
1011
bbba
ffff
ffff
Encoding:
1010
bbba
ffff
ffff
Description:
Description:
Words:
Words:
Cycles:
1(2)
Note:
Cycles:
1(2)
Note:
Q Cycle Activity:
Q Cycle Activity:
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Decode
Read
register f
Process
Data
No
operation
Decode
Read
register f
Process
Data
No
operation
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
If skip:
If skip:
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
Example:
HERE
FALSE
TRUE
BTFSC
:
:
FLAG, 1
Example:
HERE
FALSE
TRUE
BTFSS
:
:
FLAG, 1
Before Instruction
PC
address (HERE)
Before Instruction
PC
address (HERE)
After Instruction
If FLAG<1>
PC
If FLAG<1>
PC
=
=
=
=
0;
address (TRUE)
1;
address (FALSE)
After Instruction
If FLAG<1>
PC
If FLAG<1>
PC
=
=
=
=
0;
address (FALSE)
1;
address (TRUE)
DS39616D-page 296
PIC18F2331/2431/4331/4431
BTG
Bit Toggle f
BOV
Branch if Overflow
Syntax:
Syntax:
[ label ] BOV
Operands:
0 f 255
0b<7
a [0,1]
Operands:
-128 n 127
Operation:
if Overflow bit is 1,
(PC) + 2 + 2n PC
Status Affected:
None
Operation:
(f<b>) f<b>
Status Affected:
None
Encoding:
Encoding:
0111
bbba
ffff
ffff
Description:
Words:
Cycles:
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
register f
Process
Data
Write
register f
Example:
BTG
PORTC,
Before Instruction:
PORTC =
0111 0101 [0x75]
After Instruction:
PORTC =
1110
Description:
0100
nnnn
nnnn
Words:
Cycles:
1(2)
Q Cycle Activity:
If Jump:
Q1
Q2
Q3
Q4
Decode
Read literal
n
Process
Data
Write to
PC
No
operation
No
operation
No
operation
No
operation
If No Jump:
Q1
Q2
Q3
Q4
Decode
Read literal
n
Process
Data
No
operation
Example:
HERE
BOV
JUMP
Before Instruction
PC
address (HERE)
After Instruction
If Overflow
PC
If Overflow
PC
=
=
=
=
1;
address (JUMP)
0;
address (HERE + 2)
DS39616D-page 297
PIC18F2331/2431/4331/4431
BZ
Branch if Zero
CALL
Syntax:
[ label ] BZ
Syntax:
Operands:
-128 n 127
Operands:
Operation:
if Zero bit is 1,
(PC) + 2 + 2n PC
0 k 1048575
s [0,1]
Operation:
(PC) + 4 TOS,
k PC<20:1>;
if s = 1:
(W) WS,
(STATUS) STATUSS,
(BSR) BSRS
Status Affected:
None
Status Affected:
Subroutine Call
None
Encoding:
1110
Description:
0000
nnnn
nnnn
Words:
Cycles:
1(2)
Encoding:
1st word (k<7:0>)
2nd word(k<19:8>)
1110
1111
Q1
Q2
Q3
Q4
Read literal
n
Process
Data
Write to
PC
No
operation
No
operation
No
operation
No
operation
If No Jump:
Q1
Q2
Q3
Q4
Decode
Read literal
n
Process
Data
No
operation
Example:
HERE
BZ
Words:
Cycles:
address (HERE)
After Instruction
If Zero
PC
If Zero
PC
=
=
=
=
1;
address (Jump)
0;
address (HERE + 2)
DS39616D-page 298
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read literal
k<7:0>,
Push PC to
Stack
Read literal
k<19:8>,
Write to PC
No
operation
No
operation
No
operation
No
operation
Jump
Before Instruction
PC
kkkk0
kkkk8
Description:
Q Cycle Activity:
If Jump:
Decode
k7kkk
kkkk
110s
k19kkk
Example:
HERE
CALL
THERE,FAST
Before Instruction
PC
=
address (HERE)
After Instruction
PC
=
TOS
=
WS
=
BSRS
=
STATUSS =
address (THERE)
address (HERE + 4)
W
BSR
STATUS
PIC18F2331/2431/4331/4431
CLRF
Clear f
Syntax:
[ label ] CLRF
Operands:
0 f 255
a [0,1]
Operation:
000h f,
1Z
Status Affected:
Encoding:
0110
f [,a]
101a
ffff
ffff
CLRWDT
Syntax:
[ label ] CLRWDT
Operands:
None
Operation:
000h WDT,
000h WDT postscaler,
1 TO,
1 PD
Status Affected:
TO, PD
Clears the contents of the specified register. If a is 0, the Access Bank will be
selected, overriding the BSR value. If
a = 1, then the bank will be selected as
per the BSR value.
Encoding:
Description:
Words:
Words:
Cycles:
Cycles:
Description:
Q Cycle Activity:
0000
0000
0000
0100
Q Cycle Activity:
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Decode
Read
register f
Process
Data
Write
register f
Decode
No
operation
Process
Data
No
operation
Example:
CLRF
FLAG_REG
Before Instruction
FLAG_REG
0x5A
After Instruction
FLAG_REG
0x00
Example:
CLRWDT
Before Instruction
WDT Counter
After Instruction
WDT Counter
WDT Postscaler
TO
PD
=
=
=
=
0x00
0
1
1
DS39616D-page 299
PIC18F2331/2431/4331/4431
COMF
Complement f
Syntax:
[ label ] COMF
Operands:
0 f 255
d [0,1]
a [0,1]
Operation:
(f) dest
Status Affected:
N, Z
Encoding:
0001
Description:
CPFSEQ
f [,d [,a]]
11da
ffff
ffff
Words:
Cycles:
Syntax:
[ label ] CPFSEQ
Operands:
0 f 255
a [0,1]
Operation:
(f) (W),
skip if (f) = (W)
(unsigned comparison)
Status Affected:
None
Encoding:
0110
Description:
Q Cycle Activity:
Q1
Q2
Q3
Q4
Words:
Read
register f
Process
Data
Write to
destination
Cycles:
1(2)
Note:
COMF
Before Instruction
REG
=
After Instruction
REG
=
W
=
ffff
ffff
Decode
Example:
001a
f [,a]
REG, W
Q Cycle Activity:
0x13
0x13
0xEC
Q1
Q2
Q3
Q4
Decode
Read
register f
Process
Data
No
operation
If skip:
Q1
Q2
Q3
Q4
No
operation
No
operation
No
operation
No
operation
Q2
Q3
Q4
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
Example:
DS39616D-page 300
HERE
NEQUAL
EQUAL
CPFSEQ REG
:
:
Before Instruction
PC Address
W
REG
=
=
=
HERE
?
?
After Instruction
If REG
PC
If REG
PC
=
=
W;
Address (EQUAL)
W;
Address (NEQUAL)
PIC18F2331/2431/4331/4431
CPFSGT
CPFSLT
Syntax:
[ label ] CPFSGT
Syntax:
[ label ] CPFSLT
Operands:
0 f 255
a [0,1]
Operands:
0 f 255
a [0,1]
Operation:
(f) W),
skip if (f) > (W)
(unsigned comparison)
Operation:
(f) W),
skip if (f) < (W)
(unsigned comparison)
Status Affected:
None
Status Affected:
None
Encoding:
0110
010a
f [,a]
ffff
ffff
Description:
Words:
Cycles:
1(2)
Note:
Encoding:
Q2
Q3
Q4
Decode
Read
register f
Process
Data
No
operation
Q1
Q2
Q3
Q4
No
operation
No
operation
No
operation
No
operation
Cycles:
1(2)
Note:
Q3
Q4
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
HERE
NGREATER
GREATER
CPFSGT REG
:
:
Before Instruction
PC
W
=
=
Address (HERE)
?
After Instruction
If REG
PC
If REG
PC
W;
Address (GREATER)
W;
Address (NGREATER)
ffff
ffff
Q1
Q2
Q3
Q4
Decode
Read
register f
Process
Data
No
operation
If skip:
Q1
Q2
Q3
Q4
No
operation
No
operation
No
operation
No
operation
Q2
Q3
Q4
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
HERE
NLESS
LESS
CPFSLT REG
:
:
Example:
Example:
000a
Q Cycle Activity:
f [,a]
Words:
If skip:
Q1
0110
Description:
Q Cycle Activity:
Q1
Before Instruction
PC
W
=
=
Address (HERE)
?
After Instruction
If REG
PC
If REG
PC
<
=
W;
Address (LESS)
W;
Address (NLESS)
DS39616D-page 301
PIC18F2331/2431/4331/4431
DAW
DECF
Syntax:
[ label ] DAW
Syntax:
Operands:
None
Operands:
Operation:
0 f 255
d [0,1]
a [0,1]
Operation:
(f) 1 dest
Status Affected:
C, DC, N, OV, Z
Encoding:
If [W<7:4> 9] or [C = 1] then,
(W<7:4>) + 6 W<7:4>;
else,
(W<7:4>) W<7:4>
Status Affected:
Decrement f
0000
0000
Description:
0000
0000
Words:
Cycles:
Cycles:
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
register f
Process
Data
Write to
destination
Example:
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
register W
Process
Data
Write
W
Example 1:
DAW
Before Instruction
W
=
C
=
DC
=
0xA5
0
0
After Instruction
W
=
C
=
DC
=
0x05
1
0
ffff
Words:
0111
ffff
C, DC
Encoding:
01da
Description:
DECF
Before Instruction
CNT
=
Z
=
0x01
0
After Instruction
CNT
=
Z
=
0x00
1
CNT,
Example 2:
Before Instruction
W
=
C
=
DC
=
0xCE
0
0
After Instruction
W
=
C
=
DC
=
0x34
1
0
DS39616D-page 302
PIC18F2331/2431/4331/4431
DECFSZ
Decrement f, Skip if 0
DCFSNZ
Syntax:
Syntax:
[ label ] DCFSNZ
Operands:
0 f 255
d [0,1]
a [0,1]
Operands:
0 f 255
d [0,1]
a [0,1]
Operation:
(f) 1 dest,
skip if result = 0
Operation:
(f) 1 dest,
skip if result 0
Status Affected:
None
Status Affected:
None
Encoding:
0010
Description:
11da
ffff
ffff
Encoding:
0100
Description:
Words:
Words:
Cycles:
1(2)
Note: 3 cycles if skip and followed
by a 2-word instruction.
Cycles:
1(2)
Note:
Q Cycle Activity:
11da
f [,d [,a]]
ffff
ffff
Q Cycle Activity:
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Decode
Read
register f
Process
Data
Write to
destination
Decode
Read
register f
Process
Data
Write to
destination
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
If skip:
If skip:
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
Example:
HERE
DECFSZ
GOTO
CNT
LOOP
Example:
CONTINUE
Before Instruction
PC
=
After Instruction
CNT
=
If CNT
=
PC =
If CNT
PC =
HERE
ZERO
NZERO
DCFSNZ
:
:
TEMP
Address (HERE)
Before Instruction
TEMP
CNT 1
0;
Address (CONTINUE)
0;
Address (HERE + 2)
After Instruction
TEMP
If TEMP
PC
If TEMP
PC
=
=
=
TEMP 1,
0;
Address (ZERO)
0;
Address (NZERO)
DS39616D-page 303
PIC18F2331/2431/4331/4431
GOTO
Unconditional Branch
INCF
Syntax:
[ label ]
Syntax:
[ label ]
Operands:
0 k 1048575
Operands:
Operation:
k PC<20:1>
Status Affected:
None
0 f 255
d [0,1]
a [0,1]
Operation:
(f) + 1 dest
Status Affected:
C, DC, N, OV, Z
Encoding:
1st word (k<7:0>)
2nd word(k<19:8>)
1110
1111
GOTO k
1111
k19kkk
k7kkk
kkkk
kkkk0
kkkk8
Description:
Words:
Cycles:
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read literal
k<7:0>,
No
operation
Read literal
k<19:8>,
Write to PC
No
operation
No
operation
No
operation
Increment f
Encoding:
0010
GOTO THERE
After Instruction
PC =
Address (THERE)
DS39616D-page 304
f [,d [,a]]
10da
ffff
ffff
Description:
Words:
Cycles:
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
register f
Process
Data
Write to
destination
No
operation
Example:
Example:
INCF
INCF
Before Instruction
CNT
=
Z
=
C
=
DC
=
0xFF
0
?
?
After Instruction
CNT
=
Z
=
C
=
DC
=
0x00
1
1
1
CNT,
PIC18F2331/2431/4331/4431
INCFSZ
Increment f, Skip if 0
INFSNZ
Syntax:
[ label ]
Syntax:
[ label ]
Operands:
0 f 255
d [0,1]
a [0,1]
Operands:
0 f 255
d [0,1]
a [0,1]
Operation:
(f) + 1 dest,
skip if result = 0
Operation:
(f) + 1 dest,
skip if result 0
Status Affected:
None
Status Affected:
None
Encoding:
0011
Description:
INCFSZ
f [,d [,a]]
11da
ffff
ffff
Encoding:
0100
Description:
Words:
Words:
Cycles:
1(2)
Note: 3 cycles if skip and followed
by a 2-word instruction.
Cycles:
1(2)
Note:
Q Cycle Activity:
INFSNZ
f [,d [,a]]
10da
ffff
ffff
Q Cycle Activity:
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Decode
Read
register f
Process
Data
Write to
destination
Decode
Read
register f
Process
Data
Write to
destination
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
If skip:
If skip:
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
Example:
HERE
NZERO
ZERO
Before Instruction
PC
=
After Instruction
CNT
=
If CNT
=
PC
=
If CNT
PC
=
INCFSZ
:
:
CNT
Example:
HERE
ZERO
NZERO
INFSNZ
REG
Address (HERE)
Before Instruction
PC
=
Address (HERE)
CNT + 1
0;
Address (ZERO)
0;
Address (NZERO)
After Instruction
REG
=
If REG
PC
=
If REG
=
PC
=
REG + 1
0;
Address (NZERO)
0;
Address (ZERO)
DS39616D-page 305
PIC18F2331/2431/4331/4431
IORLW
IORWF
Syntax:
[ label ]
Syntax:
[ label ]
Operands:
0 k 255
Operands:
Operation:
(W) .OR. k W
Status Affected:
N, Z
0 f 255
d [0,1]
a [0,1]
Operation:
Status Affected:
N, Z
Encoding:
0000
Description:
IORLW k
1001
kkkk
kkkk
Words:
Cycles:
Inclusive OR W with f
Encoding:
0001
Q1
Q2
Q3
Q4
Read
literal k
Process
Data
Write to
W
Example:
IORLW
Before Instruction
W
=
0x9A
After Instruction
W
=
0xBF
0x35
00da
ffff
ffff
Words:
Cycles:
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
register f
Process
Data
Write to
destination
Example:
DS39616D-page 306
f [,d [,a]]
Description:
Q Cycle Activity:
Decode
IORWF
IORWF
Before Instruction
RESULT =
W
=
0x13
0x91
After Instruction
RESULT =
W
=
0x13
0x93
RESULT, W
PIC18F2331/2431/4331/4431
LFSR
Load FSR
MOVF
Syntax:
[ label ]
Syntax:
[ label ]
Operands:
0f2
0 k 4095
Operands:
Operation:
k FSRf
0 f 255
d [0,1]
a [0,1]
Status Affected:
None
Operation:
f dest
Status Affected:
N, Z
Encoding:
LFSR f,k
1110
1111
1110
0000
00ff
k7kkk
k11kkk
kkkk
Description:
Words:
Cycles:
Move f
Encoding:
0101
Q1
Q2
Q3
Q4
Read literal
k MSB
Process
Data
Write
literal k
MSB to
FSRfH
Decode
Read literal
k LSB
Process
Data
Write literal
k to FSRfL
Example:
After Instruction
FSR2H
FSR2L
LFSR 2, 0x3AB
=
=
0x03
0xAB
00da
ffff
ffff
Words:
Cycles:
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
register f
Process
Data
Write
W
Example:
f [,d [,a]]
Description:
Q Cycle Activity:
Decode
MOVF
MOVF
REG, W
Before Instruction
REG
W
=
=
0x22
0xFF
After Instruction
REG
W
=
=
0x22
0x22
DS39616D-page 307
PIC18F2331/2431/4331/4431
MOVFF
Move f to f
MOVLB
Syntax:
[ label ]
Operands:
0 fs 4095
0 fd 4095
Operation:
(fs) fd
Status Affected:
None
Encoding:
Encoding:
1st word (source)
2nd word (destin.)
MOVFF fs,fd
1100
1111
Description:
ffff
ffff
ffff
ffff
ffffs
ffffd
Words:
Cycles:
2 (3)
Syntax:
[ label ]
Operands:
0 k 255
MOVLB k
Operation:
k BSR
Status Affected:
None
0000
0001
0000
kkkk
Description:
Words:
Cycles:
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read literal
k
Process
Data
Write
literal k to
BSR
Example:
MOVLB
Before Instruction
BSR register
0x02
After Instruction
BSR register
0x05
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
register f
(src)
Process
Data
No
operation
Decode
No
operation
No
operation
Write
register f
(dest)
No dummy
read
Example:
MOVFF
REG1, REG2
Before Instruction
REG1
REG2
=
=
0x33
0x11
After Instruction
REG1
REG2
=
=
0x33
0x33
DS39616D-page 308
PIC18F2331/2431/4331/4431
MOVLW
Move Literal to W
MOVWF
Syntax:
[ label ]
Syntax:
[ label ]
Operands:
0 k 255
Operands:
Operation:
kW
0 f 255
a [0,1]
Status Affected:
None
Operation:
(W) f
Status Affected:
None
Encoding:
0000
MOVLW k
1110
kkkk
kkkk
Description:
Words:
Cycles:
Move W to f
Encoding:
0110
Q1
Q2
Q3
Q4
Read
literal k
Process
Data
Write to
W
Example:
After Instruction
W
=
MOVLW
0x5A
0x5A
ffff
ffff
Words:
Cycles:
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
register f
Process
Data
Write
register f
Example:
MOVWF
Before Instruction
W
=
REG
=
After Instruction
W
=
REG
=
111a
f [,a]
Description:
Q Cycle Activity:
Decode
MOVWF
REG
0x4F
0xFF
0x4F
0x4F
DS39616D-page 309
PIC18F2331/2431/4331/4431
MULLW
Syntax:
[ label ]
Operands:
0 k 255
Operation:
(W) x k PRODH:PRODL
Status Affected:
None
Encoding:
0000
Description:
MULLW
MULWF
1101
kkkk
kkkk
Words:
Cycles:
Multiply W with f
Syntax:
[ label ]
Operands:
0 f 255
a [0,1]
Operation:
Status Affected:
None
Encoding:
0000
Q1
Q2
Q3
Q4
Read
literal k
Process
Data
Write
registers
PRODH:
PRODL
Example:
MULLW
0xC4
Before Instruction
W
PRODH
PRODL
=
=
=
0xE2
?
?
After Instruction
W
PRODH
PRODL
=
=
=
0xE2
0xAD
0x08
DS39616D-page 310
001a
f [,a]
ffff
ffff
Description:
Words:
Cycles:
Q Cycle Activity:
Decode
MULWF
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
register f
Process
Data
Write
registers
PRODH:
PRODL
Example:
MULWF
REG
Before Instruction
W
REG
PRODH
PRODL
=
=
=
=
0xC4
0xB5
?
?
After Instruction
W
REG
PRODH
PRODL
=
=
=
=
0xC4
0xB5
0x8A
0x94
PIC18F2331/2431/4331/4431
NEGF
Negate f
Syntax:
[ label ]
Operands:
0 f 255
a [0,1]
Operation:
(f)+1f
Status Affected:
N, OV, C, DC, Z
Encoding:
0110
Description:
NEGF
f [,a]
Cycles:
No Operation
Syntax:
[ label ]
Operands:
None
ffff
NOP
Operation:
No operation
Status Affected:
None
Encoding:
110a
0000
1111
ffff
Words:
NOP
0000
xxxx
Description:
No operation.
Words:
Cycles:
0000
xxxx
0000
xxxx
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
No
operation
No
operation
No
operation
Example:
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
register f
Process
Data
Write
register f
Example:
NEGF
None.
REG, 1
Before Instruction
REG
=
After Instruction
REG
=
DS39616D-page 311
PIC18F2331/2431/4331/4431
POP
PUSH
Syntax:
[ label ]
Syntax:
[ label ]
Operands:
None
Operands:
None
Operation:
Operation:
(PC + 2) TOS
Status Affected:
None
Status Affected:
None
Encoding:
0000
POP
0000
0000
0110
Description:
Words:
Cycles:
Encoding:
Q2
Q3
Q4
Decode
No
operation
POP TOS
value
No
operation
POP
GOTO
NEW
Before Instruction
TOS
Stack (1 level down)
DS39616D-page 312
0000
0000
0101
Words:
Cycles:
Q Cycle Activity:
Q1
After Instruction
TOS
PC
0000
Description:
Q Cycle Activity:
Example:
PUSH
Q1
Q2
Q3
Q4
Decode
PUSH
PC + 2 onto
return stack
No
operation
No
operation
Example:
=
=
=
=
0x0031A2
0x014332
0x014332
NEW
PUSH
Before Instruction
TOS
PC
=
=
0x00345A
0x000124
After Instruction
PC
TOS
Stack (1 level down)
=
=
=
0x000126
0x000126
0x00345A
PIC18F2331/2431/4331/4431
RCALL
Relative Call
Syntax:
[ label ] RCALL
Operands:
-1024 n 1023
Operation:
(PC) + 2 TOS,
(PC) + 2 + 2n PC
Status Affected:
None
Encoding:
1101
Description:
1nnn
nnnn
nnnn
Words:
Cycles:
RESET
Reset
Syntax:
[ label ]
Operands:
None
Operation:
Status Affected:
All
Encoding:
0000
Q1
Q2
Q3
Q4
Decode
Read literal
n
Process
Data
Write to PC
No
operation
No
operation
0000
1111
1111
Description:
Words:
Cycles:
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Start
Reset
No
operation
No
operation
Example:
Q Cycle Activity:
RESET
After Instruction
Registers =
Flags*
=
RESET
Reset Value
Reset Value
PUSH PC to
stack
No
operation
Example:
No
operation
HERE
RCALL Jump
Before Instruction
PC =
Address (HERE)
After Instruction
PC =
Address (Jump)
TOS =
Address (HERE + 2)
DS39616D-page 313
PIC18F2331/2431/4331/4431
RETFIE
RETLW
Syntax:
[ label ]
Syntax:
[ label ]
Operands:
s [0,1]
Operands:
0 k 255
Operation:
(TOS) PC,
1 GIE/GIEH or PEIE/GIEL;
if s = 1:
(WS) W,
(STATUSS) STATUS,
(BSRS) BSR,
PCLATU, PCLATH are unchanged
Operation:
k W,
(TOS) PC,
PCLATU, PCLATH are unchanged
Status Affected:
None
Status Affected:
RETFIE [s]
Encoding:
0000
0000
Description:
0000
0001
Words:
Cycles:
Q Cycle Activity:
1100
kkkk
kkkk
Words:
Cycles:
000s
RETLW k
Description:
GIE/GIEH, PEIE/GIEL.
Encoding:
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
literal k
Process
Data
POP PC
from stack,
Write to W
No
operation
No
operation
No
operation
No
operation
Example:
Q1
Q2
Q3
Q4
Decode
No
operation
No
operation
POP PC
from stack
Set GIEH or
GIEL
No
operation
Return Literal to W
No
operation
Example:
RETFIE
After Interrupt
PC
W
BSR
STATUS
GIE/GIEH, PEIE/GIEL
DS39616D-page 314
No
operation
No
operation
1
=
=
=
=
=
TOS
WS
BSRS
STATUSS
1
CALL TABLE ;
;
;
;
:
TABLE
ADDWF PCL ;
RETLW k0
;
RETLW k1
;
:
:
RETLW kn
;
W contains table
offset value
W now has
table value
W = offset
Begin table
End of table
Before Instruction
W
=
0x07
After Instruction
W
=
value of kn
PIC18F2331/2431/4331/4431
RETURN
RLCF
Syntax:
[ label ]
Syntax:
[ label ]
Operands:
s [0,1]
Operands:
Operation:
(TOS) PC;
if s = 1:
(WS) W,
(STATUSS) STATUS,
(BSRS) BSR,
PCLATU, PCLATH are unchanged
0 f 255
d [0,1]
a [0,1]
Operation:
Status Affected:
C, N, Z
Status Affected:
None
Encoding:
0000
Description:
RETURN [s]
Encoding:
0000
0001
001s
0011
Description:
f [,d [,a]]
01da
ffff
ffff
register f
Words:
Words:
Cycles:
Cycles:
Q Cycle Activity:
RLCF
Q Cycle Activity:
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Decode
No
operation
Process
Data
POP PC
from stack
Decode
Read
register f
Process
Data
Write to
destination
No
operation
No
operation
No
operation
No
operation
Example:
RETURN
After Interrupt
PC = TOS
Example:
RLCF
Before Instruction
REG
=
C
=
1110 0110
0
After Instruction
REG
=
W
=
C
=
1110 0110
1100 1100
1
REG, W
DS39616D-page 315
PIC18F2331/2431/4331/4431
RLNCF
RRCF
Syntax:
[ label ]
Syntax:
[ label ]
Operands:
0 f 255
d [0,1]
a [0,1]
Operands:
0 f 255
d [0,1]
a [0,1]
Operation:
Operation:
Status Affected:
N, Z
Status Affected:
C, N, Z
Encoding:
0100
Description:
RLNCF
01da
f [,d [,a]]
ffff
ffff
Encoding:
0011
Description:
RRCF
00da
Cycles:
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
register f
Process
Data
Write to
destination
Example:
RLNCF
Words:
Cycles:
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
register f
Process
Data
Write to
destination
REG
Example:
Before Instruction
REG
=
1010 1011
After Instruction
REG
=
0101 0111
DS39616D-page 316
ffff
register f
C
1
ffff
register f
Words:
f [,d [,a]]
RRCF
REG, W
Before Instruction
REG
=
C
=
1110 0110
0
After Instruction
REG
=
W
=
C
=
1110 0110
0111 0011
0
PIC18F2331/2431/4331/4431
RRNCF
SETF
Syntax:
[ label ]
Syntax:
[ label ] SETF
Operands:
0 f 255
d [0,1]
a [0,1]
Operands:
0 f 255
a [0,1]
Operation:
FFh f
Operation:
Status Affected:
None
Status Affected:
RRNCF
f [,d [,a]]
Encoding:
N, Z
Encoding:
0100
Description:
00da
ffff
ffff
Words:
Cycles:
1
Q1
Q2
Q3
Q4
Decode
Read
register f
Process
Data
Write to
destination
RRNCF
1101 0111
After Instruction
REG
=
1110 1011
RRNCF
f [,a]
100a
ffff
ffff
Description:
Words:
Cycles:
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
register f
Process
Data
Write
register f
SETF
REG
Before Instruction
REG
0x5A
After Instruction
REG
0xFF
REG, 1, 0
Before Instruction
REG
=
Example 2:
0110
Example:
Q Cycle Activity:
Example 1:
Set f
REG, W
Before Instruction
W
=
REG
=
?
1101 0111
After Instruction
W
=
REG
=
1110 1011
1101 0111
DS39616D-page 317
PIC18F2331/2431/4331/4431
SLEEP
SUBFWB
Syntax:
[ label ]
Syntax:
[ label ]
Operands:
0 f 255
d [0,1]
a [0,1]
Operation:
Status Affected:
N, OV, C, DC, Z
SLEEP
Operands:
None
Operation:
00h WDT,
0 WDT postscaler,
1 TO,
0 PD
Status Affected:
TO, PD
Encoding:
0000
Encoding:
0000
0000
0011
Description:
Words:
Cycles:
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
No
operation
Process
Data
Go to
Sleep
Example:
SLEEP
Before Instruction
TO =
?
?
PD =
After Instruction
1
TO =
0
PD =
If WDT causes wake-up, this bit is cleared.
0101
01da
f [,d [,a]]
ffff
ffff
Description:
Words:
Cycles:
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
register f
Process
Data
Write to
destination
Example 1:
Before Instruction
REG
=
W
=
C
=
After Instruction
REG
=
W
=
C
=
Z
=
N
=
Example 2:
Before Instruction
REG
=
W
=
C
=
After Instruction
REG
=
W
=
C
=
Z
=
N
=
Example 3:
Before Instruction
REG
=
W
=
C
=
After Instruction
REG
=
W
=
C
=
Z
=
N
=
DS39616D-page 318
SUBFWB
SUBFWB REG
0x03
0x02
0x01
0xFF
0x02
0x00
0x00
0x01
SUBFWB
; result is negative
REG, 0, 0
2
5
1
2
3
1
0
0
; result is positive
SUBFWB
REG, 1, 0
1
2
0
0
2
1
1
0
; result is zero
PIC18F2331/2431/4331/4431
SUBLW
SUBWF
Subtract W from f
Syntax:
[ label ]
Syntax:
[ label ]
Operands:
0 f 255
d [0,1]
a [0,1]
Operation:
Status Affected:
N, OV, C, DC, Z
SUBLW k
Operands:
0 k 255
Operation:
k (W) W
Status Affected:
N, OV, C, DC, Z
Encoding:
0000
1000
kkkk
kkkk
Description:
Words:
Cycles:
Encoding:
0101
Q1
Q2
Q3
Q4
Read
literal k
Process
Data
Write to
W
Example 1:
Before Instruction
W
=
C
=
After Instruction
W
=
C
=
Z
=
N
=
Example 2:
SUBLW
1
?
1
1
0
0
SUBLW
Before Instruction
W
=
C
=
2
?
After Instruction
W
=
C
=
Z
=
N
=
0
1
1
0
Example 3:
0x02
SUBLW
11da
f [,d [,a]]
ffff
ffff
Description:
Words:
Cycles:
Q Cycle Activity:
Decode
SUBWF
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
register f
Process
Data
Write to
destination
; result is positive
Example 1:
0x02
; result is zero
0x02
Before Instruction
W
=
C
=
3
?
After Instruction
W
=
C
=
Z
=
N
=
FF ; (2s complement)
; result is negative
0
0
1
Before Instruction
REG
=
W
=
C
=
After Instruction
REG
=
W
=
C
=
Z
=
N
=
Example 2:
Before Instruction
REG
=
W
=
C
=
After Instruction
REG
=
W
=
C
=
Z
=
N
=
Example 3:
Before Instruction
REG
=
W
=
C
=
After Instruction
REG
=
W
=
C
=
Z
=
N
=
SUBWF
REG
3
2
?
1
2
1
0
0
SUBWF
; result is positive
REG, W
2
2
?
2
0
1
1
0
SUBWF
; result is zero
REG
0x01
0x02
?
0xFFh ; (2s complement)
0x02
0x00 ; result is negative
0x00
0x01
DS39616D-page 319
PIC18F2331/2431/4331/4431
SUBWFB
SWAPF
Syntax:
[ label ]
Syntax:
[ label ]
0 f 255
d [0,1]
a [0,1]
SUBWFB
f [,d [,a]]
Swap f
SWAPF f [,d [,a]]
Operands:
0 f 255
d [0,1]
a [0,1]
Operands:
Operation:
Operation:
Status Affected:
N, OV, C, DC, Z
(f<3:0>) dest<7:4>,
(f<7:4>) dest<3:0>
Status Affected:
None
Encoding:
0101
10da
ffff
ffff
Description:
Words:
Cycles:
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
register f
Process
Data
Write to
destination
Example 1:
SUBWFB
Before Instruction
REG
=
W
=
C
=
After Instruction
REG
=
W
=
C
=
Z
=
N
=
Example 2:
0011
10da
ffff
ffff
Description:
Words:
Cycles:
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
register f
Process
Data
Write to
destination
REG, 1, 0
Example:
0x19
0x0D
0x01
(0001 1001)
(0000 1101)
0x0C
0x0D
0x01
0x00
0x00
(0000 1011)
(0000 1101)
SWAPF
Before Instruction
REG
=
0x53
After Instruction
REG
=
0x35
REG
; result is positive
SUBWFB REG, 0, 0
Before Instruction
REG
=
W
=
C
=
After Instruction
REG
=
W
=
C
=
Z
=
N
=
Example 3:
0x1B
0x1A
0x00
(0001 1011)
(0001 1010)
0x1B
0x00
0x01
0x01
0x00
(0001 1011)
SUBWFB
Before Instruction
REG
=
W
=
C
=
After Instruction
REG
=
W
C
Z
N
Encoding:
=
=
=
=
DS39616D-page 320
; result is zero
REG, 1, 0
0x03
0x0E
0x01
(0000 0011)
(0000 1101)
0xF5
(1111 0100)
; [2s comp]
(0000 1101)
0x0E
0x00
0x00
0x01
; result is negative
PIC18F2331/2431/4331/4431
TBLRD
Table Read
TBLRD
Syntax:
[ label ]
Example 1:
TBLRD
Operands:
None
Operation:
if TBLRD *,
(Prog Mem (TBLPTR)) TABLAT,
TBLPTR No Change;
if TBLRD *+,
(Prog Mem (TBLPTR)) TABLAT,
(TBLPTR) + 1 TBLPTR;
if TBLRD *-,
(Prog Mem (TBLPTR)) TABLAT,
(TBLPTR) 1 TBLPTR;
if TBLRD +*,
(TBLPTR) + 1 TBLPTR,
(Prog Mem (TBLPTR)) TABLAT
Encoding:
0000
0000
0000
=
=
=
0x55
0x00A356
0x34
After Instruction
TABLAT
TBLPTR
=
=
0x34
0x00A357
Example 2:
*+ ;
Before Instruction
TABLAT
TBLPTR
MEMORY(0x00A356)
TBLRD
+* ;
Before Instruction
TABLAT
TBLPTR
MEMORY(0x01A357)
MEMORY(0x01A358)
=
=
=
=
0xAA
0x01A357
0x12
0x34
After Instruction
TABLAT
TBLPTR
=
=
0x34
0x01A358
*
=1 *+
=2 *=3 +*
Description:
Words:
Cycles:
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
No
operation
No
operation
No
operation
No
operation
No operation
(Read Program
Memory)
No
operation
No operation
(Write
TABLAT)
DS39616D-page 321
PIC18F2331/2431/4331/4431
TBLWT
Table Write
Syntax:
[ label ]
Words:
Operands:
None
Cycles: 2
Operation:
if TBLWT*,
(TABLAT) Holding Register,
TBLPTR No Change;
if TBLWT*+,
(TABLAT) Holding Register,
(TBLPTR) + 1 TBLPTR;
if TBLWT*-,
(TABLAT) Holding Register,
(TBLPTR) 1 TBLPTR;
if TBLWT+*,
(TBLPTR) + 1 TBLPTR,
(TABLAT) Holding Register
Q Cycle Activity:
Status Affected:
Encoding:
Description:
Example 1:
None
0000
0000
0000
11nn
nn = 0 *
=1 *+
=2 *=3 +*
DS39616D-page 322
Q1
Q2
Q3
Q4
Decode
No
operation
No
operation
No
operation
No
operation
No
operation
(Read
TABLAT)
No
operation
No
operation
(Write to
Holding
Register )
TBLWT
*+;
Before Instruction
TABLAT
TBLPTR
HOLDING REGISTER
(0x00A356)
=
=
0x55
0x00A356
0xFF
TBLWT
+*;
Before Instruction
TABLAT
TBLPTR
HOLDING REGISTER
(0x01389A)
HOLDING REGISTER
(0x01389B)
=
=
0x34
0x01389A
0xFF
0xFF
PIC18F2331/2431/4331/4431
TSTFSZ
Test f, Skip if 0
XORLW
Syntax:
[ label ]
Syntax:
[ label ]
Operands:
0 f 255
a [0,1]
TSTFSZ f [,a]
Operation:
skip if f = 0
Status Affected:
None
Encoding:
Description:
Operands:
0 k 255
Operation:
(W) .XOR. k W
Status Affected:
N, Z
Encoding:
0110
011a
ffff
ffff
Words:
Cycles:
1(2)
Note: 3 cycles if skip and followed
by a 2-word instruction.
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
register f
Process
Data
No
operation
XORLW k
0000
1010
kkkk
kkkk
Description:
Words:
Cycles:
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
literal k
Process
Data
Write to W
Example:
XORLW
Before Instruction
W
=
0xB5
After Instruction
W
=
0x1A
0xAF
If skip:
Q1
Q2
Q3
Q4
No
operation
No
operation
No
operation
No
operation
Q2
Q3
Q4
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
Example:
HERE
NZERO
ZERO
TSTFSZ
:
CNT
Before Instruction
PC = Address (HERE)
After Instruction
If CNT
PC
If CNT
PC
=
=
0x00,
Address (ZERO)
0x00,
Address (NZERO)
DS39616D-page 323
PIC18F2331/2431/4331/4431
XORWF
Exclusive OR W with f
Syntax:
[ label ]
Operands:
0 f 255
d [0,1]
a [0,1]
Operation:
Status Affected:
N, Z
Encoding:
0001
XORWF
10da
f [,d [,a]]
ffff
ffff
Description:
Words:
Cycles:
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
register f
Process
Data
Write to
destination
Example:
XORWF
Before Instruction
REG
=
W
=
0xAF
0xB5
After Instruction
REG
=
W
=
0x1A
0xB5
DS39616D-page 324
REG
PIC18F2331/2431/4331/4431
25.0
DEVELOPMENT SUPPORT
25.1
DS39616D-page 325
PIC18F2331/2431/4331/4431
25.2
25.3
25.4
MPASM Assembler
25.5
25.6
DS39616D-page 326
PIC18F2331/2431/4331/4431
25.7
25.8
25.9
MPLAB ICD 3 In-Circuit Debugger System is Microchips most cost effective high-speed hardware
debugger/programmer for Microchip Flash Digital Signal Controller (DSC) and microcontroller (MCU)
devices. It debugs and programs PIC Flash microcontrollers and dsPIC DSCs with the powerful, yet
easy-to-use graphical user interface of MPLAB
Integrated Development Environment (IDE).
The MPLAB ICD 3 In-Circuit Debugger probe is connected to the design engineers PC using a high-speed
USB 2.0 interface and is connected to the target with a
connector compatible with the MPLAB ICD 2 or MPLAB
REAL ICE systems (RJ-11). MPLAB ICD 3 supports all
MPLAB ICD 2 headers.
DS39616D-page 327
PIC18F2331/2431/4331/4431
25.11 PICkit 2 Development
Programmer/Debugger and
PICkit 2 Debug Express
25.13 Demonstration/Development
Boards, Evaluation Kits, and
Starter Kits
DS39616D-page 328
PIC18F2331/2431/4331/4431
26.0
ELECTRICAL CHARACTERISTICS
NOTICE: Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at those or any other conditions above those
indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for
extended periods may affect device reliability.
DS39616D-page 329
PIC18F2331/2431/4331/4431
FIGURE 26-1:
6.0V
5.5V
Voltage
5.0V
PIC18F2X31/4X31
4.5V
4.2V
4.0V
3.5V
3.0V
2.5V
2.0V
40 MHz
Frequency
FIGURE 26-2:
6.0V
5.5V
5.0V
PIC18LF2X31/4X31
Voltage
4.5V
4.2V
4.0V
3.5V
3.0V
2.5V
2.0V
40 MHz
4 MHz
Frequency
FMAX = (16.36 MHz/V) (VDDAPPMIN 2.0V) + 4 MHz
Note: VDDAPPMIN is the minimum voltage of the PIC device in the application.
DS39616D-page 330
PIC18F2331/2431/4331/4431
26.1
PIC18LF2331/2431/4331/4431
(Industrial)
PIC18F2331/2431/4331/4431
(Industrial, Extended)
Param
No.
D001
Symbol
VDD
Characteristic
Min
Typ
Max
Units
Conditions
Supply Voltage
PIC18LF2X31/4X31
2.0
5.5
PIC18F2X31/4X31
4.2
5.5
D001C
AVDD
VDD 0.3
VDD + 0.3
D001D
AVSS
VSS 0.3
VSS + 0.3
D002
VDR
1.5
D003
VPOR
0.7
D004
SVDD
0.05
D005A
VBOR
D005B
D005C
D005D
D005E
D005F
Legend:
Note 1:
2:
BORV<1:0> = 11
N/A
N/A
N/A
BORV<1:0> = 10
2.50
2.72
2.94
BORV<1:0> = 01
3.88
4.22
4.56
BORV<1:0> = 00
4.18
4.54
4.90
Reserved
N/A
N/A
N/A
BORV<1:0>= 10
2.34
2.72
3.10
BORV<1:0> = 01
3.63
4.22
4.81
BORV<1:0> = 00
3.90
4.54
5.18
Reserved
N/A
N/A
N/A
Reserved
BORV<1:0> = 01
3.88
4.22
4.56
(Note 2)
BORV<1:0> = 00
4.18
4.54
4.90
(Note 2)
N/A
N/A
N/A
Reserved
BORV<1:0> = 01
N/A
N/A
N/A
Reserved
BORV<1:0> = 00
3.90
4.54
5.18
(Note 2)
N/A
N/A
N/A
Reserved
BORV<1:0> = 01
3.88
4.22
4.56
(Note 2)
BORV<1:0> = 00
4.18
4.54
4.90
(Note 2)
N/A
N/A
N/A
Reserved
BORV<1:0> = 01
N/A
N/A
N/A
Reserved
BORV<1:0> = 00
3.90
4.54
5.18
(Note 2)
DS39616D-page 331
PIC18F2331/2431/4331/4431
26.2
PIC18LF2331/2431/4331/4431
(Industrial)
PIC18F2331/2431/4331/4431
(Industrial, Extended)
Param
No.
Device
Typ
Max
Units
Conditions
PIC18LF2X31/4X31
All devices
Legend:
Note 1:
2:
3:
4:
0.1
0.5
-40C
0.1
0.5
+25C
0.2
1.9
+85C
0.1
0.5
-40C
0.1
0.5
+25C
0.3
1.9
+85C
0.1
2.0
-40C
0.1
2.0
+25C
0.4
6.5
+85C
33
+125C
VDD = 2.0V
(Sleep mode)
VDD = 3.0V
(Sleep mode)
VDD = 5.0V
(Sleep mode)
DS39616D-page 332
PIC18F2331/2431/4331/4431
26.2
PIC18LF2331/2431/4331/4431
(Industrial)
PIC18F2331/2431/4331/4431
(Industrial, Extended)
Param
No.
Device
Typ
Max
Units
Conditions
40
-40C
40
+25C
11
40
+85C
25
68
-40C
25
68
+25C
20
68
+85C
55
180
-40C
55
180
+25C
50
180
+85C
0.25
mA
+125C
140
220
-40C
145
220
+25C
155
220
+85C
PIC18LF2X31/4X31
All devices
PIC18LF2X31/4X31
PIC18LF2X31/4X31
All devices
PIC18LF2X31/4X31
PIC18LF2X31/4X31
All devices
Legend:
Note 1:
2:
3:
4:
215
330
-40C
225
330
+25C
235
330
+85C
385
550
-40C
390
550
+25C
405
550
+85C
+125C
0.7
2.8
mA
410
600
-40C
425
600
+25C
435
600
+85C
650
900
-40C
670
900
+25C
680
900
+85C
1.2
1.8
mA
-40C
1.2
1.8
mA
+25C
1.2
1.8
mA
+85C
2.2
mA
+125C
VDD = 2.0V
VDD = 3.0V
FOSC = 31 kHz
(RC_RUN mode,
Internal oscillator source)
VDD = 5.0V
VDD = 2.0V
VDD = 3.0V
FOSC = 1 MHz
(RC_RUN mode,
Internal oscillator source)
VDD = 5.0V
VDD = 2.0V
VDD = 3.0V
FOSC = 4 MHz
(RC_RUN mode,
Internal oscillator source)
VDD = 5.0V
DS39616D-page 333
PIC18F2331/2431/4331/4431
26.2
PIC18LF2331/2431/4331/4431
(Industrial)
PIC18F2331/2431/4331/4431
(Industrial, Extended)
Param
No.
Device
Typ
Max
Units
Conditions
PIC18LF2X31/4X31
All devices
PIC18LF2X31/4X31
PIC18LF2X31/4X31
All devices
PIC18LF2X31/4X31
PIC18LF2X31/4X31
All devices
Legend:
Note 1:
2:
3:
4:
4.7
-40C
5.0
+25C
5.8
11
+85C
7.0
11
-40C
7.8
11
+25C
8.7
15
+85C
12
16
-40C
14
16
+25C
14
22
+85C
200
850
+125C
75
150
-40C
85
150
+25C
95
150
+85C
110
180
-40C
125
180
+25C
135
180
+85C
180
300
-40C
195
300
+25C
200
300
+85C
300
750
+125C
175
275
-40C
185
275
+25C
195
275
+85C
265
375
-40C
280
375
+25C
300
375
+85C
475
800
-40C
500
800
+25C
505
800
+85C
0.7
1.6
mA
+125C
VDD = 2.0V
VDD = 3.0V
FOSC = 31 KHz
(RC_IDLE mode,
Internal oscillator source)
VDD = 5.0V
VDD = 2.0V
VDD = 3.0V
FOSC = 1 MHz
(RC_IDLE mode,
Internal oscillator source)
VDD = 5.0V
VDD = 2.0V
VDD = 3.0V
FOSC = 4 MHz
(RC_IDLE mode,
Internal oscillator source)
VDD = 5.0V
DS39616D-page 334
PIC18F2331/2431/4331/4431
26.2
PIC18LF2331/2431/4331/4431
(Industrial)
PIC18F2331/2431/4331/4431
(Industrial, Extended)
Param
No.
Device
Typ
Max
Units
Conditions
PIC18LF2X31/4X31
All devices
PIC18LF2X31/4X31
PIC18LF2X31/4X31
All devices
150
250
-40C
150
250
+25C
160
250
+85C
340
350
-40C
300
350
+25C
+85C
280
350
0.72
1.0
mA
-40C
0.63
1.0
mA
+25C
0.57
1.0
mA
+85C
+125C
0.9
2.1
mA
440
600
-40C
450
600
+25C
460
600
+85C
0.80
1.0
mA
-40C
0.78
1.0
mA
+25C
0.77
1.0
mA
+85C
1.6
2.0
mA
-40C
1.5
2.0
mA
+25C
1.5
2.0
mA
+85C
2.0
4.2
mA
+125C
10
28
mA
+125C
VDD = 2.0V
VDD = 3.0V
VDD = 5.0V
VDD = 2.0V
VDD = 3.0V
All devices
Legend:
Note 1:
2:
3:
4:
9.5
12
mA
-40C
9.7
12
mA
+25C
9.9
12
mA
+85C
11.9
15
mA
-40C
12.1
15
mA
+25C
12.3
15
mA
+85C
FOSC = 4 MHz
(PRI_RUN,
EC oscillator)
VDD = 5.0V
All devices
All devices
FOSC = 1 MHZ
(PRI_RUN,
EC oscillator)
VDD = 5.0V
VDD = 4.2V
VDD = 5.0V
FOSC = 25 MHz
(PRI_RUN,
EC oscillator)
FOSC = 40 MHZ
(PRI_RUN,
EC oscillator)
DS39616D-page 335
PIC18F2331/2431/4331/4431
26.2
PIC18LF2331/2431/4331/4431
(Industrial)
PIC18F2331/2431/4331/4431
(Industrial, Extended)
Param
No.
Device
Typ
Max
Units
Conditions
PIC18LF2X31/4X31
All devices
PIC18LF2X31/4X31
PIC18LF2X31/4X31
All devices
35
50
-40C
35
50
+25C
35
60
+85C
55
80
-40C
50
80
+25C
60
100
+85C
105
150
-40C
110
150
+25C
115
150
+85C
300
400
+125C
135
180
-40C
140
180
+25C
140
180
+85C
215
280
-40C
225
280
+25C
230
280
+85C
410
525
-40C
420
525
+25C
430
525
+85C
1.2
1.7
mA
+125C
18
22
mA
+125C
3.2
4.1
mA
-40C
VDD = 2.0V
VDD = 3.0V
VDD = 5.0V
VDD = 2.0V
VDD = 3.0V
All devices
Legend:
Note 1:
2:
3:
4:
3.2
4.1
mA
+25C
3.3
4.1
mA
+85C
4.0
5.1
mA
-40C
4.1
5.1
mA
+25C
4.1
5.1
mA
+85C
FOSC = 4 MHz
(PRI_IDLE mode,
EC oscillator)
VDD = 5.0V
All devices
All devices
FOSC = 1 MHz
(PRI_IDLE mode,
EC oscillator)
VDD = 5.0V
FOSC = 25 MHz
(PRI_IDLE mode,
EC oscillator)
VDD = 4.2 V
FOSC = 40 MHz
(PRI_IDLE mode,
EC oscillator)
VDD = 5.0V
DS39616D-page 336
PIC18F2331/2431/4331/4431
26.2
PIC18LF2331/2431/4331/4431
(Industrial)
PIC18F2331/2431/4331/4431
(Industrial, Extended)
Param
No.
Device
Typ
Max
Units
Conditions
PIC18LF2X31/4X31
All devices
PIC18LF2X31/4X31
PIC18LF2X31/4X31
All devices
Legend:
Note 1:
2:
3:
4:
5.1
-10C
5.8
+25C
7.9
11
+70C
7.9
12
-10C
8.9
12
+25C
10.5
14
+70C
12.5
20
-10C
16.3
20
+25C
18.9
25
+70C
150
850
+125C
9.2
15
-10C
9.6
15
+25C
12.7
18
+70C
22.0
30
-10C
21.0
30
+25C
20.0
35
+70C
30
80
-10C
45
80
+25C
45
85
+70C
250
850
+125C
VDD = 2.0V
VDD = 3.0V
FOSC = 32 kHz(4)
(SEC_RUN mode,
Timer1 as clock)
VDD = 5.0V
VDD = 2.0V
VDD = 3.0V
FOSC = 32 kHz(4)
(SEC_IDLE mode,
Timer1 as clock)
VDD = 5.0V
DS39616D-page 337
PIC18F2331/2431/4331/4431
26.2
PIC18LF2331/2431/4331/4431
(Industrial)
PIC18F2331/2431/4331/4431
(Industrial, Extended)
Param
No.
Device
Typ
Max
Units
Conditions
D022A
(IBOR)
D022B
(ILVD)
Watchdog Timer
Brown-out Reset
Low-Voltage Detect
D025
(IOSCB)
Timer1 Oscillator
D026
(IAD)
A/D Converter
Legend:
Note 1:
2:
3:
4:
1.5
4.0
-40C
2.2
4.0
+25C
3.1
5.0
+85C
2.5
6.0
-40C
3.3
6.0
+25C
4.7
7.0
+85C
3.7
10.0
-40C
4.5
10.0
+25C
6.1
13.0
+85C
22
44
+125C
19
35.0
-40C to +85C
24
45.0
-40C to +85C
40
75
+125C
VDD = 2.0V
VDD = 3.0V
VDD = 5.0V
VDD = 3.0V
VDD = 5.0V
8.5
25.0
-40C to +85C
VDD = 2.0V
16
35.0
-40C to +85C
VDD = 3.0V
20
45.0
-40C to +85C
35
66
+125C
1.7
3.5
-40C
1.8
3.5
+25C
2.1
4.5
+85C
2.2
4.5
-40C
2.6
4.5
+25C
2.8
5.5
+85C
3.0
6.0
-40C
3.3
6.0
+25C
3.6
7.0
+85C
VDD = 5.0V
VDD = 2.0V
32 kHz on Timer1(4)
VDD = 3.0V
32 kHz on Timer1(4)
VDD = 5.0V
32 kHz on Timer1(4)
42
70
+125C
1.0
3.0
-40C to +85C
VDD = 2.0V
1.0
4.0
-40C to +85C
VDD = 3.0V
2.0
10.0
-40C to +85C
150
950
+125C
VDD = 5.0V
DS39616D-page 338
PIC18F2331/2431/4331/4431
26.3
DC CHARACTERISTICS
Param
Symbol
No.
VIL
Characteristic
Min
Max
Units
Conditions
VSS
0.15 VDD
0.8
VSS
VSS
0.2 VDD
0.3 VDD
V
V
I2C enabled
D030
D030A
D031
D032
MCLR
VSS
0.2 VDD
D032A
VSS
0.3 VDD
D033
OSC1
VSS
0.2 VDD
EC mode(1)
VDD
VIH
D040
D040A
D041
2.0
VDD
0.8 VDD
0.7 VDD
VDD
VDD
V
V
I2C enabled
D042
MCLR
0.8 VDD
VDD
D042A
0.7 VDD
VDD
D043
OSC1
0.8 VDD
VDD
EC mode(1)
+200 nA
+50 nA
MCLR
OSC1
50
400
IIL
D060
D061
D063
D070
Note 1:
2:
3:
IPU
IPURB
In RC oscillator configuration, the OSC1/CLKI pin is a Schmitt Trigger input. It is not recommended that the
PIC device be driven with an external clock while in RC mode.
The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified
levels represent normal operating conditions. Higher leakage current may be measured at different input
voltages.
Negative current is defined as current sourced by the pin.
DS39616D-page 339
PIC18F2331/2431/4331/4431
26.3
DC CHARACTERISTICS
Param
Symbol
No.
VOL
Characteristic
Min
Max
Units
Conditions
D080
I/O Ports
0.6
D083
OSC2/CLKO
(RC, RCIO, EC, ECIO modes)
0.6
VOH
D090
I/O Ports
VDD 0.7
D092
OSC2/CLKO
(RC, RCIO, EC, ECIO modes)
VDD 0.7
COSC2
OSC2 Pin
15
pF
D101
CIO
50
pF
D102
CB
SCL, SDA
400
pF
I2C Specification
Note 1:
2:
3:
In RC oscillator configuration, the OSC1/CLKI pin is a Schmitt Trigger input. It is not recommended that the
PIC device be driven with an external clock while in RC mode.
The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified
levels represent normal operating conditions. Higher leakage current may be measured at different input
voltages.
Negative current is defined as current sourced by the pin.
DS39616D-page 340
PIC18F2331/2431/4331/4431
TABLE 26-1:
DC CHARACTERISTICS
Param
No.
Sym
Characteristic
Min
Typ
Max
Units
Conditions
VPP
9.00
13.25
D112
IPP
300
D113
IDDP
mA
(Note 3)
ED
Byte Endurance
100K
1M
D121
VDRW
VMIN
5.5
D122
TDEW
ms
D123
40
D124
TREF
1M
10M
EP
Cell Endurance
10K
100K
D131
VPR
VMIN
5.5
D132
VIE
4.5
5.5
D132A VIW
4.5
5.5
D132B VPEW
VMIN
5.5
D133
TIE
ms
D133A TIW
ms
D133A TIW
ms
40
100
D134
Data in Typ column is at 5.0V, 25C unless otherwise stated. These parameters are for design guidance
only and are not tested.
Note 1: These specifications are for programming the on-chip program memory through the use of table write
instructions.
2: Refer to Section 7.9 Using the Data EEPROM for a more detailed discussion on data EEPROM
endurance.
3: Required only if Single-Supply Programming is disabled.
DS39616D-page 341
PIC18F2331/2431/4331/4431
FIGURE 26-3:
VLVD
(LVDIF set by hardware)
LVDIF
TABLE 26-2:
PIC18LF2331/2431/4331/4431
(Industrial)
PIC18F2331/2431/4331/4431
(Industrial, Extended)
Param
No.
D420A
Symbol
VLVD
Legend:
Characteristic
LVD Voltage on VDD Transition High-to-Low
Min
Typ
Max
Units
Conditions
N/A
N/A
N/A
Reserved
LVDL<3:0> = 0001
N/A
N/A
N/A
Reserved
LVDL<3:0> = 0010
2.08
2.26
2.44
LVDL<3:0> = 0011
2.26
2.45
2.65
LVDL<3:0> = 0100
2.35
2.55
2.76
LVDL<3:0> = 0101
2.55
2.77
2.99
LVDL<3:0> = 0110
2.64
2.87
3.10
LVDL<3:0> = 0111
2.82
3.07
3.31
LVDL<3:0> = 1000
3.09
3.36
3.63
LVDL<3:0> = 1001
3.29
3.57
3.86
LVDL<3:0> = 1010
3.38
3.67
3.96
LVDL<3:0> = 1011
3.56
3.87
4.18
LVDL<3:0> = 1100
3.75
4.07
4.40
LVDL<3:0> = 1101
3.93
4.28
4.62
LVDL<3:0> = 1110
4.23
4.60
4.96
DS39616D-page 342
PIC18F2331/2431/4331/4431
TABLE 26-2:
PIC18LF2331/2431/4331/4431
(Industrial)
PIC18F2331/2431/4331/4431
(Industrial, Extended)
Param
No.
D420B
D420C
Symbol
VLVD
VLVD
Characteristic
LVD Voltage on VDD Transition High-to-Low
D420F
VLVD
Legend:
Conditions
N/A
Reserved
N/A
N/A
N/A
Reserved
LVDL<3:0> = 0010
1.99
2.26
2.53
LVDL<3:0> = 0011
2.16
2.45
2.75
LVDL<3:0> = 0100
2.25
2.55
2.86
LVDL<3:0> = 0101
2.43
2.77
3.10
LVDL<3:0> = 0110
2.53
2.87
3.21
LVDL<3:0> = 0111
2.70
3.07
3.43
LVDL<3:0> = 1000
2.96
3.36
3.77
LVDL<3:0> = 1001
3.14
3.57
4.00
LVDL<3:0> = 1010
3.23
3.67
4.11
LVDL<3:0> = 1011
3.41
3.87
4.34
LVDL<3:0> = 1100
3.58
4.07
4.56
LVDL<3:0> = 1101
3.76
4.28
4.79
LVDL<3:0> = 1110
4.04
4.60
5.15
VLVD
Units
N/A
Max
LVDL<3:0> = 0001
LVDL<3:0> = 1110
VLVD
Typ
Min
4.28
4.62
4.23
4.60
4.96
4.28
4.79
4.04
4.60
5.15
3.94
4.28
4.62
LVDL<3:0> = 1110
4.23
4.60
4.96
Reserved
3.77
4.28
4.79
LVDL<3:0> = 1110
4.05
4.60
5.15
Reserved
DS39616D-page 343
PIC18F2331/2431/4331/4431
26.4
26.4.1
AC (Timing) Characteristics
TIMING PARAMETER SYMBOLOGY
DS39616D-page 344
3. TCC:ST
4. Ts
Time
osc
rd
rw
sc
ss
t0
t1
wr
OSC1
RD
RD or WR
SCK
SS
T0CKI
T1CKI
WR
P
R
V
Z
Period
Rise
Valid
High-Impedance
High
Low
High
Low
SU
Setup
STO
Stop condition
PIC18F2331/2431/4331/4431
26.4.2
TIMING CONDITIONS
Note:
TABLE 26-3:
AC CHARACTERISTICS
FIGURE 26-4:
Load Condition 1
VDD/2
RL
CL
Pin
VSS
CL
Pin
VSS
RL = 464
CL = 50 pF
DS39616D-page 345
PIC18F2331/2431/4331/4431
26.4.3
FIGURE 26-5:
Q1
Q2
Q3
Q4
Q1
OSC1
1
CLKO
TABLE 26-4:
Param.
No.
1A
Symbol
FOSC
Characteristic
Min
Max
Units
DC
40
MHz
EC, ECIO
DC
MHz
RC osc
0.1
MHz
XT osc
25
MHz
HS osc
10
MHz
HS + PLL osc
200
kHz
LP Osc mode
25
ns
EC, ECIO
250
ns
RC osc
250
10,000
ns
XT osc
25
100
250
250
ns
ns
HS osc
HS + PLL osc
25
LP osc
100
ns
TCY = 4/FOSC
30
ns
XT osc
2.5
LP osc
10
ns
HS osc
20
ns
XT osc
50
ns
LP osc
7.5
ns
HS osc
Oscillator Frequency
TOSC
(1)
Oscillator Period
Time(1)
TCY
Instruction Cycle
TosL,
TosH
Note 1:
TosR,
TosF
Conditions
Instruction cycle period (TCY) equals four times the input oscillator time base period for all configurations
except PLL. All specified values are based on characterization data for that particular oscillator type under
standard operating conditions with the device executing code. Exceeding these specified limits may result
in an unstable oscillator operation and/or higher than expected current consumption. All devices are tested
to operate at min. values with an external clock applied to the OSC1/CLKI pin. When an external clock
input is used, the max. cycle time limit is DC (no clock) for all devices.
DS39616D-page 346
PIC18F2331/2431/4331/4431
TABLE 26-5:
Param
No.
Sym
Characteristic
Min
Typ
Max
4
16
10
40
Units
F10
F11
F12
TPLL
ms
CLK
-2
+2
F13
Conditions
Data in Typ column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only
and are not tested.
TABLE 26-6:
INTERNAL RC ACCURACY
PIC18LF2331/2431/4331/4431
(Industrial)
PIC18F2331/2431/4331/4431
(Industrial)
Param
No.
Device
Min
Typ
Max
Units
Conditions
INTOSC Accuracy @ Freq = 8 MHz, 4 MHz, 2 MHz, 1 MHz, 500 kHz, 250 kHz, 125 kHz(1)
F2
PIC18LF2331/2431/4331/4431
-15
+/-5
+15
25C
VDD = 3.0V
F3
All devices
-15
+/-5
+15
25C
VDD = 5.0V
35.938
kHz
25C
VDD = 3.0V
35.938
kHz
25C
VDD = 5.0V
kHz(2)
PIC18LF2331/2431/4331/4431 26.562
All devices
26.562
DS39616D-page 347
PIC18F2331/2431/4331/4431
FIGURE 26-6:
Q4
Q2
Q3
OSC1
11
10
CLKO
13
14
19
12
18
16
I/O Pin
(Input)
15
17
I/O Pin
(Output)
New Value
Old Value
20, 21
TABLE 26-7:
Param
No.
Symbol
Characteristic
Min
Typ
Max
Units Conditions
10
75
200
ns
(Note 1)
11
75
200
ns
(Note 1)
12
TckR
35
100
ns
(Note 1)
13
TckF
35
100
ns
(Note 1)
0.5 TCY + 20
ns
(Note 1)
0.25 TCY + 25
ns
(Note 1)
(Note 1)
14
TckL2ioV
15
16
TckH2ioI
17
18
TosH2ioI
18A
ns
50
150
ns
PIC18FXX31
100
ns
PIC18LFXX31
200
ns
ns
PIC18FXX31
10
25
ns
PIC18LFXX31
60
ns
PIC18FXX31
10
25
ns
PIC18LFXX31
60
ns
19
20
TioR
20A
21
TioF
21A
22
TINP
TCY
ns
23
TRBP
TCY
ns
These parameters are asynchronous events not related to any internal clock edges.
Note 1: Measurements are taken in RC mode, where CLKO output is 4 x TOSC.
DS39616D-page 348
PIC18F2331/2431/4331/4431
FIGURE 26-7:
VDD
MCLR
30
Internal
POR
33
PWRT
Time-out
32
Oscillator
Time-out
Internal
Reset
Watchdog
Timer Reset
31
34
34
I/O Pins
FIGURE 26-8:
VDD
BVDD
35
VIRVST
VBGAP = 1.2V
(nominal)
Enable Internal
Reference Voltage
Internal Reference
Voltage Stable
36
DS39616D-page 349
PIC18F2331/2431/4331/4431
TABLE 26-8:
Param.
Symbol
No.
30
31
TMCL
TWDT
32
33
TOST
TPWRT
34
TIOZ
35
36
TBOR
TIRVST
37
38
39
TLVD
TCSD
TIOBST
Characteristic
MCLR Pulse Width (low)
Watchdog Timer Time-out Period
(no postscaler)
Oscillation Start-up Timer Period
Power-up Timer Period
I/O High-impedance from MCLR
Low or Watchdog Timer Reset
Brown-out Reset Pulse Width
Time for Internal Reference
Voltage to become Stable
Low-Voltage Detect Pulse Width
CPU Start-up Time
Time for INTOSC to Stabilize
DS39616D-page 350
Min
Typ
Max
Units
4.00
s
ms
65.5
ms
Conditions
200
20
50
s
s
200
10
1
s
s
ms
VDD VLVD
PIC18F2331/2431/4331/4431
FIGURE 26-9:
41
40
42
T1OSO/T1CKI
46
45
47
48
TMR0 or TMR1
TABLE 26-9:
Param
Symbol
No.
Characteristic
40
Tt0H
No prescaler
41
Tt0L
No prescaler
With prescaler
With prescaler
42
Tt0P
T0CKI Period
No prescaler
With prescaler
45
Tt1H
46
Tt1L
T1CKI
Low Time
Asynchronous
47
Tt1P
Ft1
0.5 TCY + 20
ns
ns
10
0.5 TCY + 20
ns
10
ns
TCY + 10
ns
Greater of:
20 ns or TCY + 40
N
ns
0.5 TCY + 20
ns
10
ns
ns
25
ns
PIC18LFXX31
50
ns
0.5 TCY + 5
ns
PIC18FXX31
10
ns
PIC18LFXX31
25
ns
PIC18FXX31
30
ns
PIC18LFXX31
50
ns
Greater of:
20 ns or TCY + 40
N
ns
60
ns
DC
50
kHz
2 TOSC
7 TOSC
Units
30
Asynchronous
48
Max
PIC18FXX31
Synchronous, no prescaler
Synchronous,
with prescaler
Min
Conditions
VDD = 2V
N = prescale value
(1, 2, 4,..., 256)
N = prescale value
(1, 2, 4, 8)
DS39616D-page 351
PIC18F2331/2431/4331/4431
FIGURE 26-10:
50
51
52
CCPx
(Compare or PWM Mode)
53
54
51
TccL
TccH
Characteristic
Min
Max
Units
0.5 TCY + 20
ns
10
ns
20
ns
0.5 TCY + 20
ns
10
ns
20
ns
3 TCY + 40
N
ns
52
TccP
53
TccR
54
TccF
DS39616D-page 352
PIC18FXX31
25
ns
PIC18LFXX31
45
ns
PIC18FXX31
25
ns
PIC18LFXX31
45
ns
Conditions
N = prescale
value (1, 4 or 16)
PIC18F2331/2431/4331/4431
FIGURE 26-11:
SCK
(CKP = 0)
78
79
79
78
SCK
(CKP = 1)
80
bit 6 - - - - - -1
MSb
SDO
LSb
75, 76
SDI
MSb In
bit 6 - - - -1
LSb In
74
73
Symbol
Characteristic
73
TdiV2scH,
TdiV2scL
73A
Tb2b
74
TscH2diL,
TscL2diL
75
TdoR
76
TdoF
78
TscR
PIC18FXX31
PIC18LFXX31
79
TscF
80
TscH2doV,
TscL2doV
Min
Max Units
20
ns
1.5 TCY + 40
ns
40
ns
25
ns
45
ns
25
ns
PIC18FXX31
25
ns
PIC18LFXX31
45
ns
25
ns
PIC18FXX31
50
ns
PIC18LFXX31
100
ns
Conditions
DS39616D-page 353
PIC18F2331/2431/4331/4431
FIGURE 26-12:
SCK
(CKP = 0)
79
73
SCK
(CKP = 1)
80
78
MSb
SDO
bit 6 - - - - - -1
LSb
bit 6 - - - -1
LSb In
75, 76
SDI
MSb In
74
Symbol
Characteristic
73
TdiV2scH,
TdiV2scL
73A
Tb2b
74
TscH2diL,
TscL2diL
75
TdoR
76
TdoF
78
TscR
79
TscF
80
TscH2doV,
TscL2doV
20
ns
1.5 TCY + 40
ns
40
ns
PIC18FXX31
25
ns
45
ns
25
ns
25
ns
PIC18FXX31
45
ns
25
ns
PIC18FXX31
50
ns
PIC18LFXX31
100
ns
TCY
ns
DS39616D-page 354
Max Units
PIC18LFXX31
PIC18LFXX31
81
Min
Conditions
PIC18F2331/2431/4331/4431
FIGURE 26-13:
SS
70
SCK
(CKP = 0)
83
71
72
SCK
(CKP = 1)
80
MSb
SDO
bit 6 - - - - - -1
LSb
77
75, 76
SDI
MSb In
bit 6 - - - -1
LSb In
74
73
Symbol
Characteristic
70
71
TscH
71A
72
TscL
72A
73
Min
TCY
ns
Continuous
1.25 TCY + 30
ns
Single byte
40
ns
Continuous
1.25 TCY + 30
ns
Single byte
40
ns
20
ns
73A
TB2B
ns
74
Last Clock Edge of Byte 1 to the First Clock Edge of Byte 2 1.5 TCY + 40
40
ns
75
TdoR
PIC18FXX31
25
ns
PIC18LFXX31
45
ns
76
TdoF
25
ns
77
10
50
ns
80
50
ns
100
ns
1.5 TCY + 40
ns
83
Note 1:
2:
(Note 1)
(Note 1)
(Note 2)
DS39616D-page 355
PIC18F2331/2431/4331/4431
FIGURE 26-14:
SS
SCK
(CKP = 0)
70
83
71
72
SCK
(CKP = 1)
80
MSb
SDO
bit 6 - - - - - -1
LSb
75, 76
SDI
77
bit 6 - - - -1
MSb In
LSb In
74
Symbol
Characteristic
Min
70
71
TscH
TscL
73A
TB2B
Last Clock Edge of Byte 1 to the First Clock Edge of Byte 2 1.5 TCY + 40
74
75
TdoR
76
TdoF
77
10
50
ns
80
PIC18FXX31
50
ns
PIC18LFXX31
100
ns
PIC18FXX31
50
ns
PIC18LFXX31
100
ns
1.5 TCY + 40
ns
71A
72
72A
TCY
ns
1.25 TCY + 30
ns
Single byte
40
ns
Continuous
1.25 TCY + 30
ns
Single byte
40
ns
(Note 1)
ns
(Note 2)
40
ns
25
ns
45
ns
25
ns
Continuous
PIC18FXX31
PIC18LFXX31
82
83
Note 1:
2:
(Note 1)
DS39616D-page 356
PIC18F2331/2431/4331/4431
FIGURE 26-15:
SCL
91
93
90
92
SDA
Stop
Condition
Start
Condition
Characteristic
90
TSU:STA
Start Condition
91
THD:STA
92
TSU:STO
93
Max
Units
4700
ns
ns
Setup Time
600
Start Condition
4000
Hold Time
600
Stop Condition
4000
Setup Time
Hold Time
FIGURE 26-16:
Min
600
4700
600
Conditions
ns
ns
102
100
101
SCL
90
106
107
91
92
SDA
In
110
109
109
SDA
Out
DS39616D-page 357
PIC18F2331/2431/4331/4431
TABLE 26-16: I2C BUS DATA REQUIREMENTS (SLAVE MODE)
Param.
No.
100
Symbol
THIGH
Characteristic
Clock High Time
Min
Max
Units
Conditions
4.0
0.6
1.5 TCY
4.7
1.3
SSP module
101
TLOW
1.5 TCY
1000
ns
20 + 0.1 CB
300
ns
300
ns
20 + 0.1 CB
300
ns
CB is specified to be from
10 to 400 pF
4.7
0.6
4.0
0.6
ns
0.9
250
ns
100
ns
4.7
0.6
3500
ns
ns
4.7
1.3
400
pF
SSP Module
102
TR
103
TF
90
TSU:STA
91
THD:STA
106
THD:DAT
107
TSU:DAT
92
TSU:STO
109
TAA
110
TBUF
D102
CB
Note 1:
2:
CB is specified to be from
10 to 400 pF
(Note 2)
(Note 1)
Time the bus must be free
before a new transmission can
start
As a transmitter, the device must provide this internal minimum delay time to bridge the undefined region (min. 300 ns)
of the falling edge of SCL to avoid unintended generation of Start or Stop conditions.
A Fast mode I2C bus device can be used in a Standard mode I2C bus system, but the requirement, TSU:DAT 250 ns,
must then be met. This will automatically be the case if the device does not stretch the LOW period of the SCL signal. If
such a device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line,.
TR max. + TSU:DAT = 1000 + 250 = 1250 ns (according to the Standard mode I2C bus specification), before the SCL line
is released.
DS39616D-page 358
PIC18F2331/2431/4331/4431
TABLE 26-17: SSP I2C BUS DATA REQUIREMENTS
Param.
No.
Symbol
Characteristic
Min
Max
Units
2(TOSC)(BRG + 1)
ms
100
THIGH
2(TOSC)(BRG + 1)
ms
101
TLOW
2(TOSC)(BRG + 1)
ms
2(TOSC)(BRG + 1)
ms
102
TR
1000
ns
20 + 0.1 CB
300
ns
103
TF
300
ns
20 + 0.1 CB
300
ns
90
TSU:STA
Start Condition
Setup Time
2(TOSC)(BRG + 1)
ms
2(TOSC)(BRG + 1)
ms
2(TOSC)(BRG + 1)
ms
91
2(TOSC)(BRG + 1)
ms
106
ns
0.9
ms
107
TSU:DAT
250
ns
100
ns
92
2(TOSC)(BRG + 1)
ms
2(TOSC)(BRG + 1)
ms
109
TAA
Output Valid
from Clock
3500
ns
1000
ns
110
TBUF
4.7
ms
1.3
ms
400
pF
D102 CB
Data Input
Setup Time
Conditions
CB is specified to be from
10 to 400 pF
CB is specified to be from
10 to 400 pF
Only relevant for
Repeated Start
condition
After this period, the first
clock pulse is generated
DS39616D-page 359
PIC18F2331/2431/4331/4431
FIGURE 26-17:
RC6/TX/CK/SS
Pin
121
121
RC7/RX/DT/SDO
Pin
120
122
Characteristic
121
Tckrf
122
Tdtrf
FIGURE 26-18:
Min
Max
Units
PIC18FXX31
40
ns
PIC18LFXX31
100
ns
PIC18FXX31
20
ns
PIC18LFXX31
50
ns
PIC18FXX31
20
ns
PIC18LFXX31
50
ns
Conditions
RC6/TX/CK/SS
Pin
125
RC7/RX/DT/SDO
Pin
126
Symbol
TdtV2ckl
TckL2dtl
DS39616D-page 360
Characteristic
Min
Max
Units
10
ns
15
ns
Conditions
PIC18F2331/2431/4331/4431
TABLE 26-20: A/D CONVERTER CHARACTERISTICS
PIC18LF2331/2431/4331/4431
(Industrial)
PIC18F2331/2431/4331/4431
(Industrial)
Param
Symbol
No.
Characteristic
Min
Typ
Max
Units
VDD + 0.3
Conditions
Device Supply
AVDD
VDD 0.3
AVSS
VSS 0.3
VSS + 0.3
IAD
Module Current
(during conversion)
500
250
A
A
IADO
1.0
VDD = 5V
VDD = 2.5V
AC Timing Parameters
A10
FTHR
Throughput Rate
200
75
ksps
ksps
A11
TAD
385
1000
20,000
20,000
ns
ns
VDD = 5V
VDD = 3V
A12
TRC
500
750
10000
1500
2250
20000
ns
ns
ns
PIC18F parts
PIC18LF parts
AVDD < 3.0V
A13
TCNV
Conversion Time(1)
12
12
12
TAD
A14
TACQ
Acquisition Time(2)
2(2)
TAD
A16
TTC
1/4 TCY
1.5
1.8
AVDD AVSS
AVDD AVSS
Reference Inputs
A20
VREF
V
V
VDD 3V
VDD < 3V
VDD 3V
A21
VREFH
1.5V
AVDD
A22
VREFL
AVSS
VREFH 1.5V
A23
IREF
Reference Current
150 A
75 A
VDD = 5V
VDD = 2.5V
VAIN
Input Voltage(3)
AVSS 0.3
AVDD + 0.3
A30
ZAIN
2.5
A31
ZCHIN
10.0
VDD = 3.0V
DC Performance
A41
NR
Resolution
A42
EIL
Integral Nonlinearity
<1
LSb
VDD 3.0V
VREFH 3.0V
A43
EIL
Differential Nonlinearity
<1
LSb
VDD 3.0V
VREFH 3.0V
A45
EOFF
Offset Error
0.5
<1.5
LSb
VDD 3.0V
VREFH 3.0V
A46
EGA
Gain Error
0.5
<1.5
LSb
VDD 3.0V
VREFH 3.0V
A47
Monotonicity(4)
VDD 3.0V
VREFH 3.0V
Note 1:
2:
3:
4:
10 bits
guaranteed
Conversion time does not include acquisition time. See Section 21.0 10-Bit High-Speed Analog-to-Digital Converter
(A/D) Module for a full discussion of acquisition time requirements.
In Sequential modes, TACQ should be 12 TAD or greater.
For VDD < 2.7V and temperature below 0C, VAIN should be limited to range < VDD/2.
The A/D conversion result never decreases with an increase in the input voltage and has no missing codes.
DS39616D-page 361
PIC18F2331/2431/4331/4431
NOTES:
DS39616D-page 362
PIC18F2331/2431/4331/4431
27.0
PACKAGING INFORMATION
27.1
Example
PIC18F2331-I/SP e3
1010017
XXXXXXXXXXXXXXXXX
XXXXXXXXXXXXXXXXX
YYWWNNN
28-Lead SOIC
Example
XXXXXXXXXXXXXXXXXXXX
XXXXXXXXXXXXXXXXXXXX
XXXXXXXXXXXXXXXXXXXX
YYWWNNN
28-Lead QFN
Example
XXXXXXXX
XXXXXXXX
YYWWNNN
18F2431
-I/ML e3
1010017
Legend: XX...X
Y
YY
WW
NNN
e3
Note:
PIC18F2431-E/SO e3
1010017
Customer-specific information
Year code (last digit of calendar year)
Year code (last 2 digits of calendar year)
Week code (week of January 1 is week 01)
Alphanumeric traceability code
Pb-free JEDEC designator for Matte Tin (Sn)
This package is Pb-free. The Pb-free JEDEC designator ( e3 )
can be found on the outer packaging for this package.
In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.
DS39616D-page 363
PIC18F2331/2431/4331/4431
27.1
Example
XXXXXXXXXXXXXXXXXX
XXXXXXXXXXXXXXXXXX
XXXXXXXXXXXXXXXXXX
YYWWNNN
44-Lead TQFP
XXXXXXXXXX
XXXXXXXXXX
XXXXXXXXXX
YYWWNNN
44-Lead QFN
XXXXXXXXXX
XXXXXXXXXX
XXXXXXXXXX
YYWWNNN
DS39616D-page 364
PIC18F4331-I/P e3
1010017
Example
PIC18F4431
-I/PT e3
1010017
Example
PIC18F4431
-I/ML e3
1010017
PIC18F2331/2431/4331/4431
27.2
Package Details
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PIC18F2331/2431/4331/4431
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
DS39616D-page 367
PIC18F2331/2431/4331/4431
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PIC18F2331/2431/4331/4431
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PIC18F2331/2431/4331/4431
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DS39616D-page 374
PIC18F2331/2431/4331/4431
APPENDIX A:
REVISION HISTORY
TABLE B-1:
APPENDIX B:
DEVICE
DIFFERENCES
DEVICE DIFFERENCES
Features
PIC18F2331
PIC18F2431
PIC18F4331
PIC18F4431
4096
8192
4096
8192
2048
4096
2048
4096
22
22
34
34
Interrupt Sources
I/O Ports
Capture/Compare/PWM Modules
Enhanced Capture/Compare/
PWM Modules
5 Input Channels
5 Input Channels
9 Input Channels
9 Input Channels
28-Pin SPDIP
28-Pin SOIC
28-Pin QFN
28-Pin SPDIP
28-Pin SOIC
28-Pin QFN
40-Pin PDIP
44-Pin TQFP
44-Pin QFN
40-Pin PDIP
44-Pin TQFP
44-Pin QFN
DS39616D-page 375
PIC18F2331/2431/4331/4431
APPENDIX C:
CONVERSION
CONSIDERATIONS
DS39616D-page 376
APPENDIX D:
MIGRATION FROM
BASELINE TO
ENHANCED DEVICES
PIC18F2331/2431/4331/4431
APPENDIX E:
MIGRATION FROM
MID-RANGE TO
ENHANCED DEVICES
APPENDIX F:
MIGRATION FROM
HIGH-END TO
ENHANCED DEVICES
DS39616D-page 377
PIC18F2331/2431/4331/4431
NOTES:
DS39616D-page 378
PIC18F2331/2431/4331/4431
INDEX
A
A/D .................................................................................... 239
Acquisition Requirements ......................................... 249
Associated Registers ................................................ 255
Calculating the Minimum Required
Acquisition Time ............................................... 250
Configuring................................................................ 247
Configuring Analog Port Pins.................................... 252
Conversions .............................................................. 253
Converter Characteristics ......................................... 361
Operation in Power-Managed Modes ....................... 252
Result Buffer ............................................................. 249
Selecting and Configuring Automatic
Acquisition Time ............................................... 251
Selecting the Conversion Clock ................................ 251
Special Event Trigger (CCP)..................................... 147
Voltage References .................................................. 251
Absolute Maximum Ratings .............................................. 329
AC (Timing) Characteristics .............................................. 344
Load Conditions for Device
Timing Specifications ........................................ 345
Parameter Symbology .............................................. 344
Temperature and Voltage Specifications .................. 345
Timing Conditions ..................................................... 345
ACK Pulse................................................................. 212, 214
ADDLW ............................................................................. 289
ADDWF ............................................................................. 289
ADDWFC .......................................................................... 290
Analog-to-Digital Converter. See A/D.
ANDLW ............................................................................. 290
ANDWF ............................................................................. 291
Application Notes
AN578 (Use of the SSP Module in the
I2C Multi-Master Environment) ......................... 205
Assembler
MPASM Assembler................................................... 326
Auto-Wake-up on Sync Break Character .......................... 231
B
BC ..................................................................................... 291
BCF ................................................................................... 292
BF Bit ................................................................................ 206
Block Diagrams
A/D ............................................................................ 246
Analog Input Model ................................................... 250
Capture Mode Operation .......................................... 146
Center Connected Load............................................ 194
Compare Mode Operation ........................................ 147
Dead-Time Control Unit for One
PWM Output Pair .............................................. 191
EUSART Receive ..................................................... 229
EUSART Transmit .................................................... 227
External Clock Input, EC............................................. 31
External Components for Timer1 LP Oscillator......... 133
External Power-on Reset Circuit
(Slow VDD Power-up).......................................... 49
Fail-Safe Clock Monitor............................................. 277
Generic I/O Port ........................................................ 113
Input Capture for IC1 ................................................ 153
Input Capture for IC2 and IC3................................... 154
Interrupt Logic ............................................................. 98
Low-Voltage Detect with External Input .................... 258
Motion Feedback Module.......................................... 152
C
C Compilers
MPLAB C18.............................................................. 326
CALL................................................................................. 298
Capture (CCP Module) ..................................................... 146
Associated Registers................................................ 148
CCP Pin Configuration ............................................. 146
CCPR1H:CCPR1L Registers ................................... 146
Prescaler .................................................................. 146
Software Interrupt ..................................................... 146
Timer1 Mode Selection............................................. 146
Capture/Compare/PWM (CCP) ........................................ 145
Capture Mode. See Capture.
CCP1 ........................................................................ 145
CCPR1H Register ............................................ 145
CCPR1L Register ............................................. 145
DS39616D-page 379
PIC18F2331/2431/4331/4431
CCP2 ........................................................................ 145
CCPR2H Register............................................. 145
CCPR2L Register ............................................. 145
Compare Mode. See Compare.
Timer Resources....................................................... 145
CKE Bit.............................................................................. 206
CKP Bit.............................................................................. 207
Clock Sources ..................................................................... 34
Effects of Power-Managed Modes .............................. 37
Selection Using OSCCON Register ............................ 34
Clocking Scheme/Instruction Cycle..................................... 65
CLRF................................................................................. 299
CLRWDT........................................................................... 299
Code Examples
Changing Between Capture Prescalers .................... 146
Computed GOTO Using an Offset Value .................... 64
Data EEPROM Read .................................................. 81
Data EEPROM Refresh Routine ................................. 82
Data EEPROM Write .................................................. 81
Erasing a Flash Program Memory Row ...................... 90
Fast Register Stack..................................................... 64
How to Clear RAM (Bank 1) Using
Indirect Addressing ............................................. 75
Implementing a Real-Time Clock Using a
Timer1 Interrupt Service ................................... 135
Initializing PORTA ..................................................... 113
Initializing PORTB ..................................................... 116
Initializing PORTC..................................................... 119
Initializing PORTD..................................................... 122
Initializing PORTE ..................................................... 124
Reading a Flash Program Memory Word ................... 89
Saving STATUS, WREG and BSR
Registers in RAM .............................................. 112
Writing to Flash Program Memory ........................ 9394
16 x 16 Signed Multiply Routine ................................. 96
16 x 16 Unsigned Multiply Routine ............................. 96
8 x 8 Signed Multiply Routine ..................................... 95
8 x 8 Unsigned Multiply Routine ................................. 95
Code Protection ........................................................ 263, 279
Associated Registers ................................................ 279
Data EEPROM .......................................................... 282
Program Memory ...................................................... 280
COMF................................................................................ 300
Compare (CCP Module).................................................... 147
Associated Registers ................................................ 148
CCP Pin Configuration .............................................. 147
CCPR1 Register ....................................................... 147
CCPR2 Register ....................................................... 147
Software Interrupt Mode ........................................... 147
Special Event Trigger................................................ 147
Timer1 Mode Selection ............................................. 147
Configuration Bits.............................................................. 263
Configuration Register Protection ..................................... 282
Conversion Considerations ............................................... 376
CPFSEQ ........................................................................... 300
CPFSGT............................................................................ 301
CPFSLT ............................................................................ 301
Crystal Oscillator/Ceramic Resonators ............................... 29
Customer Change Notification Service ............................. 387
Customer Notification Service........................................... 387
Customer Support ............................................................. 387
DS39616D-page 380
D
D/A Bit............................................................................... 206
Data Addressing Modes ..................................................... 75
Direct .......................................................................... 75
Indirect ........................................................................ 75
Inherent and Literal..................................................... 75
Data EEPROM Memory...................................................... 79
Associated Registers .................................................. 83
EEADR Register ......................................................... 79
EECON1 and EECON2 Registers .............................. 79
Operation During Code-Protect .................................. 82
Protection Against Spurious Write .............................. 81
Reading ...................................................................... 81
Using .......................................................................... 82
Write Verify ................................................................. 81
Writing ........................................................................ 81
Data Memory ...................................................................... 67
Access Bank ............................................................... 68
Bank Select Register (BSR) ....................................... 68
General Purpose Register (GPR) File ........................ 68
Map for PIC18F2331/2431/4331/4431 ....................... 67
Special Function Registers (SFRs)............................. 69
DAW ................................................................................. 302
DC Characteristics............................................................ 339
Power-Down and Supply Current ............................. 332
Supply Voltage ......................................................... 331
DCFSNZ ........................................................................... 303
DECF ................................................................................ 302
DECFSZ ........................................................................... 303
Development Support ....................................................... 325
Device Differences............................................................ 375
Device Overview................................................................. 11
Features (table) .......................................................... 13
New Core Features..................................................... 11
Other Special Features............................................... 12
Device Reset Timers
Oscillator Start-up Timer (OST) .................................. 50
PLL Lock Time-out...................................................... 50
Power-up Timer (PWRT) ............................................ 50
Time-out Sequence .................................................... 50
Direct Addressing ............................................................... 76
E
Electrical Characteristics .................................................. 329
Enhanced Universal Synchronous Asynchronous
Receiver Transmitter (EUSART) .............................. 217
Equations
A/D Acquisition Time ................................................ 249
Conversion Time for Multi-Channel Modes .............. 254
Minimum A/D Holding Capacitor Charging Time ...... 249
PWM Period for Free-Running Mode ....................... 185
PWM Period for Up/Down Count Mode .................... 185
PWM Resolution ....................................................... 185
16 x 16 Signed Multiplication Algorithm...................... 96
16 x 16 Unsigned Multiplication Algorithm.................. 96
Errata .................................................................................... 9
PIC18F2331/2431/4331/4431
EUSART
Asynchronous Mode ................................................. 226
Associated Registers, Receive ......................... 230
Associated Registers, Transmit ........................ 228
Auto-Wake-up on Sync Break .......................... 231
Receiver............................................................ 229
Receiving a Break Character ............................ 232
Setting Up 9-Bit Mode with Address Detect...... 229
Transmitter........................................................ 226
12-Bit Break Character Sequence .................... 232
Baud Rate Generator (BRG)..................................... 221
Associated Registers ........................................ 222
Auto-Baud Rate Detect ..................................... 225
Baud Rate Error, Calculating ............................ 222
Baud Rates, Asynchronous Modes .................. 222
High Baud Rate Select (BRGH Bit) .................. 221
Power-Managed Mode Operation..................... 221
Sampling ........................................................... 221
Serial Port Enable (SPEN Bit)................................... 217
Synchronous Master Mode ....................................... 233
Associated Registers, Receive ......................... 236
Associated Registers, Transmit ........................ 234
Reception.......................................................... 235
Transmission .................................................... 233
Synchronous Slave Mode ......................................... 237
Associated Registers, Receive ......................... 238
Associated Registers, Transmit ........................ 237
Reception.......................................................... 238
Transmission .................................................... 237
External Clock Input ............................................................ 31
F
Fail-Safe Clock Monitor............................................. 263, 277
Exiting ....................................................................... 277
Interrupts in Power-Managed Modes........................ 278
POR or Wake From Sleep ........................................ 278
WDT During Oscillator Failure .................................. 277
Fail-Safe Clock Monitor (FSCM) ....................................... 263
Fast Register Stack............................................................. 64
Flash Program Memory ...................................................... 85
Associated Registers .................................................. 94
Control Registers ........................................................ 86
EECON1 and EECON2 ...................................... 86
Erase Sequence ......................................................... 90
Erasing........................................................................ 90
Operation During Code-Protect .................................. 94
Reading....................................................................... 89
TABLAT Register ........................................................ 88
Table Pointer............................................................... 88
Boundaries Based on Operation......................... 88
Table Pointer Boundaries ........................................... 88
Table Reads and Table Writes ................................... 85
Unexpected Termination of Write Operation............... 94
Write Sequence .......................................................... 92
Write Verify ................................................................. 94
Writing......................................................................... 91
FSCM. See Fail-Safe Clock Monitor.
G
Getting Started .................................................................... 25
GOTO ............................................................................... 304
H
Hardware Multiplier............................................................. 95
Introduction................................................................. 95
Operation.................................................................... 95
Performance Comparison........................................... 95
I
I/O Ports ........................................................................... 113
ID Locations.............................................................. 263, 282
INCF ................................................................................. 304
INCFSZ............................................................................. 305
In-Circuit Debugger........................................................... 282
In-Circuit Serial Programming (ICSP)....................... 263, 282
Independent PWM Mode .................................................. 193
Duty Cycle Assignment ............................................ 193
Indirect Addressing ............................................................. 76
INFSNZ............................................................................. 305
Initialization Conditions for All Registers....................... 5459
Instruction Flow/Pipelining .................................................. 65
Instruction Set
ADDLW..................................................................... 289
ADDWF .................................................................... 289
ADDWFC.................................................................. 290
ANDLW..................................................................... 290
ANDWF .................................................................... 291
BC............................................................................. 291
BCF .......................................................................... 292
BN............................................................................. 292
BNC .......................................................................... 293
BNN .......................................................................... 293
BNOV ....................................................................... 294
BNZ .......................................................................... 294
BOV .......................................................................... 297
BRA .......................................................................... 295
BSF........................................................................... 295
BTFSC...................................................................... 296
BTFSS ...................................................................... 296
BTG .......................................................................... 297
BZ ............................................................................. 298
CALL......................................................................... 298
CLRF ........................................................................ 299
CLRWDT .................................................................. 299
COMF ....................................................................... 300
CPFSEQ ................................................................... 300
CPFSGT ................................................................... 301
CPFSLT.................................................................... 301
DAW ......................................................................... 302
DCFSNZ ................................................................... 303
DECF........................................................................ 302
DECFSZ ................................................................... 303
General Format ........................................................ 285
GOTO ....................................................................... 304
INCF ......................................................................... 304
INCFSZ..................................................................... 305
INFSNZ..................................................................... 305
IORLW ...................................................................... 306
IORWF...................................................................... 306
LFSR ........................................................................ 307
MOVF ....................................................................... 307
MOVFF ..................................................................... 308
MOVLB ..................................................................... 308
DS39616D-page 381
PIC18F2331/2431/4331/4431
MOVLW .................................................................... 309
MOVWF .................................................................... 309
MULLW ..................................................................... 310
MULWF ..................................................................... 310
NEGF ........................................................................ 311
NOP .......................................................................... 311
POP .......................................................................... 312
PUSH ........................................................................ 312
RCALL ...................................................................... 313
Read-Modify-Write Operations ................................. 283
RESET ...................................................................... 313
RETFIE ..................................................................... 314
RETLW ..................................................................... 314
RETURN ................................................................... 315
RLCF......................................................................... 315
RLNCF ...................................................................... 316
RRCF ........................................................................ 316
RRNCF ..................................................................... 317
SETF ......................................................................... 317
SLEEP ...................................................................... 318
SUBFWB................................................................... 318
SUBLW ..................................................................... 319
SUBWF ..................................................................... 319
SUBWFB................................................................... 320
Summary................................................................... 283
Summary Table......................................................... 286
SWAPF ..................................................................... 320
TBLRD ...................................................................... 321
TBLWT ...................................................................... 322
TSTFSZ .................................................................... 323
XORLW ..................................................................... 323
XORWF..................................................................... 324
INTCON Register
RBIF Bit..................................................................... 116
INTCON Registers .............................................................. 99
Inter-Integrated Circuit (I2C). See I2C Mode.
Internal Oscillator Block ...................................................... 32
Adjustment .................................................................. 32
INTIO Modes............................................................... 32
INTRC Output Frequency ........................................... 32
OSCTUNE Register .................................................... 32
Internal RC Oscillator
Use with WDT ........................................................... 274
Internet Address................................................................ 387
Interrupt Sources............................................................... 263
Capture Complete (CCP) .......................................... 146
Interrupt-on-Change (RB7:RB4) ............................... 116
INTx Pin .................................................................... 112
PORTB, Interrupt-on-Change ................................... 112
TMR0 ........................................................................ 112
TMR1 Overflow ......................................................... 131
TMR2 to PR2 Match (PWM) ............................. 136, 149
Interrupts ............................................................................. 97
Context Saving, During ............................................. 112
Interrupts, Enable Bits
CCP1 Enable (CCP1IE Bit)....................................... 146
Interrupts, Flag Bits
CCP1 Flag (CCP1IF Bit) ........................................... 146
CCP1IF Flag (CCP1IF Bit) ........................................ 147
CCP2IF Flag (CCP2IF Bit) ........................................ 147
Interrupt-on-Change (RB7:RB4) Flag
(RBIF Bit) .......................................................... 116
INTOSC, INTRC. See Internal Oscillator Block.
IORLW .............................................................................. 306
IORWF .............................................................................. 306
IPR Registers .................................................................... 108
DS39616D-page 382
I2C Mode
Operation .................................................................. 212
I2C Mode (SSP)
Addressing................................................................ 213
Associated Registers ................................................ 216
Master Mode............................................................. 216
Mode Selection ......................................................... 212
Multi-Master Mode .................................................... 216
Operation .................................................................. 212
Reception ................................................................. 214
Slave Mode............................................................... 212
SCL and SDA Pins ........................................... 212
Transmission ............................................................ 215
L
LFSR................................................................................. 307
Low-Voltage Detect .......................................................... 257
Applications .............................................................. 261
Associated Registers ................................................ 261
Characteristics .......................................................... 342
Current Consumption................................................ 259
Effects of a Reset ..................................................... 261
Operation .................................................................. 259
Operation During Sleep ............................................ 261
Setup ........................................................................ 259
Start-up Time ............................................................ 260
LVD. See Low-Voltage Detect.
M
Master Clear (MCLR).......................................................... 49
Memory Organization ......................................................... 61
Data Memory .............................................................. 67
Program Memory ........................................................ 61
Memory Programming Requirements............................... 341
MFM
Input Capture
Edge Capture Mode ......................................... 156
Entering and Timing ......................................... 159
IC Interrupts...................................................... 159
Pulse-Width Measurement Mode ..................... 157
Special Event Trigger (CAP1 Only) .................. 160
State Change.................................................... 158
Time Base Reset Summary.............................. 160
Timer5 Reset .................................................... 159
Input Capture (IC) Submode..................................... 153
Input Capture Mode
Period Measurement Mode .............................. 157
Noise Filters.............................................................. 169
Microchip Internet Web Site.............................................. 387
Migration From Baseline to Enhanced Devices................ 376
Migration From High-End to Enhanced Devices............... 377
Migration From Mid-Range to Enhanced Devices ............ 377
Motion Feedback Module (MFM) ...................................... 151
Associated Registers ................................................ 171
Summary of Features ............................................... 151
MOVF ............................................................................... 307
MOVFF ............................................................................. 308
MOVLB ............................................................................. 308
MOVLW ............................................................................ 309
MOVWF ............................................................................ 309
MPLAB ASM30 Assembler, Linker, Librarian ................... 326
MPLAB Integrated Development
Environment Software .............................................. 325
MPLAB PM3 Device Programmer .................................... 328
MPLAB REAL ICE In-Circuit Emulator System ................ 327
PIC18F2331/2431/4331/4431
MPLINK Object Linker/MPLIB Object Librarian ................ 326
MULLW ............................................................................. 310
MULWF ............................................................................. 310
N
NEGF ................................................................................ 311
NOP .................................................................................. 311
O
Opcode Field Descriptions ................................................ 284
Oscillator Configuration....................................................... 29
EC ............................................................................... 29
ECIO ........................................................................... 29
HS ............................................................................... 29
HSPLL......................................................................... 29
Internal Oscillator Block .............................................. 32
INTIO1 ........................................................................ 29
INTIO2 ........................................................................ 29
LP................................................................................ 29
RC............................................................................... 29
RCIO ........................................................................... 29
XT ............................................................................... 29
Oscillator Selection ........................................................... 263
Oscillator Start-up Timer (OST) .................................. 37, 263
Oscillator Switching............................................................. 34
Oscillator Transitions .......................................................... 37
Oscillator, Timer1 .............................................................. 131
P
P (Stop) Bit........................................................................ 206
Packaging Information ...................................................... 363
Details ....................................................................... 365
Marking ..................................................................... 363
PIE Registers .................................................................... 105
Pin Diagrams ........................................................................ 4
Pin Functions
MCLR/VPP................................................................... 16
MCLR/VPP/RE3........................................................... 19
OSC1/CLKI/RA7 ................................................... 16, 19
OSC2/CLKO/RA6 ................................................. 16, 19
RA0/AN0 ............................................................... 16, 20
RA1/AN1 ............................................................... 16, 20
RA2/AN2/VREF-/CAP1/INDX................................. 16, 20
RA3/AN3/VREF+/CAP2/QEA................................. 16, 20
RA4/AN4/CAP3/QEB ............................................ 16, 20
RA5/AN5/LVDIN ......................................................... 20
RB0/PWM0 ........................................................... 17, 21
RB1/PWM1 ........................................................... 17, 21
RB2/PWM2 ........................................................... 17, 21
RB3/PWM3 ........................................................... 17, 21
RB4/KBIO/PWM5........................................................ 17
RB4/KBI0/PWM5 ........................................................ 21
RB5/KBI1/PWM4/PGM ......................................... 17, 21
RB6/KBI2/PGC ..................................................... 17, 21
RB7/KBI3/PGD ..................................................... 17, 21
RC0/T1OSO/T1CKI .............................................. 18, 22
RC1/T1OSI/CCP2/FLTA ....................................... 18, 22
RC2/CCP1 .................................................................. 18
RC2/CCP1/FLTB ........................................................ 22
RC3/T0CKI/T5CKI/INT0........................................ 18, 22
RC4/INT1/SDI/SDA............................................... 18, 22
RC5/INT2/SCK/SCL.............................................. 18, 22
RC6/TX/CK/SS ..................................................... 18, 22
RC7/RX/DT/SDO .................................................. 18, 22
RD0/T0CKI/T5CKI ...................................................... 23
RD1/SDO .................................................................... 23
RD2/SDI/SDA ............................................................. 23
RD3/SCK/SCL ............................................................ 23
RD4/FLTA................................................................... 23
RD5/PWM4................................................................. 23
RD6/PWM6................................................................. 23
RD7/PWM7................................................................. 23
RE0/AN6..................................................................... 24
RE1/AN7..................................................................... 24
RE2/AN8..................................................................... 24
VDD ....................................................................... 18, 24
VSS ....................................................................... 24, 18
Pinout I/O Descriptions
PIC18F2331/2431 ...................................................... 16
PIC18F4331/4431 ...................................................... 19
PIR Registers.................................................................... 102
PLL
HSPLL Mode .............................................................. 30
Multiplier ..................................................................... 30
POP .................................................................................. 312
POR. See Power-on Reset.
PORTA
Associated Registers................................................ 115
LATA Register .......................................................... 113
PORTA Register....................................................... 113
TRISA Register......................................................... 113
PORTB
Associated Registers................................................ 118
LATB Register .......................................................... 116
PORTB Register....................................................... 116
RB7:RB4 Interrupt-on-Change Flag (RBIF Bit) ........ 116
TRISB Register......................................................... 116
PORTC
Associated Registers................................................ 121
LATC Register .......................................................... 119
PORTC Register....................................................... 119
TRISC Register ........................................................ 119
PORTD
Associated Registers................................................ 123
LATD Register .......................................................... 122
PORTD Register....................................................... 122
TRISD Register ........................................................ 122
PORTE
Associated Registers................................................ 125
LATE Register .......................................................... 124
PORTE Register....................................................... 124
TRISE Register......................................................... 124
Postscaler, WDT
Assignment (PSA Bit) ............................................... 129
Rate Select (T0PS2:T0PS0 Bits).............................. 129
Power-Managed Modes...................................................... 39
Clock Sources ............................................................ 39
Clock Transitions and Status Indicators ..................... 40
Entering ...................................................................... 39
Exiting Idle and Sleep Modes ..................................... 45
By Interrupt ......................................................... 45
By Reset ............................................................. 45
By WDT Time-out ............................................... 45
Without an Oscillator Start-up Delay .................. 46
Idle Modes .................................................................. 43
PRI_IDLE ........................................................... 44
RC_IDLE ............................................................ 45
SEC_IDLE .......................................................... 44
Multiple Sleep Commands.......................................... 40
DS39616D-page 383
PIC18F2331/2431/4331/4431
Run Modes.................................................................. 40
PRI_RUN ............................................................ 40
RC_RUN ............................................................. 41
SEC_RUN........................................................... 40
Selecting ..................................................................... 39
Sleep Mode ................................................................. 43
Summary (table) ......................................................... 39
Power-on Reset (POR) ............................................... 49, 263
Power-up Delays................................................................. 37
Power-up Timer (PWRT)............................................. 37, 263
Prescaler, Timer0.............................................................. 129
Assignment (PSA Bit) ............................................... 129
Rate Select (T0PS2:T0PS0 Bits) .............................. 129
Prescaler, Timer2.............................................................. 150
PRI_IDLE Mode .................................................................. 44
PRI_RUN Mode .................................................................. 40
Program Counter (PC) ........................................................ 62
Program Memory
Instructions.................................................................. 66
Two-Word ........................................................... 66
Interrupt Vector ........................................................... 61
Map and Stack
PIC18F2331/4331............................................... 61
PIC18F2431/4431............................................... 61
Reset Vector ............................................................... 61
Program Verification.......................................................... 279
Pulse-Width Modulation. See PWM (CCP Module).
PUSH ................................................................................ 312
PUSH and POP Instructions ............................................... 64
PWM
Associated Registers ................................................ 203
Complementary Operation ........................................ 190
Control Registers ...................................................... 176
Dead-Time Generators ............................................. 191
Duty Cycle................................................................. 187
Center-Aligned .................................................. 189
Comparison....................................................... 187
Edge-Aligned .................................................... 188
Register Buffers ................................................ 188
Registers........................................................... 187
Fault Inputs ............................................................... 199
Functionality .............................................................. 176
Modes
Continuous Up/Down Count ............................. 180
Free-Running .................................................... 180
Single-Shot ....................................................... 180
Output and Polarity Control....................................... 198
Output Override ........................................................ 194
Single-Pulse Operation ............................................. 194
Special Event Trigger................................................ 202
Time Base ................................................................. 176
Interrupts........................................................... 181
Continuous Up/Down
Count Mode ...................................... 182
Double Update Mode ................................ 184
Free-Running Mode .................................. 181
Single-Shot Mode ..................................... 182
Postscaler ......................................................... 181
Prescaler........................................................... 180
Update Lockout ......................................................... 202
DS39616D-page 384
Q
Q Clock ............................................................................. 150
QEI
and IC Shared Interrupts .......................................... 170
Configuration ............................................................ 162
Direction of Rotation ................................................. 163
Interrupts .................................................................. 164
Operation .................................................................. 163
Operation in Sleep Mode .......................................... 170
3x Input Capture ............................................... 170
Sampling Modes ....................................................... 163
Velocity Measurement .............................................. 167
Quadrature Encoder Interface (QEI)................................. 161
R
R/W Bit...................................................... 206, 213, 214, 215
RAM. See Data Memory.
RC Oscillator....................................................................... 31
RCIO Oscillator Mode................................................. 31
RC_IDLE Mode................................................................... 45
RC_RUN Mode................................................................... 41
RCALL .............................................................................. 313
RCSTA Register
SPEN Bit................................................................... 217
Reader Response............................................................. 388
Registers
ADCHS (A/D Channel Select) .................................. 244
ADCON0 (A/D Control 0).......................................... 240
ADCON1 (A/D Control 1).......................................... 241
ADCON2 (A/D Control 2).......................................... 242
ADCON3 (A/D Control 3).......................................... 243
ANSEL0 (Analog Select 0) ....................................... 245
ANSEL1 (Analog Select 1) ....................................... 245
BAUDCON (Baud Rate Control)............................... 220
CAPxCON (Input Capture x Control) ........................ 155
CCPxCON (CCPx Control) ....................................... 145
CONFIG1H (Configuration 1 High) ........................... 264
CONFIG2H (Configuration 2 High) ........................... 266
CONFIG2L (Configuration 2 Low) ............................ 265
CONFIG3H (Configuration 3 High) ........................... 268
CONFIG3L (Configuration 3 Low) ............................ 267
CONFIG4L (Configuration 4 Low) ............................ 269
CONFIG5H (Configuration 5 High) ........................... 270
CONFIG5L (Configuration 5 Low) ............................ 270
CONFIG6H (Configuration 6 High) ........................... 271
CONFIG6L (Configuration 6 Low) ............................ 271
CONFIG7H (Configuration 7 High) ........................... 272
CONFIG7L (Configuration 7 Low) ............................ 272
DEVID1 (Device ID 1)............................................... 273
PIC18F2331/2431/4331/4431
DEVID2 (Device ID 2) ............................................... 273
DFLTCON (Digital Filter Control) .............................. 169
DTCON (Dead-Time Control) ................................... 192
EECON1 (Data EEPROM Control 1) .......................... 87
EECON1 (EEPROM Control 1)................................... 80
FLTCONFIG (Fault Configuration)............................ 201
INTCON (Interrupt Control)......................................... 99
INTCON2 (Interrupt Control 2).................................. 100
INTCON3 (Interrupt Control 3).................................. 101
IPR1 (Peripheral Interrupt Priority 1)......................... 108
IPR2 (Peripheral Interrupt Priority 2)......................... 109
IPR3 (Peripheral Interrupt Priority 3)......................... 110
LVDCON (Low-Voltage Detect Control).................... 257
OSCCON (Oscillator Control) ..................................... 36
OSCTUNE (Oscillator Tuning) .................................... 33
OVDCOND (Output Override Control) ...................... 196
OVDCONS (Output State) ........................................ 196
PIE1 (Peripheral Interrupt Enable 1)......................... 105
PIE2 (Peripheral Interrupt Enable 2)......................... 106
PIE3 (Peripheral Interrupt Enable 3)......................... 107
PIR1 (Peripheral Interrupt Request (Flag) 1) ............ 102
PIR2 (Peripheral Interrupt Request (Flag) 2) ............ 103
PIR3 (Peripheral Interrupt Request (Flag) 3) ............ 104
PTCON0 (PWM Timer Control 0) ............................. 178
PTCON1 (PWM Timer Control 1) ............................. 178
PWMCON0 (PWM Control 0) ................................... 179
PWMCON1 (PWM Control 1) ................................... 180
QEICON (QEI Control).............................................. 162
RCON (Reset Control) ........................................ 48, 111
RCSTA (Receive Status and Control)....................... 219
SSPCON (SSP Control)............................................ 207
SSPSTAT (SSP Status)............................................ 206
STATUS...................................................................... 74
STKPTR (Stack Pointer) ............................................. 63
Summary............................................................... 7073
TRISE ....................................................................... 124
TXSTA (Transmit Status and Control) ...................... 218
T0CON (Timer0 Control)........................................... 127
T1CON (Timer1 Control)........................................... 131
T2CON (Timer2 Control)........................................... 136
T5CON (Timer5 Control)........................................... 139
WDTCON (Watchdog Timer Control) ....................... 275
RESET .............................................................................. 313
Reset................................................................................... 47
Resets ............................................................................... 263
RETFIE ............................................................................. 314
RETLW ............................................................................. 314
RETURN ........................................................................... 315
Return Address Stack ......................................................... 62
Return Stack Pointer (STKPTR) ......................................... 62
Revision History ................................................................ 375
RLCF................................................................................. 315
RLNCF .............................................................................. 316
RRCF ................................................................................ 316
RRNCF ............................................................................. 317
S
S (Start) Bit ....................................................................... 206
SCK................................................................................... 205
SCL ................................................................................... 212
SDI .................................................................................... 205
SDO .................................................................................. 205
SEC_IDLE Mode................................................................. 44
SEC_RUN Mode ................................................................. 40
Serial Clock (SCK) Pin ...................................................... 205
Serial Data In (SDI) Pin..................................................... 205
T
TABLAT Register................................................................ 88
Table Pointer Operations (table)......................................... 88
TBLPTR Register................................................................ 88
TBLRD .............................................................................. 321
TBLWT ............................................................................. 322
Time-out in Various Situations (table)................................. 50
Timer0 .............................................................................. 127
Associated Registers................................................ 129
Clock Source Edge Select (T0SE Bit) ...................... 129
Clock Source Select (T0CS Bit) ............................... 129
Interrupt .................................................................... 129
Operation.................................................................. 129
Prescaler .................................................................. 129
Switching Assignment ...................................... 129
Prescaler. See Prescaler, Timer0.
16-Bit Mode Timer Reads and Writes ...................... 129
Timer1 .............................................................................. 131
Associated Registers................................................ 135
Interrupt .................................................................... 134
Operation.................................................................. 132
Oscillator........................................................... 131, 133
Layout Considerations...................................... 133
Overflow Interrupt ..................................................... 131
Resetting, Using a Special Event Trigger
Output (CCP).................................................... 134
Special Event Trigger (CCP) .................................... 147
TMR1H Register....................................................... 131
TMR1L Register ....................................................... 131
Use as a Real-Time Clock (RTC) ............................. 134
16-Bit Read/Write Mode ........................................... 134
DS39616D-page 385
PIC18F2331/2431/4331/4431
Timer2 ............................................................................... 136
Associated Registers ................................................ 137
Interrupt..................................................................... 137
Operation .................................................................. 136
Postscaler. See Postscaler, Timer2.
Prescaler. See Prescaler, Timer2.
PR2 Register............................................................. 136
SSP Clock Shift................................................. 136, 137
TMR2 Register .......................................................... 136
TMR2 to PR2 Match Interrupt ........................... 136, 149
Timer5 ............................................................................... 139
Associated Registers ................................................ 143
Interrupt..................................................................... 142
Noise Filter ................................................................ 142
Operation .................................................................. 140
Continuous Count and Single-Shot................... 141
Sleep Mode....................................................... 142
Prescaler ................................................................... 141
Special Event Trigger
Output ............................................................... 142
Reset Input........................................................ 142
16-Bit Read/Write and Write Modes ......................... 141
16-Bit Read-Modify-Write.......................................... 141
Timing Diagrams
Automatic Baud Rate Calculation ............................. 225
Auto-Wake-up Bit (WUE) During
Normal Operation.............................................. 231
Auto-Wake-up Bit (WUE) During Sleep .................... 231
Brown-out Reset (BOR) ............................................ 349
Capture/Compare/PWM (All CCP Modules) ............. 352
CAPx Interrupts and IC1 Special Event Trigger........ 159
CLKO and I/O ........................................................... 348
Clock, Instruction Cycle .............................................. 65
Dead-Time Insertion for Complementary PWM ........ 191
Duty Cycle Update Times in Continuous
Up/Down Count Mode....................................... 188
Duty Cycle Update Times in Continuous
Up/Down Count Mode with
Double Updates ................................................ 189
Edge Capture Mode .................................................. 156
Edge-Aligned PWM................................................... 188
EUSART Asynchronous Reception .......................... 230
EUSART Asynchronous Transmission ..................... 227
EUSART Asynchronous Transmission
(Back to Back)................................................... 227
EUSART Synchronous Receive (Master/Slave) ....... 360
EUSART Synchronous Reception
(Master Mode, SREN)....................................... 235
EUSART Synchronous Transmission ....................... 233
EUSART Synchronous Transmission
(Through TXEN)................................................ 234
EUSART SynchronousTransmission
(Master/Slave)................................................... 360
Example SPI Master Mode (CKE = 0) ...................... 353
Example SPI Master Mode (CKE = 1) ...................... 354
Example SPI Slave Mode (CKE = 0) ........................ 355
Example SPI Slave Mode (CKE = 1) ........................ 356
External Clock (All Modes Except PLL) .................... 346
Fail-Safe Clock Monitor............................................. 278
Input Capture on State Change, Hall Effect
Sensor Mode.................................................... 158
I2C Bus Data ............................................................. 357
I2C Bus Start/Stop Bits.............................................. 357
I2C Reception (7-Bit Address)................................... 214
I2C Transmission (7-Bit Address) ............................. 215
DS39616D-page 386
PIC18F2331/2431/4331/4431
Example SPI Mode Requirements
(Slave Mode, CKE = 0) ..................................... 355
Example SPI Slave Mode Requirements
(CKE = 1) .......................................................... 356
External Clock Requirements ................................... 346
Internal RC Accuracy ................................................ 347
I2C Bus Data Requirements (Slave Mode) ............... 358
I2C Bus Start/Stop Bits Requirements
(Slave Mode) .................................................... 357
PLL Clock.................................................................. 347
Reset, Watchdog Timer, Oscillator Start-up
Timer, Power-up Timer and Brown-out
Reset Requirements ......................................... 350
SSP I2C Bus Data Requirements ............................. 359
Timer0 and Timer1 External Clock
Requirements ................................................... 351
Top-of-Stack Access ........................................................... 62
TSTFSZ ............................................................................ 323
Two-Speed Start-up .................................................. 263, 276
Two-Word Instructions
Example Cases........................................................... 66
TXSTA Register
BRGH Bit .................................................................. 221
T0CON Register
PSA Bit...................................................................... 129
T0CS Bit.................................................................... 129
T0PS2:T0PS0 Bits .................................................... 129
T0SE Bit.................................................................... 129
U
UA Bit ............................................................................... 206
W
Watchdog Timer (WDT)............................................ 263, 274
Associated Registers................................................ 275
Control Register........................................................ 274
During Oscillator Failure ........................................... 277
Programming Considerations ................................... 274
WWW Address ................................................................. 387
WWW, On-Line Support ....................................................... 9
X
XORLW ............................................................................ 323
XORWF ............................................................................ 324
DS39616D-page 387
PIC18F2331/2431/4331/4431
NOTES:
DS39616D-page 388
PIC18F2331/2431/4331/4431
THE MICROCHIP WEB SITE
CUSTOMER SUPPORT
Distributor or Representative
Local Sales Office
Field Application Engineer (FAE)
Technical Support
Development Systems Information Line
Customers
should
contact
their
distributor,
representative or field application engineer (FAE) for
support. Local sales offices are also available to help
customers. A listing of sales offices and locations is
included in the back of this document.
Technical support is available through the web site
at: http://support.microchip.com
DS39616D-page 389
PIC18F2331/2431/4331/4431
READER RESPONSE
It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip
product. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our
documentation can better serve you, please FAX your comments to the Technical Publications Manager at
(480) 792-4150.
Please list the following information, and use this outline to provide us with your comments about this document.
TO:
RE:
Reader Response
From: Name
Company
Address
City / State / ZIP / Country
Telephone: (_______) _________ - _________
Application (optional):
Would you like a reply?
Device: PIC18F2331/2431/4331/4431
Questions:
1. What are the best features of this document?
2. How does this document meet your hardware and software development needs?
3. Do you find the organization of this document easy to follow? If not, why?
4. What additions to the document do you think would enhance the structure and subject?
5. What deletions from the document could be made without affecting the overall usefulness?
DS39616D-page 390
PIC18F2331/2431/4331/4431
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
PART NO.
/XX
XXX
Device
Temperature
Range
Package
Pattern
Examples:
a)
b)
Device
PIC18F2331/2431/4331/4431(1),
PIC18F2331/2431/4331/4431T(1,2);
VDD range 4.2V to 5.5V
c)
PIC18LF2331/2431/4331/4431(1),
PIC18LF2331/2431/4331/44310T(1,2);
VDD range 2.0V to 5.5V
Temperature
Range
I
E
=
=
Package
PT
SO
SP
P
ML
=
=
=
=
=
Pattern
Note 1:
2:
DS39616D-page 391
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08/04/10
DS39616D-page 392