Architecture, Programming and Development Tools

ARM
Architecture, Programming
and
Development Tools
Lesson 3
ARM CPU32 bit ARM and
16-bit Thumb Instruction Sets
"Microcontrollers....", Raj Kamal,

from Pearson Education, 2005
Outline
Basic Features
32-bit
Instruction Set
Thumb 16-bit Instruction Set
Inter-working with ARM/Thumb sets

ARM
code size small than other

RISCs
32-bit un-segmented memory

Basic Programming Features Processor
can operate on the words

as per initialization.
A word alignment can in big
endian [least significant byte stored
as higher bits (address 3) of a
word] or little endian [least
significant byte stored as lower bits
(address 0) of a word].
Data Types support

8-bit
byte,
16-bit half-word data types
half-words are aligned on 2byte boundaries
32-bit data types- words are
aligned on 4-byte boundaries
Little Endian Mode
Address
Half word
Address0 Byte0 (LSB)

Address1 byte1 (MSB)
Word
Byte3 (MSB)
byte2
byte1
Byte0 (LSB)
Byte
Address0
Address1
Address2
Address3
Address0- even address; Address1- odd address
Three DataType options

Big Endian Mode
Address
Half word
Address0 byte1 (MSB)

Address1 Byte0 (LSB)
Word
Byte3 (MSB)
byte2
byte1
byte0 (LSB)
Byte
Address0
Address1
Address2
Address3
Address0- even address; Address1- odd address
Three DataType options

Programming Model
16
general-purpose registers
with program counter as one of
the register (R15).

- Registers
R0 R1 R2 R3 R4 R5 R6 R7 Lo
R8registers
R9 R10 R11 R12 Hi registers
SP (R13) Stack Pointer

LR (R14) Link Register
PC (Rr15) Program Counter
CPSR
SPSR

10
CPSR and SPSR

CPSR
(Conditions and Processor

Status Register)
SPSR ( Saved Program Status
Register) Saves Program Status
Register from CPSR on branch and
link (routine call) and SPSR can be
stacked for each processor mode
11
Outline
Basic
Features
32-bit Instruction Set

12
Load Instructions
LDM:
Load multiple registers

LDR: Load a register (32 bit)
LDRB: Load a byte (8 bit) into
register

13
Load Instructions (in certain variants

e.g. ARM7500, StrongARM)
LFM:
Load multiple floating point

values - ARM7500
LDRSB: Load a signed byte (8 bit)
into register
Load a half-word (16 bit) into
register (in certain variants e.g.
StrongARM)
14
Store Instructions
STM:
Store multiple registers

STR: Store a register (32 bit)
STRB: Store a byte (8 bit) from a
register

15
Store Instructions (in certain variants

e.g. ARM7500, StrongARM)
SFM:
Store Multiple Floating

point values- ARM7500
STRSB: Store a signed byte from a
register- StrongARM
STRSH: Store a signed half-word
from a register- StrongARM
16
Load-store architecture
Features
LDM/STM with multiple options
of addressing modes (like
immediate)
LDM/STM loads into a subset of
registers in a list or save from the
list to the memory addresses
17
Data Transfer Instructions

MOV:
Move value/register into a

register
MRC: Co-processor register
transfer (co-processor to ARM)
MVN: Move after negation

18
ARM Arithmetic
Instructions
ADD
ADC
BIC
A select
Add with Carry bit
clear
Subtract with carry
SUB: Subtract
MAC unit
Support
SBC
and
SUB
MUL
32x32
and
MULL
MLA
and
MLAL
multiply
(32 x 32 32)
with add
instruction
(32 x 32 64) multiply
multiply long
(32 x 32 64)
long
19
and add instruction.
Arithmetic Instructions
ADC:
Add with Carry, ADD:Add

SBC: Subtract with carry , SUB:
Subtract
RSC: Reverse Subtract with carry ,
RSB: Reverse Subtract
BIC: A select bit Clear
20
MUL and DIV Instructions..

UMULL:
Unsigned Long (64 bit)

Multiply- StrongARM
DVF:
Divide floating Point-
ARM7500

21
MAC unit Support

MLA
and MLAL implement DSP

instructions
UMLAL: Unsigned Long (64 bit)
Multiply with Accumulate-Strong
ARM
22
ARM Logic
Instructions
AND
ORR
Hypothetical
AND
TST
Test
bits
CMN
TEQ
CMP
Compare negated
values
EOR
Exclusive
OR
Test Equivalence
(Hypothetical EOR)
(Hypothetical
SUB)
23
Logical Instructions..
Logical
AND, ORR, EOR

TST: Test bits (Hypothetical AND)
TEQ: Test Equivalence
(Hypothetical EOR)
CMP: Compare values
(Hypothetical SUB), CMN:
Compare negated values
24
Program Flow Control

B:
Branch
BL: Branch with Link

25
Interrupt Control Instruction

SWI<suffix>
<number>
SWI: cond SWI (8 msbs) remaining 24
bit lsbs are irrelevant as far as
execution of the instruction is
concerned.
Interrupt handler can use the 24-bits
for the suffix parameter (s) and
number to reflect the interrupting
foreground program (source of SWI).
26
Lets the OS including Device

Drivers, have a modular
structure
SWI
<suffix>
<number>
The code required to create a

complete operating system spliced
into a number of small parts
(modules) and a module handler
specifies by <number>
The handler executes
after passing any data
through use of <suffix>
27
ARM32-bit Instruction Set Features

Data processing, data transfer and

control flow execute with several
settable options
Implementation of many instructions by just a few instructions at the set
CPU instruction decoder decodes
instruction as per chosen options
28
ARM32-bit Instruction Option fields

Conditional
or no-condition 4-bit field

inmost instructions - facilitates
implementation of many conditional
instructions
After cond option, there are option fields
like addressing mode, shift or rotate
option, flag change fields
29
32-bit Instruction Format

Cond Opcode X- Opcode S- Rn Rd
44-bits major Bit Minor
Bit 4-bits 4-bits Bits
4-bits
2-bits
flag change
field
Source
operand 2
8-bits
Destination
Option Field
Refer Next
Slide
Refer Next Slide
Bits 31-0
30
Instruction Format
cond
00 X opcode S Rn Rd
operand 2
S specifies CPSR flags change or no

change by the operation
31
If
X =1 then b11-b8 specifies

rotate right instruction and b7-b0
immediate operand. b11-b8 =
0000 means no rotation, b11-b8 =
0001 means rotate right 2 times,
b11-b8 = 1111 means ROR 30
times. Immediate operand is32-bit
with 24 msbs = 0s
32
Second
source operand can also be

shifted or rotated before using the
source in the operations.
Flags (N, Z, C and V)can be changed
or unchanged as per S bit in the
instruction. Move can be conditional
or unconditional as per cond 4-bit
field in the instruction
33
Outline
Basic
Features

34
- Thumb16 bit subset

Better
code density than 32-bit

architecture instruction set

35
Programming Model
8
general-purpose Lower set of

registers permit 3-bit in the
instruction for a register
Program counter register (R15)
Link Register (R14)
Stack Pointer (R13)
36
16-bit Thumb Instruction Set

Features
Code
size small than 32-bit instruction

Most instructions - data processing, data
transfer and control flow execute with nocondition field
3-bit for Lower set register facilitates
implementation with 16-bit instruction
37
Instructions Examples LDMIA:Thumb:
Store multiple
registers
LDR: Load register (32 bits?)
LDRB:Load byte (8 bit) into
register
LDRH: Load half-word (!)into
register
38
Contd
LDRSB:
oad signed byte (sign

+ 7 bit) into registe
LDRSH: Load signed half-word
(sign + 15 bit) into register

39
Contd
STMIA:Thumb:
Store multiple
registers
STR: Store register (32 bit?)
STRB:Store byte (8 bit)
STRH: Store half-word (16 bit)
40
Data Transfer Instructions

MOV:
Move value/register into a

register
MVN: Move after negation
PUSH: registers to stack
POP: registers from stack

41
Thumb Arithmetic
Instructions
ADD
ADC
BIC
A select
Add with Carry bit
clear
SBC
and
SUB
Subtract with carry

SUB: Subtract
MUL
NEG
multiply
By -1
multiply long
(32 x 32 64)

42
Thumb Logic
Instructions
AND
OR
TST
Test
bits
CMN
Hypothetical
AND
CMP
EOR
Exclusive
OR
(Hypothetical
SUB)
Compare negated
values
43
Program Flow Control

NOP:
No operation,
B: Branch, BX: Branch and
Exchange
BL: Long Branch with Link (LR
and PC exchange), BLX:Branch
with Link and Exchange
BKPT: Breakpoint
44
Interrupt Control Instruction

SWI:
cond SWI (8 msbs) remaining 8

bit lsbs are irrelevant as far as
execution of the instruction is
concerned. However, the handler can
use the 4-bits for the suffix parameter
and a number of 4-bits to reflect the
interrupting foreground program
(source of SWI).
45
16-bit Thumb Instruction Format

Opcode X- Opcode Rd
operand
major Bit Minor
3-bits 8-bits
2-bits
2-bits
Immediate
Operand
if X=1
Destination
cum Source
Register
or Rm
Rn Rd or other options
For Index
Bits 15-0
46
Instruction Example
ADD
r4, #data8 16-bit instruction

in memory decompressed at run
time into 32-bit format will be
1110 (condition code) 011 01001
(minor opcode) 0 (S bit) 01000 (S
bit) 0100 0000 (rotation) 1000
0000.
47
Outline
Basic
Features

48
ARM/THUMB Inter-working
T-bit
at CPSR support for interworking with 16-bit Thumb set and

32-bit ARM. T-bit in CPSR can
always switch from ARM to
Thumb and vice versa using
assembly instruction code16 and
code32, respectively.
49
When
working with 16-bit Thumb

set execute the instruction code16,
T bit set in CPSR. When
switching to 32-bit Arm set
execute the instruction code32,
reset T bit in CPSR.
50
ARM and Thumb code each execute

in their own processor state as
ARM PC increments by 4 and
Thumb by 2

51
Popular References at Web

http://www.cs.umd.edu/class/fall2001/cmsc41
1/proj01/arm/home.html
http://www.e-lab.de/ARM7/ARMinstructionset.pdf.
http://www.cvsi.fau.edu/shankar/Presenta
tions/Lecture7_Ch2_ARM.pdf.
52
http://www.cs.umd.edu/class/fall2001/
cmsc411/proj01/arm/thumb.html
http://www.cs.man.ac.uk/Study_subwe
b/Ugrad/coursenotes/cs1031/Lec20Thumb.pdf.

53
Summary

54
We learnt
Programmability
as little
endian and big endian
ARM 7 - Princeton
architecture, ARM 9 Harvard architecture
8-bit
byte, 16-bit half-word and

32-bit data types
55
We learnt
Conditional data processing, data
transfer and control flow Execution
and addressing modes facilitate by
the few instructions only
Options for shift or rotate an

operand in many instructions

56
We learnt
LDM/STM
with many more

addressing modes(like
immediate)
MAC Support
57
We learnt Thumb16 bit
subset
Better code density than 32-bit
architecture instruction set and
switching in-between ARM 32-bit
set and Thumb 16-bit set supported

58
End of Lesson 3 on ARM 32-bit

and Thumb16-bit Instruction Sets

59
THANK YOU

60

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ARM

"Microcontrollers....", Raj Kamal,

"Microcontrollers....", Raj Kamal,

code size small than other

"Microcontrollers....", Raj Kamal,

Basic Programming Features Processor

can operate on the words

Data Types support

Little Endian Mode

Address0 Byte0 (LSB)

Address0- even address; Address1- odd address

Three DataType options

Big Endian Mode

Address0 byte1 (MSB)

Address0- even address; Address1- odd address

Three DataType options

"Microcontrollers....", Raj Kamal,

SP (R13) Stack Pointer

"Microcontrollers....", Raj Kamal,

CPSR and SPSR

(Conditions and Processor

"Microcontrollers....", Raj Kamal,

Load multiple registers

"Microcontrollers....", Raj Kamal,

Load Instructions (in certain variants

Load multiple floating point

Store multiple registers

"Microcontrollers....", Raj Kamal,

Store Instructions (in certain variants

Store Multiple Floating

Data Transfer Instructions

Move value/register into a

"Microcontrollers....", Raj Kamal,

(32 x 32 64) multiply

Add with Carry, ADD:Add

MUL and DIV Instructions..

Unsigned Long (64 bit)

Divide floating Point-

"Microcontrollers....", Raj Kamal,

MAC unit Support

and MLAL implement DSP

AND, ORR, EOR

Program Flow Control

"Microcontrollers....", Raj Kamal,

Interrupt Control Instruction

Lets the OS including Device

The code required to create a

ARM32-bit Instruction Set Features

Data processing, data transfer and

ARM32-bit Instruction Option fields

or no-condition 4-bit field

32-bit Instruction Format

Refer Next Slide

S specifies CPSR flags change or no

X =1 then b11-b8 specifies

source operand can also be

"Microcontrollers....", Raj Kamal,

- Thumb16 bit subset

code density than 32-bit

"Microcontrollers....", Raj Kamal,

general-purpose Lower set of

16-bit Thumb Instruction Set

size small than 32-bit instruction