High Speed Op-amp Design: Compensation and

Topologies for Two and Three Stage Designs

R. Jacob Baker and Vishal Saxena

Department of Electrical and Computer Engineering
Boise State University
1910 University Dr., MEC 108
Boise, ID 83725
jbaker@boisestate.edu and vishalsaxena@ieee.org
Abstract :
As CMOS technology continues to evolve, the supply voltages are decreasing while at
the same time the transistor threshold voltages are remaining relatively constant. Making
matters worse, the inherent gain available from the nano-CMOS transistors is dropping.
Traditional techniques for achieving high gain by vertically stacking (i.e. cascoding)
transistors becomes less useful in sub-100nm processes. Horizontal cascading (multi-
stage) must be used in order to realize op-amps in low supply voltage processes.
This seminar discusses new design techniques for the realization of multi-stage op-amps.
Both single- and fully-differential op-amps are presented where low power, small
VDD, and high speed are important. The proposed, and experimentally verified, op-
amps exhibit significant improvements in speed over the traditional op-amp designs
while at the same time having smaller layout area.
Baker/Saxena
Outline

Introduction
Two-stage Op-amp Compensation
Multi-stage Op-amp Design
Multi-stage Fully-Differential Op-amps
Conclusion

Baker/Saxena
Op-amps and CMOS Scaling

The Operational Amplifier (op-amp) is a fundamental building

block in Mixed Signal design.
9 Employed profusely in data converters, filters, sensors, drivers etc.
Continued scaling in CMOS technology has been challenging
the established paradigms for op-amp design.
With downscaling in channel length (L)
9 Transition frequency increases (more speed).
9 Open-loop gain reduces (lower gains).
9 Supply voltage is scaled down (lower headroom) [1].

Baker/Saxena
 CMOS Scaling Trends

VDD is scaling down but VTHN is almost constant.

9 Design headroom is shrinking faster.
Transistor open-loop gain is dropping (~10s in nano-CMOS)
9 Results in lower op-amp open-loop gain. But we need gain!
Random offsets due to device mismatches.
[3], [4].

Baker/Saxena
Integration of Analog into Nano-CMOS?

Design low-VDD op-amps.

9 Replace vertical stacking (cascoding) by horizontal cascading of gain
stages (see the next slide).
Explore more effective op-amp compensation techniques.
Offset tolerant designs.
Also minimize power and layout area to keep up with the
digital trend.
Better power supply noise rejection (PSRR).

Baker/Saxena
 Cascoding vs Cascading in Op-amps
A Telescopic Two-stage Op-amp
A Cascade of low-VDD
Amplifier Blocks.
(Compensation not shown here)

VDD VDD VDD VDD VDD VDD

VDD

2 n-1

1
vm vp n vout

CL
Vbiasn Vbiasn Vbiasn

Stage 1 Stage 2 Stage (n-1) Stage n

VDDmin>4Vovn+Vovp+VTHP with VDDmin=2Vovn+Vovp+VTHP.

wide-swing biasing. [1]

Even if we employ wide-swing biasing for low-voltage designs, three- or

higher stage op-amps will be indispensable in realizing large open-loop DC
gain.
Baker/Saxena
 TWO-STAGE OP-AMP COMPENSATION

Baker/Saxena
 Direct (or Miller) Compensation

Compensation capacitor (Cc)

VDD VDD
between the output of the gain stages
VDD
M3 M4 M7
causes pole-splitting and achieves
1
220/2 dominant pole compensation.
750

vm vp iC fb An RHP zero exists at

M1 M2 vout
CC 10pF 2 CL 9 Due to feed-forward component of
iC ff
30pF the compensation current (iC).
Vbias3
M6TL
M6TR M8T
100/2 The second pole is located at
Vbias4
M6BL
M6BR M8B
100/2 The unity-gain frequency is
Unlabeled NMOS are 10/2.
Unlabeled PMOS are 22/2. x10

All the op-amps presented have been designed in AMI C5N 0.5m CMOS process with scale=0.3 m and Lmin=2.
The op-amps drive a 30pF off-chip load offered by the test-setup.

Baker/Saxena
Drawbacks of Direct (Miller) Compensation

VDD VDD The RHP zero decreases phase

VDD margin
M7
M3 M4
1 9 Requires large CC for
220/2
compensation (10pF here for a
vm
M1 M2
vp CC
vout
30pF load!).
10pF 2 CL Slow-speed for a given load, CL.
30pF
Vbias3 Poor PSRR
M6TL 100/2
M6TR M8T
Vbias4 9 Supply noise feeds to the output
M6BL 100/2
M6BR M8B through CC.
Unlabeled NMOS are 10/2.
Large layout size.
Unlabeled PMOS are 22/2.
x10

Baker/Saxena
 Indirect Compensation

VDD VDD VDD

VDD
The RHP zero can be eliminated by
M3 M4 M9
blocking the feed-forward compensation
1 M7
220/2 current component by using
vm ic
9 A common gate stage,
M1 M2 Cc
MCG
A
2 vout
CL
9 A voltage buffer,
vp
Vbias3
30pF 9 Common gate embedded in the
M6TL
M6TR M10T M8T
100/2
cascode diff-amp, or
Vbias4
M6BL
M6BR M10B M8B
100/2
9 A current mirror buffer.
Unlabeled NMOS are 10/2.
Unlabeled PMOS are 22/2.
Now, the compensation current is fed-
x10
back from the output to node-1 indirectly
An indirect-compensated op-amp through a low-Z node-A.
using a common-gate stage.
Since node-1 is not loaded by CC, this
results in higher unity-gain frequency
(fun).

Baker/Saxena
 Indirect Compensation in a Cascoded Op-amp
VDD VDD
M4T
M3T
A
ic VDD
M4B
Vbias2
M3B M7
110/2
1

vm vp CC CC
M1 M2 vout vout
2 CL CL
1.5pF vm vp
30pF

Vbias3
M6TL 50/2
M6TR M8T
Vbias4
M6BL 50/2
M6BR M8B

Unlabeled NMOS are 10/2.

Unlabeled PMOS are 44/2.

Indirect-compensation using Indirect-compensation using

cascoded current mirror load. cascoded diff-pair.

Employing the common gate device embedded in the cascode structure

for indirect compensation avoids a separate buffer stage.
9 Lower power consumption.
9 Also voltage buffer reduces the swing which is avoided here.
Baker/Saxena
Analytical Modeling of Indirect Compensation

The compensation
current (iC) is indirectly
fed-back to node-1.
Block Diagram

vout
ic
1 sCc + Rc

RC is the resistance
attached to node-A.

Small signal analytical model

Baker/Saxena
Derivation of the Small-Signal Model

Resistance roc is
assumed to be large.

The small-signal model

for a common gate
indirect compensated op-
amp topology is
approximated to the
simplified model seen in
the last slide.

gmc>>roc-1, RA-1,
CC>>CA

Baker/Saxena
 Analytical Results for Indirect Compensation
j

un

p3 p2 z1 p1

Pole-zero plot
LHP zero

Pole p2 is much farther away from fun.

9 Can use smaller gm2=>less power!
LHP zero improves phase margin.
Much faster op-amp with lower
power and smaller CC.
Better slew rate as CC is smaller.

Baker/Saxena
Indirect Compensation Using Split-Length Devices

As VDD scales down, cascoding is becoming tough. Then how to realize

indirect compensation as we have no low-Z node available?
Solution: Employ split-length devices to create a low-Z node.
9 Creates a pseudo-cascode stack but its really a single device.
In the NMOS case, the lower device is always in triode hence node-A is a
low-Z node. Similarly for the PMOS, node-A is low-Z.

Split-length 44/4(=22/2)
NMOS PMOS PMOS layout

Baker/Saxena
Split-Length Current Mirror Load (SLCL) Op-amp
VDD VDD
VDD
M3T M4T ic
A 220/2
M3B M4B M7T

220/2
1
M7B
vm vp CC
M1 M2 vout
2pF 2 CL
30pF
Vbias3
M6TL 50/2
M6TR M8T Frequency Response
M6BL
Vbias4
50/2
M6BR M8B

Unlabeled NMOS are 10/2.

Unlabeled PMOS are 22/2. ts

The current mirror load devices are

split-length to create low-Z node-A.
Here, fun=20MHz, PM=75 and
ts=60ns. Small step-input settling in follower
configuration

Baker/Saxena
 SLCL Op-amp Analysis
1 1 1
gmp gmp gmp
g m1
A v A
gm1v s + gmp s
-
2 Cc Cc

1 vout 1 vout
id2 id1 2 id1 2
vs vs vs

2 2
CL CL
2

v=0
(a) (b)

rop A
Cc 2
1

+ +
gm1v s
+ 1 1
v1 vsgA vout
2 gmp gmp
R1 C1 gmpvsgA - CA gm2v1 R2 C2
gm 1
- v -
gmp s

1 2 Here fz1=3.77fun
+ +
Cc
9 LHP zero appears at a higher
v1 vout
frequency than fun.
g m1v s 1
R1 C1 ic gm2v1 R2 gmp C2

- -
vout
ic 1 1
+
sCc gmp

Baker/Saxena
 Split-Length Diff-Pair (SLDP) Op-amp
VDD VDD
VDD
M3 M4
M7
1 110/2
M1T vp
vm M2T
20/2 20/2 ic vout
A
2pF 2 CL
20/2 20/2 CC 30pF
M1B M2B

Vbias3
M6TL
M6TR M8T
50/2 Frequency Response
M6BL
Vbias4
50/2
M6BR M8B

Unlabeled NMOS are 10/2.

Unlabeled PMOS are 22/2.

The diff-pair devices are split-length to

create low-Z node-A.
Here, fun=35MHz, PM=62, ts=75ns.
Small step-input settling in follower
Better PSRR due to isolation of node-A configuration
from the supply rails.
Baker/Saxena
 SLDP Op-amp Analysis

vout vout
vs vs
vs
2 2 2

1 1
gmn v s 1
gmn gmn id 2 = gmn
4

Cc

A ron 1
2

+ +
1
gmn
vA
1
gmn
+
vgs1 vout
Here fz1=0.94fun,
- gmnvgs1 R1 C1 gm2v1 R2 C2
CA
9 LHP zero appears slightly before
gmn v s
4
- vs -
2
fun and flattens the magnitude
1 2 response.
+ +
gmn v s
Cc
9 This may degrade the phase
v1
2
R1 C1 ic gm2v1 R2
1
gmn
vout
C2 margin.
-
vout
-
Not as good as SLCL, but is of
ic 1
+
1
sCc gmn great utility in multi-stage op-amp
design due to higher PSRR.
Baker/Saxena
Test Chip 1: Two-stage Op-amps

Miller 3-Stage Indirect

SLDP
SLCL Indirect
Indirect

Miller with Rz

AMI C5N 0.5m CMOS, 1.5mmX1.5mm die size.

Baker/Saxena
Test Results and Performance Comparison
Performance comparison of the op-amps for CL=30pF.

Miller with Rz (ts=250ns)

SLCL Indirect (ts=60ns) 10X gain bandwidth (fun).

4X faster settling time.
55% smaller layout area.
40% less power consumption.

SLDP Indirect (ts=75ns)

Baker/Saxena
 MULTI-STAGE OP-AMP DESIGN

Baker/Saxena
Three-Stage Op-amps

Higher gain can be achieved by

cascading three gain stages.
9 ~100dB in 0.5m CMOS
Results in at least a third order j
system
9 3 poles and two zeros.
9 RHP zero(s) degrade the phase
margin.

Hard to compensate and stabilize.
Large power consumption compared un
to the two-stage op-amps.
Pole-zero plot

Baker/Saxena
Biasing of Multi-Stage Op-amps

Diff-amps should be
employed in inner gain stages
to properly bias second and
third gain stages
9 Current in third stage is
precisely set.
9 Robust against large offsets.
Robust Biasing 9 Boosts the CMRR of the op-
amp (needed).
Common source second stage
should be avoided.
9 Will work in feedback
configuration but will have
offsets in nano-CMOS
processes.

Fallible Biasing
Baker/Saxena
Conventional Three-Stage Topologies
Nested Miller Compensation (NMC) [6]

Requires p3=2p2=4un for stability

(Butterworth response)
9 Huge power consumption
RHP zero appears before the LHP
zero and degrades the phase
margin.
Second stage is non-inverting
9 Implemented using a current
mirror.
9 Excess forward path delay (not
modeled or discussed in the
literature).

Baker/Saxena
Conventional Three-Stage Topologies contd.
Nested Gm-C Compensation (NGCC) [7]

Employs feed-forward gms to

eliminate zeros.
9 gmf1=gm1 and gmf2=gm2
Class AB output stage.
Hard to implement gmf1 which
tracks gm1 for large signal swings.
9 Also wasteful of power.
gmf2 is a power device and will not
always be equal to gm2.
9 Compensation breaks down.
Still consumes large power.

Baker/Saxena
 Conventional Three-Stage Topologies contd.
Transconductance with Capacitive
Feedback Compensation (TCFC) [14]
Four poles and double LHP zeros
9 One LHP zero z1 cancels the pole p3.
9 Other LHP zero z2 enhances phase
margin.
Set p2=2un for PM=60.
Relatively low power.
VDD VDD VDD VDD VDD VDD Still design criterions are complex.
VB1
gm2/2
VB7
gmf
Complicated bias circuit.
1

vm vp
CC1 9 More power.
CC2
gm1 VB2
VB5 VB6
gmt
3 vout Excess forward path delay.
2
VB3 VB4
1:2 gm3

Baker/Saxena
 Three-Stage Topologies: Latest in the literature
Reverse Nested Miller with Voltage Buffer
and Resistance (RNMC-VBR) [8]
Employs reverse nesting of
compensation capacitors
9 Since output is only loaded by only
CC2, results in potentially higher fun.
9 Third stage is always non-inverting.
Uses pole-zero cancellation to realize
VDD VDD VDD VDD VDD VDD higher phase margins.
RC1 Cc1
Excess forward path delay.
vm
gm1
vp
Cc2
2
3 vout
Biasing not robust against process
20uA
gmVB gm3
CL
variations. How do you control the
current in the output buffer?
1
gm2 gmf

Baker/Saxena
Three-Stage Topologies: Latest in the literature contd.
Active Feedback Frequency
Compensation (AFFC) [9]
High-Gain Block (HGB)
Reversed nested with elimination of
Cm RHP zero.
Input Block

vs vout
9 High gain block (HGB) realizes gain
+A2 -A3
by cascading stages.
-A1
1 2 3

9 High speed block (HSB) implements

-gmf
Ca
compensation at high frequencies.
+gma
Complex design criterions.
High-Speed Block (HSB)
Excess forward path delay. Again,
uses a non-inverting gain stage.
Employs a complicated bias circuit.
9 More power consumption.

Baker/Saxena
Three-Stage Topologies: Latest in the literature contd.

Various topologies have been recently reported by combining the earlier

techniques.
9 RNMC feed-forward with nulling resistor (RNMCFNR) [17].
9 Reverse active feedback frequency compensation (RAFFC) [17].
Further improvements are required in
9 Eliminating excess forward path delay arising due to the compulsory non-
inverting stages.
9 Robust biasing against random offsets in nano-CMOS.
9 Further reduction in power and circuit complexity.
9 Better PSRR.

Baker/Saxena
 Indirect Compensation in Three-Stage Op-amps
Indirectly feedback the compensation
currents ic1 and ic2.
9 Reversed Nested
Thus named RNIC.
Employ diff-amp stages for robust
biasing and higher CMRR.
Use SLDP for higher PSRR. VDD VDD VDD VDD

Minimum forward path delay. VDD

2
No compulsion on the polarity of gain -ve
1
stages. +ve
ic1 fbl
vout
vm vp Cc1
fbr
9 Can realize any permutation of stage fbl
3 CL

polarities by just changing the sign of ic2 fbr

Cc2
the fed-back compensation current Vbiasn

using fbr and fbl nodes.

Low-voltage design.
Note Class A (well modify after
theory is discussed).
Baker/Saxena
Indirect Compensation in Three-Stage Op-amps contd.
VDD VDD VDD VDD
VDD

-ve 2

1
ic1 fbl
+ve vout
vm vp Cc1
fbl fbr
3 CL

ic2 fbr
Cc2
Vbiasn

Note the red arrows showing the node movements and the signs of the
compensation currents.
9 fbr and fbl are the low-Z nodes used for indirect compensation (have
resistances Rc1 and Rc2 attached to them).
The CCs are connected across two-nodes which move in opposite direction
for overall negative feedback the compensation loops.
Note feedback and forward delays!
Baker/Saxena
Analysis of the Indirect Compensated 3-Stage Op-amp
Plug in the indirect compensation model developed for the two-stage op-
amps.
v2
i c1
1 sCc1 + Rc 1

vout
ic 2
1 sCc 2 + Rc 2

Two LHP zeros

Four non-dominant poles.
Baker/Saxena
Pole-zero Cancellation
Poles p4,5 are parasitic conjugated poles located far away in frequency.
9 Appear due to the loading of the nodes fbr and fbl.
The small signal transfer function can be written as

The quadratic expression in the denominator describing the poles p2 and p3

can be canceled by the numerator which describes the LHP zeros.
9 Results in LHP zeros z1 and z2 canceling the poles p2 and p3 resp.
The resulting expression looks like a single pole system for low
frequencies. Phase margin close to 90.

Baker/Saxena
Pole-zero Cancellation contd.
j

Place pole-zero doublets (p2-z1 and p3-

z2) out of fun for clean transients.
9 i.e. fp2, fp3 > fun.

Best possible pole-zero arrangement
for low power design. un

Results into design equations

independent of parasitics (C3CL
here).
Rc1 and Rc2 are realized by adding poly Design Equations
Rs in series with CC1 and CC2.
9 Also Rc1, Rc2Rc0, the impedance
attached to the low-Z nodes fbr/fbl.
Robust against even 50% process
variations in Rs and Cs as long as the
pole-zero doublets stay out of fun.

Baker/Saxena
Pole-zero cancelled Class-A Op-amp

A Here, the poly resistors are estimated as

Low power, simple, robust and manufacturable topology*.
The presented three-stage op-amps have been designed with transient and SR performances to
be comparable to their two-stage counterparts.

Baker/Saxena
 Pole-zero cancelled Class-AB Op-amp 1

A dual-gain path, low-power Class-AB op-amp topology (RNIC-1).

The design equation for Rc1 is modified as

Baker/Saxena
 Pole-zero cancelled Class-AB Op-amp 2
VDD VDD VDD VDD VDD

M8 M9
M4 M5 Vbiasp
VDD

M10
1
M1T 220/2
M2T Vpcas
20/2 20/2 66/2 66/2 MFCP R2c Cc2 vout
vm vp fbr
fbl fbr M5 M6 Vncas 11/2
4.08K 2p 3 CL
20/2 20/2 R1c Cc1 MFCN
fbl 10/2
M1B M2B 100/2 30pF
7.65K 1p 2 M11

Vbiasn Vbiasn

M3L M3R M7L M7R

Unlabeled NMOS are 10/2.

Unlabeled PMOS are 22/2.

A single-gain path, Class-AB op-amp topology for good THD

performance.
9 Floating current source for biasing the output buffer.
9 Here, Vncas= 2VGS and Vpcas=VDD 2VSG.
9 Note the lack of gratuitous forward delay.

Baker/Saxena
 Simulation of Three-stage Op-amps

Bode Diagram
100

50
Magnitude (dB)

-50

-100

-150
0
-45
Phase (deg)

-90
-135
-180
-225
2 4 6 8 10
10 10 10 10 10
Frequency (Hz)

Analytical model of the Class-AB (RNIC-1) topology is simulated in

MATLAB.
The pole-zero plot illustrates the double pole-zero cancelation (collocation).
9 p4 and p5 are parasitic poles located at frequencies close to that of the fT limited
(or mirror) poles.
Here, fun30MHz and PM=90 for CL=30pF.
Baker/Saxena
 Simulation of Three-stage Op-amps contd.

SPICE simulation of the same Class AB op-amp.

CL=30pF: fun=30MHz, PM88, ts=70ns, 0.84mW, SR=20V/s.
As fast as a two-stage op-amp with only 20% more power, at 50% VDD and with
the same layout area (simpler bias circuit).
Operates at VDD as low as 1.25V in a 5V process (25% of VDD).
SPICE simulation match with the MATLAB simulation
9 Our theory for three-stage indirect compensation is validated.

Baker/Saxena
Chip 2: Low-VDD 3-Stage Op-amps

Best
Performance

AMI C5N 0.5m CMOS, 1.5mmX1.5mm die size.

Baker/Saxena
Performance Comparison

Figures of Merit
9 FoMS=funCL/Power
9 FoML=SR.CL/Power
9 IFoMS=funCL/IDD
9 IFoML=SR.CL/IDD
RNIC op-amp designed
for 500pF load for a fair
comparison.
FoMs>2X than state-of-
the-art at VDD=3V.
Comparable performance
even at lower VDD=2V.
Practical, stable and
production worthy.

Baker/Saxena
Performance Comparison contd.
60000

50000 Higher performance figures

40000 FOM_S
FOM_L
than state-of-the-art.
30000

10X faster settling.

IFOM_S
20000 IFOM_L

Better phase margins.

10000

0
R NR
Layout area same or smaller.
R

SM NR

N -3 s w P
FC
C

VB F

M C
F
M C

FC

R -2A hi s rk )

A sw )
)
k)
AC C
FN

-3 hi rk
hi ork
IC Thi C L
M ZC
C
C
M

R FF

IC RA F
F

or
F
FC

TC

o
IC (T wo
B
G

F
N

AF

C
C

w
R DP

A
R - 2 ( FF
N
M

s
C

N
N

(T
IC (T
N

N
R

Baker/Saxena
Flowchart for RNIC Op-amp Design
Start with the initial
specifications on fun, CL,
Av, and SR.

Split DC gain AOLDC

across A1, A2 and A3.

Select the overdrive (% of

VDD) which will set VGS, fT
and transistor gain gm*ro.

Identify gm1. Can

initially set gm2 equal to
gm1 or a to lower value.

Select Cc2 = gm1/fun

Select Cc1 and gm3 such that

the p2-z1 and p3-z2 doublet
locations are outside fun.
Move the corresponding pi-zj
doublet to a lower frequency
by changing Cci and Rci. May
have to sacrifice fun.
Calculate R1c and R2c.

Yes

Are the parasitic

poles p4,5 degrading
Yes Increase gm2.
Is either of R1c PM by closing on
and R2c negative? fun?

No No

Simulate the design for

frequency response No More Increase gm1 or
Yes
and transient settling. Speed? decrease Cc2.

No
Does the design Decrease gm3 or gm2.
meet the Lower In the worst case
specifications? power? Yes
scenario decrease
gm1.

No
Yes

Smaller
End Reduce Cc1, Cc2 or
layout Yes
gm3.
area?

No

Increase bias current in the

Nothing works!
No Better SR? Yes first stage (i.e. ISS1) or use
Revisit biasing.
smaller CCs

Baker/Saxena
N-Stage Indirect Compensation Theory
The three-stage indirect compensation theory has been extended to N-
stages and the closed form small signal transfer function is obtained.
Cc
n1

Cc
n2

Cc
2

Cc
ic 1
n1
ic
n2
ic
2 ic
1

Baker/Saxena
MULTI-STAGE FULLY-DIFFERENTIAL
OP-AMPS

Baker/Saxena
Fully Differential Op-amps

Analog signal processing uses only

fully differential (FD) circuits.
9 Cancels switch non-linearities and even
order harmonics.
9 Double the dynamic range.
Needs additional circuitry to maintain
the output common-mode level.
9 Common-mode feedback circuit
(CMFB) is employed.
vop-vom=-A(vinp-vinm)

Baker/Saxena
Three-Stage FD Op-amp Design: Problems
Block Diagram Circuit Implementation
VDD VDD VDD VDD VDD VDD VDD

vom1 vop1
vom2 Cc1 R1c R1c Cc1 vop2
fbr fbl

20/2 20/2 20/2

vm VCM vp vop1 Vbiasp vom1
fbl fbr
20/2 20/2 20/2

Vbiasn VCMFB1 Vbiasn

First Stage Second Stage

VDD VDD

vom2 vop2 vop

110/2 VDD VDD 110/2

100f
vom Cc2 R2c R2c Cc2

30K
vop
fbl fbr

VCMFB1
50/2 50/2 VCM

100f
30K
VCM
100/2 100/2
vom

VCMFB3 Unlabeled NMOS are 10/2.

100/2 100/2 Unlabeled PMOS are 22/2.
Output Buffer
(Third Stage)

The CMFB loop disturbs the DC biasing of the intermediate gain stages.
9 Degrades the gain, performance and may cause instability.

Baker/Saxena
Three-Stage FD Op-amp Design: Solutions
Cc2
1. Cc1
Employ CMFB
+
1p 2p 3p
1. Individually across all the stages.
vp - vop
-A1 +A2 -A3

2. Only across the last two stages as the vbiasp vbiasn vCM

biasing of the output buffer need not be

precise. vm -A1 -
1m
+A2
2m
-A3
3m
vom
+

3. Only in the third stage (output buffer).

Cc1

Cc2

Cc2 Cc2
2. 3.
Cc1 Cc1

+ +
vp 1p 2p 3p vop vp -
1p 2p 3p vop
-
-A1 +A2 -A3 -A1 +A2 -A3

vCMFB vCM vCMFB vCM

-A1 +A2 -A3 -A1 +A2 -A3

vm -
1m 2m 3m vom vm -
1m 2m 3m vom
+ +

Cc1 Cc1

Cc2 Cc2
Baker/Saxena
Three-Stage FD Op-amp Design
Circuit Implementation
Block Diagram Second Gain Stage

VDD VDD VDD VDD VDD VDD VDD

vom1 vop1
vom2 Cc1 R1c R1c Cc1 vop2
fbl fbr
20/2 20/2 20/2
vm VCM vp
fbl fbr
20/2 20/2 20/2

Vbiasn Vbiasn Vbiasn

First Gain Stage

VDD VDD
Unlabeled NMOS are 10/2.
Unlabeled PMOS are 22/2.
vom2 vop2
110/2 VDD VDD 110/2
Cc2 R2c R2c Cc2 vop
vom vop
fbr fbl

100f
30K
50/2 50/2
VCMFB3
VCM VCM
100/2 100/2

100f
30K
VCMFB3 vom
100/2 100/2

Output Buffer
(Third Stage)

Use CMFB only in the output (third) stage. Manufacturable design.

9 Leaves the biasing of second and third stage alone without disturbing them.
Employ diff-amp pairs in the second stage for robust biasing.
Baker/Saxena
Three-Stage FD Op-amp: Enlarged

100f
30K

100f
30K

Baker/Saxena
Chip 3: Low-VDD FD Op-amps

Best
Performance

AMI C5N 0.5m CMOS, 1.5mmX1.5mm die size.

Baker/Saxena
Simulation and Performance Comparison
DC behavior Transient response

82dB gain ts=275ns

>2.5X figure of merit (FoM).

Baker/Saxena
Flowchart for Three-Stage FD Op-amp Design
Start with the initial
specifications on fun, CL,
Av, and SR.

Design a singly-ended pole-zero cancelled

three-stage op-amp for the given
specifications.

Convert the singly-ended op-amp into a fully

differential one by mirroring it. Use a pair of
diff-pairs for the second stage for robust
biasing.

Add a CMFB circuit in the output buffer.

No
Update the value of gm3 corresponding to the
output buffer and recalculate R1C and R2C.

Simulate the design.

Does the design meet

specifications?

Yes

End

Baker/Saxena
Conclusions
Indirect compensation leads to significantly faster, lower power op-amps
with smaller layout area.
Indirect compensation using split-length devices facilitates low-VDD op-
amp design.
Novel pole-zero canceled three-stage RNIC op-amps exhibit substantial
improvement over the state-of-the-art.
A theory for multi-stage op-amps is presented.
New methodologies for designing multi-stage FD op-amps proposed which
improve the state-of-the-art.
All proposed op-amps are low voltage
9 Open new avenues for low-VDD mixed signal system design.

Baker/Saxena
Future Scope

Mathematical optimization of PZC op-amps.

Design of low-VDD systems in nano-CMOS process
9 Pipelined and Delta-Sigma data converters,
9 Analog filters,
9 Audio drivers, etc.
Further investigation into indirect-compensated op-amps for n4 stages.

Baker/Saxena
References

[1] Baker, R.J., CMOS: Circuit Design, Layout, and Simulation, 2nd Ed., Wiley Interscience, 2005.
[2] Saxena, V., Indirect Compensation Techniques for Multi-Stage Operational Amplifiers, M.S. Thesis, ECE Dept., Boise
State University, Oct 2007.
[3] The International Technology Roadmap for Semiconductors (ITRS), 2006 [Online]. Available:
http://www.itrs.net/Links/2006Update/2006UpdateFinal.htm
[4] Zhao, W., Cao, Yu, "New Generation of Predictive Technology Model for sub-45nm Design Exploration" [Online].
Available: http://www.eas.asu.edu/~ptm/
[5] Slide courtesy: bwrc.eecs.berkeley.edu/People/Faculty/jan/presentations/ASPDACJanuary05.pdf
[6] Leung, K.N., Mok, P.K.T., "Analysis of Multistage Amplifier-Frequency Compensation," IEEE Transactions on Circuits
and Systems I, Fundamental Theory and Applications, vol. 48, no. 9, Sep 2001.
[7] You, F., Embabi, S.H.K., Sanchez-Sinencio, E., "Multistage Amplifier Topologies with Nested Gm-C Compensation,"
IEEE Journal of Solid State Circuits, vol.32, no.12, Dec 1997.
[8] Grasso, A.D., Marano, D., Palumbo, G., Pennisi, S., "Improved Reversed Nested Miller Frequency Compensation
Technique with Voltage Buffer and Resistor," IEEE Transactions on Circuits and Systems-II, Express Briefs, vol.54, no.5,
May 2007.
[9] Lee, H., Mok, P.K.T., "Advances in Active-Feedback Frequency Compensation With Power Optimization and Transient
Improvement," IEEE Transactions on Circuits and Systems I, Fundamental Theory and Applications, vol.51, no.9, Sep
2004.
[10] Eschauzier, R.G.H., Huijsing, J.H., "A 100-MHz 100-dB operational amplifier with multipath Nested Miller
compensation," IEEE Journal of Solid State Circuits, vol. 27, no. 12, pp. 1709-1716, Dec. 1992.
[11] Leung, K. N., Mok, P. K. T., "Nested Miller compensation in low-power CMOS design," IEEE Transaction on Circuits and
Systems II, Analog and Digital Signal Processing, vol. 48, no. 4, pp. 388-394, Apr. 2001.
[12] Leung, K. N., Mok, P. K. T., Ki, W. H., Sin, J. K. O., "Three-stage large capacitive load amplifier with damping factor
control frequency compensation," IEEE Journal of Solid State Circuits, vol. 35, no. 2, pp. 221-230, Feb. 2000.

Baker/Saxena
References contd.

[13] Peng, X., Sansen, W., "AC boosting compensation scheme for low-power multistage amplifiers," IEEE Journal of Solid
State Circuits, vol. 39, no. 11, pp. 2074-2077, Nov. 2004.
[14] Peng, X., Sansen, W., "Transconductances with capacitances feedback compensation for multistage amplifiers," IEEE
Journal of Solid State Circuits, vol. 40, no. 7, pp. 1515-1520, July 2005.
[15] Ho, K.-P.,Chan, C.-F., Choy, C.-S., Pun, K.-P., "Reverse nested Miller Compensation with voltage buffer and nulling
resistor," IEEE Journal of Solid State Circuits, vol. 38, no. 7, pp. 1735-1738, Oct 2003.
[16] Fan, X., Mishra, C., Sanchez-Sinencio, "Single Miller capacitor frequency compensation technique for low-power
multistage amplifiers," IEEE Journal of Solid State Circuits, vol. 40, no. 3, pp. 584-592, March 2005.
[17] Grasso, A.D., Palumbo, G., Pennisi, S., "Advances in Reversed Nested Miller Compensation," IEEE Transactions on
Circuits and Systems-I, Regular Papers, vol.54, no.7, July 2007.
[18] Shen, Meng-Hung et al., "A 1.2V Fully Differential Amplifier with Buffered Reverse Nested Miller and Feedforward
Compensation," IEEE Asian Solid-State Circuits Conference, 2006, p 171-174.

Baker/Saxena