Professional Documents
Culture Documents
Erik Brunvand
School of Computing
University of Utah
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Contents
1 Introduction 9
1.1 Cad Tool Flows . . . . . . . . . . . . . . . . . . . . . . . . 10
2 Cadence ICFB 15
2.1 Cadence Design Framework . . . . . . . . . . . . . . . . . 15
2.2 Starting Cadence . . . . . . . . . . . . . . . . . . . . . . . 17
4 Verilog Simulation 45
4.1 Verilog Simulation of Composer Schematics . . . . . . . . . 48
4.1.1 Verilog-XL: Simulating a Schematic . . . . . . . . 49
4.1.2 NC Verilog: Simulating a Schematic . . . . . . . . 67
4.2 Behavioral Verilog Code in Composer . . . . . . . . . . . 75
4.2.1 Generating a Behavioral View . . . . . . . . . . . . 75
4.2.2 Simulating a Behavioral View . . . . . . . . . . . . 78
4.3 Stand-Alone Verilog Simulation . . . . . . . . . . . . . . . 79
4.3.1 Verilog-XL . . . . . . . . . . . . . . . . . . . . . . 80
CONTENTS Draft August 24, 2006
4.3.2 NC Verilog . . . . . . . . . . . . . . . . . . . . . 86
4.3.3 vcs . . . . . . . . . . . . . . . . . . . . . . . . . . 91
4.4 Timing in Verilog Simulations . . . . . . . . . . . . . . . . 98
4.4.1 Behavioral versus Transistor Switch Simulation . . . 98
4.4.2 Behavioral Gate Timing . . . . . . . . . . . . . . . 101
4.4.3 Standard Delay Format (SDF) Timing . . . . . . . . 104
4.4.4 Transistor Timing . . . . . . . . . . . . . . . . . . . 106
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CONTENTS Draft August 24, 2006
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Bibliography 224
Index 226
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CONTENTS Draft August 24, 2006