KASHYAP RAHUL ANILKUMAR

74 / A, Dhanpaleshwar Society,
Near Vinzol Railway Colony,
S. L. M Road, Vatva, Ahmedabad-382445
Contact: +91 9429322575
Email: kashyap.rahul260@gmail.com

M.E. in VLSI and Embedded System Design and B. Tech. in E.C.E

Seeking a challenging and rewarding opportunity with an organization of repute which recognizes and
utilizes my true potential while nurturing my analytical and technical skills

PROFESSIONAL EXPERIENCE
Organization : INDIAN INSTITUTE OF TECHNOLOGY, JODHPUR
Designation : LAB ENGINEER
Profile : Research
Experience : 04 Months

Organization : SVNIT, SURAT

Designation : TEACHING ASSISTANT, Department of ELECTRONICS ENGINEERING.
Experience : 1 Year, 6 Months.

PROFILE
Accented with the latest trends and techniques of the field; Pursued M.E in VLSI and Embedded
System Design from Gujarat Technological University, Ahmedabad, Gujarat and CDAC, Pune
Pursued B.Tech in Electronics and Communication Engineering from Rajasthan Technical University
KOTA, Rajasthan.
Certified Automation Engineer : Skills include PLC (AB, Siemens, Mitsubishi and GE Fanuc), SCADA
Systems, HMI and DCS Systems (ABB).

Tools and Softwares Proficiency

Design Compiler (DC) Synthesis tool.
IC Compiler Physical Design tool.
Custom Designer SE (SYNOPSYS) tool.
HSPICE Circuit Analysis tool.
Mentor Graphics Design Architect and ELDO Spice.
ORCAD Tool for PCB Fabrication.
Proteus Design tool for Embedded System.
Xilinx 12.3 Simulation Environment.
KEIL Vision 4(ARM 7 and 8051 microcontroller).

Areas of Interest
VLSI Design, Digital Electronics, Control Systems, Basic Electronics and Embedded System Design.
EDUCATIONAL CREDENTIALS

Qualification Specialization Institute/University Year of Passing %/CPI

VLSI and Embedded System Gujarat Technological

M.E Design University PG School and 2014 8.79 CPI
CDAC, PUNE

Electronics and Communication Rajasthan Technical

B.Tech 2012 71.21%
Engineering University, KOTA

XII Science I.S.C.E, New Delhi 2007 83.6%

X Science I.S.C.E, New Delhi 2005 75.83%

Projects Undertaken
1. M.E. Dissertation
Title: Implementation of Ternary Sequential Elements using CNTFET.
Platform: VLSI with Analog and Mixed Signal Design
Organization: CDAC, PUNE
Duration: 10-12 Months
Abstract: The Aim of this work is to present the Advantages of Ternary Logic over Binary Logic in
terms of Computations and Circuit Designs based on CNTFET, replacing MOSFET reduces the total
power consumption and occupies less area on VLSI Chips.

Other M.E Projects

CAN (Controller Area Network) Protocol Controller Design using Verilog.
ALU (Arithmetic and logical Unit) Physical Design (Frontend and Backend).
Minor Projects on ARM7 Microcontroller.

2. B. Tech Major Project

Title: SMS Based Wireless Electronic Notice Board using GSM
Platform: Embedded System
Duration: 6 months
Abstract: The main objective of the project is to display messages on LCD module (Notice Board).
Messages are sent through a mobile phone and one another SIM is inserted into a GSM module at
the receiving end. Microcontroller 8051 is used to control the messages and LCD module.

Papers Published
(1) Rahul Kashyap, Implementation of Ternary Logic Gates using CNTFET in International Journal
for Scientific Research and Development (IJSRD), Vol. 2 Issue 3, 2014, ISSN: 2321-0613, Page 352-
355.
(2) Rahul Kashyap, Radha Tapiawala, Design of Universal Logic Gates based on CNTFET for Binary
and Ternary Logic in IJERT, Vol. 3 Issue 6, June 2014, ISSN: 2278-0181, Page 604-609.

PG Diploma in Automation at PROLIFIC SYSTEMS, THANE

Proficiency in SCADA Systems.
PLC (Allen Bradley, Siemens, Mitsubishi and GE Fanuc).
Human Machine Interface (HMI).
Digital Control Systems (DCS) of ABB.
H/W design for PLC Systems.
Instrumentation Panel Designing.

Subjects undertaken during Professional Term

Analog VLSI Design (M.Tech-II)
Digital VLSI Design (M.Tech-I)
Digital Integrated Circuits (B.Tech-III)
Electronics Instrumentation (B.Tech-IV)

Seminars Guided
Sensor based Automation of Greenhouse
Android: Architecture and Development
PAN Sharpening Techniques in Image Processing

Technical Skills
Qualified GATE-2016 Examination recently with Electronics and Communication Engineering.
Qualified GATE-2012, 2013 and 2014 Examination with ECE.
VERILOG, HSPICE, Embedded C, Embedded Linux, C, C++, HTML, JAVA, Perl, Web Designing and
Internet Applications.

Achievement
Credential of being awarded for securing 100% in Mathematics in XII Examination, I.S.C.E Board.

Extra Curricular Accolades

Ethical Hacking Expert from Tech Defence Private Limited, Techfest IIT Bombay.
Served as an Event Manager of National Techfest SAKSHAMA NEW 10 and LAN Gaming.
Participated in Cultural & Technical events, involved as a team member of Colleges Annual Sports.
Seeked workshops on WEB DESIGNING, Communication Skills and Ethical Hacking.

Seminars Delivered
Delivered a Seminar on Surface Computing Technology.
Microsoft Surface Overview with In-Depth Analysis of its working and Components.
MRAM Technology.
Hobbies
PC Games, Reading, Photography, Computer Learning, Riding Bikes, Outing.

Personal Details
Date of Birth : 18th October, 1989
Gender : Male
Nationality : Indian
Marital Status : Unmarried
Languages Known : English, Hindi, and Gujarati.

Declaration:
I hereby declare that the above mentioned Information is Correct and I Bear the Responsibility for the
Correctness of the above mentioned Particulars.

Kashyap Rahul AnilKumar