ASSIGNMENT-II

Note: Hand written assignment on A4 size plain paper should be submitted to Mr.Pawan Dubey
(M.Tech. Student, Department of ECE) on 23rd of February 2017 (3:00 P.M. to 5:00 P.M.) at room no.222.
This assignment is part of your continuous evaluation.

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Q.1. List and briefly define the possible states that define an instruction execution.
(Refer William Stalling)
Q.2. What are the difference between a traditional bus structure and a high performance bus
architecture? Explain with block diagrams. (Refer William Stalling)

Q.3. Discuss an Instruction cycle with interrupts. (Refer William Stalling)

Q.4. A microprocessor has a memory write timing as shown in Figure 3.19 of William Stalling. Its
manufacturer specifies that the width of the Write signal can be determined by T-50,where T is the clock
period in nanoseconds.
a. What width should we expect for the Write signal if bus clocking rate is 5 MHz?
b. The data sheet for the microprocessor specifies that the data remain valid for 20 ns after the
falling edge of the Write signal. What is the total duration of valid data presentation to memory?
c. How many wait states should we insert if memory requires valid data presentation for at least
190 ns
.
Q.5. What are the functional groups of a bus structure?
(Refer William Stalling)

Q.6. Consider a 32-bit microprocessor whose bus cycle is the same duration as that of a 16 bit
microprocessor. Assume that, on average, 20% of the operands and instructions are 32 bits long,40% are
16 bits long, and 40% are only 8 bits long. Calculate the improvement achieved when fetching
instructions and operands with the 32-bit microprocessor.