Embedded and Intelligent Systems

RAJA VARA PRASAD Y

IIIT Chittor

September 3, 2016

1 / 115
Course Contents
I Introduction to Embedded Systems.
I Characteristics, Different Types of Embedded Systems,
Components of Embedded System,
I Hardware Architecture, Processor, Peripheral Devices,
Embedded Software Architecture, Need of Real Time
Operating Systems and Different Application Areas.
I Processor and Memory Selection: Different Types of Processor
Technologies, Processor Selection for an Embedded System,
Different Types of Memory Devices, Memory Selection for an
Embedded System.
I Interfacing
I Communication protocol concepts, Microprocessor interfacing:
I/O addressing, Port and Bus based, I/O, Memory Mapped
I/O, Standard I/O interrupts, Direct memory access, Serial
Communication Protocols I2C
I CAN, Parallel Communication Protocols PCI bus, Wireless
protocol Bluetooth etc.
I Different types of Interrupts, Interrupt Servicing Mechanism,
Device Servicing using ISR
2 / 115
Contents....

I Introduction to Real Time Operating Systems

I Basics of Operating Systems, Differences between General
Purpose and Real-Time Operating Systems, Features of Real
Time Operating Systems
I RTOS Kernel Structure,Issues in multitasking task
assignment, scheduling, InterProcess Communication and
Synchronization, Interrupt routines in RTOS Environment and
Real Time Task Scheduling.
I Introducing Commercial Real-Time Operating Systems
I Networked Embedded Systems
I Distributed Embedded Architectures
I Networks for Embedded Systems
I Internet-Enabled Systems
I Design Examples

3 / 115
Preferred Textbooks and References

I Wayne Wolf, Computers as Components - Principles of Embedded Computer

System Design, Morgan Kaufmann Publisher, 2006.
I Jonathan W. Valvano, Introduction to Embedded Systems, 2012.
I David E-Simon,An Embedded Software Primer, Pearson Education.
I Raj Kamal, Embedded Systems, Tata McGraw Hill, 2003.
I Vahid Frank, Embedded system Design: A Unified Hardware/ software
Introduction.
I Mazidi Muhammad Ali and Naimi sarmad, The avr Micro controller and
embedded systems.

4 / 115
Week wise Syllabus Coverage

Week Topic No of Hours

1 Introduction, Definitions, types and components 3
2 Architecture, Peripheral Devices, Need for RTOS and Application 3
Areas
3 Processor and Memory Selection, Processors and Controllers 3
4 Embedded Processors ARM Cortex M3 3
5 Interfacing: I/O, Direct memory access, Serial Communication 3
Protocols I2C
6 CAN, Parallel Communication Protocols PCI bus, Wireless pro- 3
tocol Bluetooth
7 Interrupt Service Routine and servicing them 3
8 Introduction to Real-time Operating System and scheduling 3
9 Multitasking and Real-time Scheduling Techniques Pre-emptive 3
and Non-pre-emptive Scheduling
10 Earliest-Deadline-First (EDF) and Rate-Monotonic Scheduling 3
etc.
11 RTOS Kernel Structure, Interrupt routines in RTOS Environment 3
and Real Time Task Scheduling.
12 Networked Embedded Systems and Distributed Embedded Archi- 3
tectures
13 Networks for Embedded Systems and Internet-Enabled Systems 3
14 Design Example with a Case study 3
5 / 115
Grading Policy

Grading Method: Relative

Component Max marks Weight Remarks

Assignments 50 12.5% Course and Lab Assignments
Mid sem-1&2 60 15% Closed book exam
Industrial Visit 30 7.5% Visit to any Automobile or Automation
report or Research industry. Individual report of
the trip.
End Exam 120 30% Part-A of exam is closed book and Part-
B is open book
Course Project 140 35% Group of Max 3 members to work on an
identified problem using Embedded kits.
Three reviews before final demonstration
and a report in the form of a paper
Total 400 100%

6 / 115
Harware Kits for Course Project

(a)

(b) (c)

Figure: a) CY8CKIT-050B b)Arduino c) Raspberry Pi 7 / 115

Industrial Visit report

(a)

(b)

Figure: a) Automobile industry b) Process and Control or Automation Industry 8 / 115

Introduction to Embedded Systems

I What is an Embedded System ?

I what do you mean by Real Time ?
I Real Time Embedded Systems ?
I What are typical embedded systems u have seen ?

9 / 115
Embedded Systems Examples

Figure: Embedded devices in day to day life

10 / 115
Definitions

I Embedded System: subsystems coexist to realize a funtion

I Real Time: Defined time limits to complete the task. Defined
time limits may be milliseconds/minutes/hours.
I Real Time Embedded Systems: Coexistence of Subsystems to
arrive at a functionality which work coherently without
exceeding predefined time limits.
I Real Time Operating Systems: Programs to execute RTOS
I Hardware and Software Co-design: Choice of
hardware/software at the trade of cost/time

11 / 115
Embedded Systems: Part of Evolving Research Areas

(a) (b)

(c) (d)

Figure: a) Smart grid b) Smart transportation c) Smart buildings d) Smart cities

12 / 115
Desktop Vs Embedded Computer

I Desktop computer is a more general purpose machine with

high computation capabilities
I Embedded Computer is designed to operate for a specific task
I Lot of subsystems are interconnected in a more standardized
way to accomplish a task
I Embedded systems are mostly System on Chip (SoC) with
minimal subsystem interface.
I Desktop machines do not continuosly interact with input and
output whereas embedded systems are more reactive to inputs
and deliver outpputs in real time.

13 / 115
Desktop Vs Embedded Computer ...

(a) (b)

Figure: a) Desktop Computer b) Embedded System

14 / 115
lets Talk about your Favourite Gadzet - Mobile Phone
Basic functionality of Mobile ?
I To Communicate (Voice)
I Display
I Input Keys

(a) (b)

Figure: a) Hardware circuitry of mobile b) Block diagram of basic components of mobile

15 / 115
Different Components of Embedded Systems

I Microprocessor
I Memory
I Input, Output and Other Interfaces
I Software

16 / 115
Design Metrics for Embedded System

I Non Recurring Engineering Cost

I Unit Cost
I Size
I Performance
I Power Consumption
I Flexibility
I Time to Prototype
I Time to market
I Maintainability
I Correctness
I Latency and Throughput

17 / 115
Different Types of Embedded Systems

I Similar to general purpose computing : Not much change the

external world.
Examples: Set-top boxes, Automated Teller Machines (ATM)
I Control Systems: Sensing, Feedback and automation:
Nuclear, Fuel injecction etc.
I Signal Processing : Radar, Sonar etc
I Communication and Networking: Cellular Phones, Internet
Appliances

18 / 115
Top Down Approach

19 / 115
Case Study: GPS based Road Navigation System

Requirements
I Name: GPS moving map
I Purpose: Consumer-grade moving map for driving use
I Inputs: Power button, two control buttons
I Outputs: Back-lit LCD display 400X600
I Functions: Uses 5-receiver GPS system; three user-selectable
resolutions; always displays current latitude and longitude
I Performance: Updates screen within 0.25 seconds upon
movement
I Manufacturing cost: 2100 Rs Power 100mW Physical size and
weight No more than 2X6 inch, 12 ounces

20 / 115
Case Study: GPS based Road Navigation System

Specifications
I Data received from the GPS satellite constellation.
I Map data.
I User interface.
I Operations that must be performed to satisfy customer
requests.
I Background actions required to keep the system running, such
as operating the GPS receiver.

21 / 115
Architecture: Block Diagram of GPS based Road
Navigation System

(a)

Figure: Block Diagram of GPS navigation module

22 / 115
Architecture of GPS Navigation - Hardware

(a)
23 / 115
Architecture of GPS Navigation - Software

(a)

Figure: Software Architectures of GPS navigation module

24 / 115
Components and System Integration stages of GPS
Navigation module

Components Design:
I Both Hardware and Software modules design
I Hardware: FPGA, standard Integrated Circuits, DSP, PCB
I Software: Topographical Database, Algorithms
I Hardware and Software Co-design
System Integration:
I Integration of all subsystems
I Debugging
I Correctness

25 / 115
General Purpose MicroProcessor and Microcontroller

I Its more a CPU

I RAM, ROM, I/O etc are interfaced
I Example: Intel X86, Motorolo 680X

Figure: General Purpose Micro-Processor

26 / 115
Microcontroller
I integrating number of components and a Microprocessor onto
a single chip
I less computational specific microprocessor, memory, serial and
parallel Input/ouput, Application specific

Figure: Microcontroller

27 / 115
Components of a Microcontroller

Figure: Microcontroller

28 / 115
 Microcontroller Vs Microprocessor for Embedded
applications

I Low Cost, small packaging

I low power consumption
I programmable, reprogrammable
I Input/output capabilities
I Easy integration with other application specific circuits
I Single purpose

29 / 115
Computer Architectures

Differentition interms of Instruction and Data access.

I Von Neumann Architecture
I Harvard Architecture
I Modified Harvard Architecture

30 / 115
Von Neumann architecture
Single Bus for Instructions and Data
I Bit widths should be same for Instruction and Data
I Data Transfers and Instructions fetches should be Scheduled
I Pipelining is complex
I Early Systems

Figure: Von Nuemann Architecture

31 / 115
Harvard Architecture
Seperate instruction and Data buses
I Different Widths can be different for Data and Instruction
I Simultaneous and faster operation
I Pipelining is Easier than Von Nuemann
I Most of the Modern Systems
I Examples: DSP processors, ARM, AVR, ATMEL, PIC etc.

Figure: Harvard Architecture

32 / 115
ARM Family

Figure: Different Variants of ARM

33 / 115
Memory

Figure: Different Variants of ARM

CPU can access memory using below Bus.

I Address Bus
I Data Bus
I Control Bus

34 / 115
Memory

I Processor Memory (Register Array)

I Internal on-chip Memory
I Primary Memory
I Cache Memory
I Secondary Memory

35 / 115
Memory

I mXn: m word memory with n bits each

I 4096X8 memory: Address lines ? and input/output signals ?
Total bits ?
I Memory Specifications: Write ability and storage performance
I Write Ability: High-RAM
Middle-FLASH, EEPROM
Lower Range-EPROM, OTP ROM
Low end-Mask Programmed ROM
I Storage performance: High-Never loses bits - Masked ROM
Middle-holds bits days, months, or years after - NVRAM
Lower range - holds bits as long as power supplied to
memory-SRAM
Low end - begins to lose bits almost immediately after written
- DRAM

36 / 115
Word

37 / 115
ROM
I Mask programmed ROM
I ONe Time Programmable ROM
I Erasable Programmabel ROM
I Electrically Erasable Programable ROM
I FLASH

38 / 115
RAM
I Static RAM - Flipflops
I Dynamic RAM - MOS transistor with capacitor
I PSRAM - Pseudo Static RAM: DRAM with built in memory
refresh controller
I Non Volatile RAM - Battery backed RAM
SRAM with a battery
SRAM with EEPROM can completely store RAM contents on
EEPROM or FLASH

39 / 115
Extending Memory - Number of words/width of words

40 / 115
Extending Memory - both for Number of words and width
of words

41 / 115
CY8CKIT59

42 / 115
General Purpose Input Output

I GPIO pins can be configured to be input or output

I GPIO pins can be enabled/disabled
I Input values are readable (typically high=1, low=0)
I Output values are writable/readable
I Input values can often be used as Interrupt Requests
Assignment: 2 bit Adder to be shown on the kit. display sum,
carry etc with LEDs using GPIO

43 / 115
CY8CKIT59 - GPIO

44 / 115
Analog to Digital Converter - ADC

I Direct/Flash ADC
I Successive Approximation ADC
I Dual Slope ADC
I Sigma Delta ADC
Reading Assignment: Dual Slope and Sigma Delta ADC

45 / 115
Flash ADC

46 / 115
Successive Approximation ADC

47 / 115
Successive Approximation ADC

48 / 115
Multi Channel ADC

49 / 115
Introduction to ARM Cortex M3

50 / 115
Different Profiles of ARM v7

I The A profile is designed for high-performance open application platforms.

to handle complex applications targeting OS like Symbian, Linux, and Windows
Embedded.
These processors requiring the highest processing power, virtual memory system
support with memory management units (MMUs), and, optionally, enhanced
Java support and a secure program execution environment.
Example products include high-end mobile phones and electronic wallets for
financial transactions.
I The R profile is designed for high-end embedded systems in which real-time
performance is needed.
Real-time, high-performance processors targeted primarily at the higher end of
the real-time market.
Examples: high-end breaking systems and hard drive controllers, in which high
processing power and high reliability are essential and for which low latency is
important.
I The M profile is designed for deeply embedded microcontroller-type systems.
Processors targeting low-cost applications in which processing efficiency is
important
cost, power consumption, low interrupt latency, and ease of use are critical
Examples: industrial control applications, including real-time control systems.

51 / 115
Introduction to ARM Cortex M3

52 / 115
Different ARM Processors and their features

53 / 115
Different ARM Processors and their features

54 / 115
Cotex M3 Applications

I Low-cost microcontrollers
I Automotive
I Data communications
I Industrial controller
I Consumer products

55 / 115
ARM Cortex M3 - Simplified Archtecture

56 / 115
ARM Cortex M3 - Registers

57 / 115
ARM Cortex M3 - Special Registers

58 / 115
ARM Cortex M3 - Operation modes

59 / 115
ARM Cortex M3 - Interrupt Controller Features

I Nested interrupt support

I Vectored interrupt support
I Dynamic priority changes support
I Reduction of interrupt latency
I Interrupt masking

60 / 115
ARM Cortex M3 - Memory MAP

I Predefined Memory Map

I built-in peripherals can be accessed by simple memory access instructions
I Most features are accessible for C programs
I highly optimized for speed and ease of integration in system-on-a-chip

61 / 115
ARM Cortex M3 - Memory Map

62 / 115
ARM Cortex M3 - BUS interface

Main BUS interfaces in Cortex M3 are :

I Code Memory Bus:
I-Code and D-Code
Optimized for instruction fetch to increase speed
I System Bus:
to access memory and peripherals
SRAM, peripherals, external RAM, external devices, and part of the system level
memory regions
I Private Peripheral Bus:
Most features are accessible for C programs
access to a part of the system-level memory dedicated to private peripherals,
such as debugging components.

63 / 115
ARM Cortex M3 - Memory Protection Unit (MPU)

I Optional MPU
I Rules for priviliged access and user program access
I If a rule is voilated fault exception is generated and fault exception handler will
be able to analyze the problem and correct it.
I To protect OS kernel and other previliged process from untrusted programs.
I To prevent accidental erase of data when multi-tasking by isolating memory
regions.

64 / 115
ARM Cortex M3 - Instruction Set

I No state switching overhead, saving both execution time and instruction space
I No need to separate ARM code and Thumb code source files, making software
development and maintenance easier
I It is easier to get the best efficiency and performance, in turn making it easier to
write software, because there is no need to worry about switching code between
ARM and Thumb to try to get the best density/performance

65 / 115
ARM Cortex M3 - Instruction Set

I UFBX, BFI, and BFC: Bit field extract, insert, and clear instructions
I UDIV and SDIV: Unsigned and signed divide instructions
I WFE, WFI, and SEV: Wait-For-Event, Wait-For-Interrupts, and Send-Event to
handle task synchronization on multiprocessor systems
I MSR and MRS: Move to special register from general-purpose register and
move special register to general-purpose register

66 / 115
ARM Cortex M3 - Low Power and High Energy Efficiency

I sleep mode and deep sleep mode supports to reduce power consumption during
idle period
I low gate count and design techniques reduce circuit activities
I Due to high code density, program size is reduced which will reduce active time
and reduce energy
I Wake-up Interrupt Controller to power down, while processor states are retained
and can be active with a simple wake-up call.

67 / 115
ARM Cortex M3 - Debug Support

Debugging features, such as program execution controls, including halting and

stepping, instruction breakpoints, data watchpoints, registers and memory accesses,
profiling, and traces.
I based on the CoreSight architecture. Not part of processor.
I can be interfaced using Debug Access Port (DAP) on core to access Joint Test
Action Group (JTAG) interface.
I can access control registers to debug hardware as well as system memory, even
when the processor is running
I Embedded Trace Macrocell (ETM) to a host like PC via Trace Port Interface
Unit (TPIU) and collect the executed instruction information trace
I Instrumentation Trace Macrocell (ITM): output data to a debugger.
Debugger can collect the data via a trace interface and display or process them.
Easy to use and faster than JTAG output.

68 / 115
ARM Cortex M3 - Registers

69 / 115
ARM Cortex M3 - Registers - Stack Pointer R13

I Main Stack Pointer (MSP) and Process Stack Pointer (PSP)

I stack memory processes - PUSH and POP.
I in Assembly language - R13/SP

70 / 115
Registers - Link Register R14, Program Counter R15,
Special Registers

I R14 - used to store the return program counter (PC) when a subroutine or
function is called
I R15 - is a processor register that indicates where a computer is in its program
sequence
I PC is incremented after fetching an instruction, and holds the memory address
of the next instruction that would be executed
Special Registers
I Program Status registers (PSRs)
I Interrupt Mask registers (PRIMASK, FAULTMASK, and BASEPRI)
I Control register (CONTROL)

71 / 115
Registers - Program Status Registers
I Application Program Status register (APSR)
I Interrupt Program Status register (IPSR)
I Execution Program Status register (EPSR)

72 / 115
Registers - Program Status Registers

73 / 115
Interrupt Mask registers and Control Registers
I PRIMASK: 1-bit register.
it allows nonmaskable interrupt (NMI) and the hard fault exception. all other
interrupts and exceptions are masked
I FAULTMASK: A 1-bit register
it allows only the NMI, and all interrupts and fault handling exceptions are
disabled
I BASEPRI: A register of up to 8 bits
it disables all interrupts of the same or lower level (larger priority value). Higher
priority interrupts can still be allowed
Control RegisterThe control register is used to define the privilege level and the SP
selection. This register has 2 bits

74 / 115
Processor Modes and Privilages

75 / 115
Processor Modes and Privilages

76 / 115
Processor Modes and Privilages

77 / 115
Processor Modes and Privilages

78 / 115
Dual Stack Implementation

79 / 115
Dual Stack Implementation

80 / 115
 Differentiating 16 bit Thumb and 32 bit Thumb-2
instruction bits

1. ADDS R0, #1 Use 16-bit Thumb instruction by default; for smaller size
2. ADDS.N R0, #1 Use 16-bit Thumb instruction (N=Narrow)
3. ADDS.W R0, #1 Use 32-bit Thumb-2 instruction (W=wide)

81 / 115
16 bit Instruction Set
I ADC Add with carry
I ADD Add
I ADR Add PC and an immediate value and put the result in a register
I AND Logical AND
I ASR Arithmetic shift right
I BIC Bit clear (Logical AND one value with the logic inversion of another value)
I CMN Compare negative (compare one data with 2s complement of another
data and update flags)
I CMP Compare (compare two data and update flags)
I CPY Copy (available from architecture v6; move a value from one high or low
register to another high or low register); synonym of MOV instruction
I EOR Exclusive OR
I LSL Logical shift left
I LSR Logical shift right
I MOV Move (can be used for register-to-register transfers or loading immediate
data)
I MUL Multiply
I MVN Move NOT (obtain logical inverted value)
I NEG Negate (obtain twos complement value), equivalent to RSB
82 / 115
Exceptions

1. 1-15 System Exceptions

2. 16-240 interrupts are external interupts
3. current running exception is indicated by the special register
Interrupt Program Status register (IPSR)
4. to check the chip manufacturers datasheets to determine the
numbering of the interrupts

83 / 115
System Exceptions

84 / 115
System Exceptions and Priority

1. Exception affected by the priority of the exception

2. A higher-priority exception can preempt a lower-priority
exception, which is the nested exception/interrupt scenario
3. Some of the exceptions like reset, NMI, and hard fault have
fixed priority levels. They are negative numbers to indicate
that they are of higher priority than other exceptions.
4. Other exceptions have programmable priority levels.
5. three fixed highest-priority levels and up to 256 levels of
programmable priority
6. designers can customize it to obtain the number of levels
required

85 / 115
System Exceptions and Priority

86 / 115
System Exceptions and Priority

87 / 115
Sub Priorities

88 / 115
Vector Tables

when Exception takes place - processor will need to locate the

starting address of the exception handler.
This information is stored in the vector table in the memory.
Minimum things to take care during booting:
I Initial main stack pointer value
I Reset vector
I NMI vector
I Hard fault vector

89 / 115
Interrupt Pending

90 / 115
Interrupt Pending

91 / 115
Fault Exceptions

I Bus faults
I Memory management faults
I Usage faults
I Hard faults

92 / 115
BUS Fault Exceptions

I Instruction fetch, commonly called prefetch abort

I Data read/write, commonly called data abort
In the Cortex-M3, bus faults can also occur during the following:
I Stack PUSH in the beginning of interrupt processing, called a
stacking error
I Stack POP at the end of interrupt processing, called an
unstacking error
I Reading of an interrupt vector address (vector fetch) when the
processor starts the interrupt handling sequence (a special
case classified as a hard fault)

93 / 115
Memory Management and Usage Faults

I Access to memory regions not defined in MPU setup

I Writing to read-only regions
I An access in the user state to a region defined as privileged access only

Usage Faults
I Undefined instructions
I Coprocessor instructions (the Cortex-M3 processor does not support a
coprocessor, but it is possible to use the fault exception mechanism to run
software compiled for other Cortex processors through coprocessor emulation)
I Trying to switch to the ARM state (software can use this faulting mechanism to
test whether the processor it is running on supports the ARM code; because the
Cortex-M3 does not support the ARM state, a usage fault takes place if theres
an attempt to switch)
I Invalid interrupt return (link register contains invalid/incorrect values)
I Unaligned memory accesses using multiple load or store instructions

94 / 115
Hard Faults

The hard fault handler can be caused by usage faults, bus faults,
and memory management faults cannot be executed.
I it can due to bus fault during vector fetch (reading of a vector
table during exception handling).
I In the NVIC, Fault Status Register (FSR) is used to know
whether the fault was caused by a vector fetch. else it need to
check the other FSRs to determine the cause of the hard fault.

95 / 115
Tail-Chaining Interrupts

96 / 115
Late Arrivals - Interrupts

97 / 115
Interrupt Latency

The delay from the start of the interrupt request to the start of
interrupt handler execution
I if the memory system has zero latency, and provided that the
bus system design allows vector fetch and stacking to happen
at the same time, the interrupt latency can be as low as 12
cycles
I includes stacking the registers, vector fetch, and fetching
instructions for the interrupt handler.
I Tail-chaining interrupts ?
I executing a multicycle instruction
I the Cortex-M3 processor allows exceptions in the middle of
Multiple Load and Store instructions

98 / 115
ARM Instruction Pipeline

99 / 115
ARM Instruction Pipeline

100 / 115
ARM Instruction Pipeline

101 / 115
ARM Instruction Pipeline

102 / 115
Architecture and Interfacing in Cortex M3

Advanced High Performance Bus (AHB) and Advanced Peripheral

Bus(APB) are part of Advanced Microcontroller Bus Architecture
(AMBA)
I The I-Code Bus
I The D-Code Bus
I The System Bus
I The External PPB
I The DAP Bus

103 / 115