ARM Cortex-M3

Introduction
ARM University Relations

1
Agenda
Cortex-M3 Overview
v7-M Architecture/Programmers Model
Data Path and Pipelines
Tools and mbed Platform

2
Whats Happening in Microcontrollers?

Microcontrollers are getting cheap

32-bit ARM Cortex-M3 Microcontrollers @ $1
Some microcontrollers sell for as little as $0.65
Microcontrollers are getting powerful
Lots of processing, memory, I/O in one package
Floating-point is even available in some!
Microcontrollers are getting interactive
Internet connectivity, new sensors and actuators
LCD and display controllers are common

Creates new opportunities for microcontrollers

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ARM Cortex-M3 Processor
ETM
NVIC Instruction
ARM
1-240 Interrupts Trace
Cortex-M3
8-256 Priorities Core (5-pins)
I D TPIU Trace Port
Trace Port Serial-Wire
DAP Viewer
JTAG/SWD ITM (1-pin)
MPU
Instrumentation
Trace

DWT
FPB Data Trace
BKPT

Bus Matrix
Code Buses System Bus
to Flash to Stack SRAM
to Code SRAM to Peripherals

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ARM Cortex-M3 Microcontroller
18 x 32-bit registers
Excellent compiler target
Reduced pin count requirements
Efficient interrupt handling
Power management
Efficient debug and development support features
Breakpoints, Watchpoints,
Flash Patch support,
Instruction Trace
Strong OS support
User/Supervisor model
OS support features
Designed to be fully programmed in C (even reset, interrupts and
exceptions)

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ARM Cortex-M3 Microcontroller
ARMv7M Architecture
No Cache - No MMU
Debug is optimized for microcontroller applications
Vector table contains addresses, not instructions
DIV instruction
Interrupts automatically save/restore state
Exceptions programmed in C (No Coprocessor 15 - All registers are memory-mapped)
Interrupt controller is part of Cortex-M3 macrocell
Fixed memory map
Bit-banding
Non-Maskable Interrupt (NMI)
Only one processor status reg
Thumb-2 processing core
Mix of 16 and 32 bit instructions for very high code density
Gives complete Thumb compatibility

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ARM and Thumb Performance

30000

25000

20000
Dhrystone 2.1/sec
@ 20MHz
15000 ARM
Thumb
10000

5000

0
32-bit 16-bit 16-bit with
32-bit stack

Memory width (zero wait state)

7
The Thumb-2 instruction set
Variable-length instructions
ARM instructions are a fixed length of 32 bits
Thumb instructions are a fixed length of 16
bits
Thumb-2 instructions can be either 16-bit or
32-bit

Thumb-2 gives approximately 26%

improvement in code density over ARM

Thumb-2 gives approximately 25%

improvement in performance over
Thumb

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Agenda
Cortex-M3 Overview
v7-M Architecture/Programmers Model
Data Path and Pipelines
Tools and mbed Platform

9
Cortex-M3 Register Set
Main
Very compiler friendly r0

Load/Store Architecture
r1
r2
32-bit registers r3
r4
Flexible register scheme r5

Linear 32-bit address space

r6
r7
r8
r9
r10
r11
r12 Process
sp
sp
lr
r15 (pc)

xPSR

10
Program Status Register
31 28 27 26 25 24 23 16 15 10 7 0

N Z C V Q IT T IT/ICI ISR Number

One Status Register consisting of

APSR - Application Program Status Register ALU flags
IPSR - Interrupt Program Status Register Interrupt/Exception No.
EPSR - Execution Program Status Register
IT field If/Then block information
ICI field Interruptible-Continuable Instruction information
xPSR
Composite of the 3 PSRs
Stored on the stack on exception entry

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An Example AMBA System

High Performance
APB
ARM processor UART

High
Bandwidth AHB Timer
APB
External
Bridge
Memory Keypad
Interface

High-bandwidth DMA PIO

on-chip RAM Bus Master
Low Power
Non-pipelined
High Performance Simple Interface
Pipelined
Burst Support
Multiple Bus Masters

12
Memory Map
Very simple linear 4GB memory map
The Bus Matrix partitions memory access via the AHB and PPB buses
FFFFFFFF
System
E0100000
The image cannot be display ed. Your computer may not hav e enough memory to open the image,
APB Debug Components
or the image may hav e been corrupted. Restart y our computer, and then open the file again. If the
red x still appears, y ou may hav e to delete the image and then insert it again.

E0040000
CM3 Instruction SCS + NVIC
E0000000
Core Data
External Peripheral
The image cannot be display ed. Your computer may not hav e enough memory to open the image, or the image may hav e been corrupt ed. Restart y our computer, and then open the file
again. If the red x still appears, y ou may hav e to delete the image and then insert it again.
1 GB
Bus Matrix INTERNAL PPB
A0000000
with SYSTEM AHB
SYSTEM AHB External RAM
Debug Bit- Bander
Debug ICODE AHB 1 GB
Aligner
and Patch DCODE AHB 60000000
Peripheral GB
40000000
RAM
GB
20000000
Code Space GB
00000000

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NXP LPC1311/13/42/43 Block Diagram

14
NXP LPC1311/13/42/43 Memory Map

15
Processor Privilege
ARM Cortex-M3

Privileged Aborts
Supervisor Interrupts
Reset
Handler Mode
OS

System Call (SVCall)

Undefined Instruction

User Non-Privileged
Thread Mode Application code

Memory

Instructions & Data

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Memory Protection Unit (MPU)

MPU provides access control for various memory regions

Zero Latency Memory Protection

8 register-stored regions
Same regions used for instructions and data
Minimum region size 32 Bytes (max 4GB)
No address translation or page tables

Configured via memory-mapped control registers

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Cortex-M3 Bit Banding

Traditional Method of Atomic Manipulation

0 0 0 0 0 0 0 0 Read byte from SRAM

0x02000000

Mask and Modify

x x x x x 1 x x
Bit Element
0x02000000

0 0 0 0 0 1 0 0 Write byte to SRAM

0x02000000

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Cortex-M3 Bit Banding
Writes to a word address in the
bit band alias affect a single bit in
the bit band region
The write is translated to an atomic
read-modify-write by the Cortex-M3
bus matrix
Bit 0 of the stored register is written
to the appropriate bit

Word alias 32MB Bit band alias

32MB

31MB

Physical bit 1MB Bit band region

32MB Bit band alias

31MB

1MB Bit band region

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Conditional Execution
If Then (IT) instruction added (16 bit)
Up to 3 additional then or else conditions maybe specified (T or E)
Makes up to 4 following instructions conditional

ITTET EQ MOVEQ
Inst 1 ADDEQ
Inst 2
SUBNE
Inst 3
Inst 4 ORREQ

Any normal ARM condition code can be used

16-bit instructions in block do not affect condition code flags
Apart from comparison instruction
32 bit instructions may affect flags (normal rules apply)
Current if-then status stored in CPSR
Conditional block maybe safely interrupted and returned to
Must NOT branch into or out of if-then block

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Interrupt Handling
One Non-Maskable Interrupt (INTNMI) supported
1-240 prioritizable interrupts supported
Interrupts can be masked
Implementation option selects number of interrupts supported
Nested Vectored Interrupt Controller (NVIC) is tightly coupled with processor core
Interrupt inputs are active HIGH

INTNMI

1-240 Interrupts NVIC

Cortex-M3

INTISR[239:0] Processor Core

Cortex-M3

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Exception Handling
Reset
NMI
Faults
Hard Fault
Memory Manage
Bus Fault
Usage Fault
SVCall
Debug Monitor
PendSV
SysTick Interrupt
External Interrupt

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Power Management
Multiple sleep modes supported
Controlled by NVIC
Sleep Now Wait for Interrupt/Event instructions
Sleep On Exit Sleep immediately on return from last ISR
Deep Sleep
Long duration sleep, so PLL can be stopped
Exports additional output signal SLEEPDEEP

Cortex-M3 system is clock gated in all sleep modes

Sleep signal is exported allowing external system to be clock gated also
NVIC interrupt Interface stays awake

Wake-Up Interrupt Controller (WIC)

External wake-up detector allows Cortex-M3 to be fully powered down
Effective with State-Retention / Power Gating (SRPG) methodology

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Cortex-M3 Debug
Single stepping
ITM (Instrumentation Trace Module)
Support for instrumented code
Like printf debugging, but single cycle writes to ITM module can be exported via serial
interface
Optional ETM (Embedded Trace Module) which provides instruction trace
Access to all memory and registers via Debug Access Port (DAP)
Profiling Support
Helps you optimize your code
A hardware triggered PC-sampler is provided by the Cortex-M3 core
Flash patch / Breakpoints
6 instruction comparators, ARMv5T BKPT instruction is supported
2 literal comparators
Allows flash code to be remapped into SRAM or system address space
Data Watchpoint and Trace (DWT) that implements 4 h/w watchpoints

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Agenda
Cortex-M3 Overview
v7-M Architecture/Programmers Model
Data Path and Pipelines
Tools and mbed Platform

25
 Cortex-M3 Datapath
I_HRDATA Instruction
Decode

Write Data D_HWDATA

Address Register
Incrementer
D_HRDATA
D_HADDR Read Data
Address Register
Register

Address
Register Barrel
Incrementer Mul/Div
Bank Shifter
I_HADDR ALU
A ALU
Address
Register
Writeback

INTADDR

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Cortex-M3 Pipeline
Cortex-M3 has 3-stage fetch-decode-execute pipeline
Similar to ARM7
Cortex-M3 does more in each stage to increase overall
performance

1st Stage - Fetch 2nd Stage - Decode 3rd Stage - Execute

Address Data Phase

AGU Phase & Write Load/Store &
Back Branch

Instruction
Fetch
Decode & Multiply & Divide Write
(Prefetch)
Register Read

Branch Shift ALU & Branch

Branch forwarding & speculation

Execute stage branch (ALU branch & Load Store Branch)

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Optimal Pipelining

Cycle 1 2 3 4 5 6 7 8 9
Operation
ADD F D E
SUB F D E
ORR F D E
AND F D E
ORR F D E
EOR F D E

F - Fetch D - Decode E - Execute

All operations here are on registers (single cycle execution)

In this example it takes 6 clock cycles to execute 6 instructions
Clock cycles per Instruction (CPI) = 1
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Branch Pipeline Example

Cycle 1 2 3 4 5 6 7 8 9
Address Operation
0x8000 BX r5 F D E
0x8002 SUB F D
0x8004 ORR F
0x8FEC AND F D E
0x8FEE ORR F D E
0x8FF0 EOR F D E

F - Fetch D - Decode E Execute

It takes 3 cycles to complete the branch

Worst case scenario indirect branch taken

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LDR Pipeline Example
Cycle 1 2 3 4 5 6 7 8 9
Operation
ADD F D E
SUB F D E
LDR F D Ea Ed
AND F D S E
ORR F S D E
EOR F D E

F - Fetch D - Decode E Execute S - Stall

Ea LDR address phase Ed LDR data phase

In this example it takes 7 clock cycles to execute 6 instructions

Clock cycles per Instruction (CPI) = 1.2
The read cycle must complete on the bus before the LDR
instruction can complete since there is only one writeback port in
the register file

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STR-STR Pipeline Example
Cycle 1 2 3 4 5 6 7 8 9
Operation
ADD F D E
SUB F D E
STR F D Ea Ed
STR F D Ea Ed
ORR F D E
EOR F D E

F - Fetch D - Decode E Execute S - Stall

Ea Execute / STR address phase Ed STR data phase

Store buffer allows STR instruction to finish before store

cycle completes on the bus
Back-to-back STR instructions pipeline on the AHB-Lite bus
- Also works for LDR-STR-LDR-STR

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Agenda
Cortex-M3 Overview
v7-M Architecture/Programmers Model
Data Path and Pipelines
Tools and mbed Platform

32
RVMDK Software Development Tools

Includes ARM macro assembler, compilers (ARM RealView C/C++

Compiler, Keil CARM Compiler, or GNU compiler), ARM linker, Keil uVision
Debugger and Keil uVision IDE
Keil uVision Debugger accurately simulates on-chip peripherals (I2C, CAN,
UART, SPI, Interrupts, I/O Ports, A/D and D/A converters, PWM, etc.)
Evaluation Version
16K byte object code + 16K data limitation
Some linker restrictions such as base addresses for code/constants
GNU tools provided are not restricted in any way
http://www.keil.com/demo/

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RVMDK Software Development Tools

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Cortex-M3 Development Platforms

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Rapid Prototyping
Rapid Prototyping helps industries create new products
Control, communication and interaction increasingly define products
Development cycles for microelectronics have not kept pace

3D Moulding 3D Printing 2D/3D Design Web Frameworks

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mbed
Getting Started and Rapid Prototyping with ARM MCUs
Complete Targeted Hardware, Software and Web 2.0 Platform

Dedicated Developer Lightweight Online Compiler

Web Platform

http://mbed.org

Rapid Prototyping
for Microcontrollers
High-level Peripheral APIs Cortex-M3 MCU in a
Prototyping Form-Factor

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mbed Motor Controller Example
#include "mbed.h
DigitalOut leftfwd(p16);
DigitalOut leftrev(p17);
PwmOut pwm(p21);
AnalogIn pot(p20);
int main(){
pwm.period_ms(1);
while(1){
float potmod = pot - 0.5;
if (potmod >= 0){
leftfwd = 1;
leftrev = 0;
pwm=((1.8 * potmod) + 0.1);
} else {
leftfwd = 0;
leftrev = 1;
pwm = fabs((1.8 * potmod) - 0.1);
}
}
}

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Documentation

ARM v7-M Architecture Reference Manual (ARM v7-M

ARM)

Cortex-M3 Technical Reference Manual (TRM)

ARM Debug Interface V5 Architecture Spec (ADIv5)

The Definitive Guide To The ARM Cortex-M3 by Joseph

Yiu (Elsevier)

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University Resources

http://www.arm.com/support/university/

university@arm.com

http://www.mbed.org/

http://www.keil.com/

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 Fin

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