F.

Maloberti

Layout of Analog
CMOS
Integrated Circuit
Part 2
Transistors and Basic Cells Layout

F. Maloberti - Layout of Analog CMOS IC

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 Outline
Introduction
Process and Overview Topics
Transistors and Basic Cells Layout
Passive components: Resistors, Capacitors
System level Mixed-signal Layout

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 Part II: Transistor and Basic Cell Layout

Transistors and Matched Transistors

Layout of a single transistor
Use of multiple fingers
Interdigitated devices
Common Centroid
Dummy devices on ends
Matched interconnect (metal, vias, contacts)
Surrounded by guard ring
Design for Layout
Stacked layout of analog cells
Stick diagram of analog cells
Example 1: two stages op-amp
Example 2: folded cascode

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 Single Transistor Layout
A CMOS transistor is the crossing of two rectangles,
polysilicon and active area
but, we need the drain and source connections and we
need to bias the substrate or the well

Polysilicon gate

diffusion

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 Source and Drain Connections
Ensure good connections

Multiple contacts or one big contact?

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 Multiple or single contacts?
Curvature in the metal layer can lead to micro-fractures

Not important for large areas

Reliability problems, possible electro-migration

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 Multiple contacts: Exercise
Consider the following design rules:
minimum contact 0.5
spacing contact-contact 0.4
minimum grid strep 0.1
spacing contact diffusion 0.6
Estimate the number of contacts and their spacing for
W=50
W=52
W=60

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 Matching single Transistors
Regular (rectangular shape)
the W and L matter!!

Parallel elements
silicon is unisotropic

Possibly, the current flowing

in the same direction

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 Asymmetry due to Fabrication

An MOS transistor is not a symmetrical device. To avoid channeling of

implanted ions the wafer is tilted by about 7 .

Shadowed region

Source and drain are not equivalent

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 Parasitics in Transistors
Analog transistors often have a large W/L ratio
W
LD

Capacitance diffusion substrate

CSB = C DB = (W + 2ldiff )( LD + 2ldiff )

Resistance of the poly gate

Rgate = Lgate Rsq , poly

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 Use of multiple fingers
W
S
C ' SB ; C ' DB
D
W/2 W/3
D S
2
CSB = C ' SB
S D 3

S 2
D C DB = C ' DB
3
1 ' D
CSB = C DB ; C DB = C DB
2
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 Parasitic in Transistors: Exercise
Calculate the parasitic capacitance diffusion-
substrate for a 40 micron width transistor
one finger
5 finger
8 finger

Use the design rules available and minimum diffusion length

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 Interdigitated Devices
Two matched transistors with one node in common
spilt them in an equal part of fingers (for example 4)
interdigitate the 8 elements: AABBAABB or ABBAABBA
1 2 2

A A B B A A B B A B B A A B B A

3 3
1 1

A B

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 Axis of Symmetries

Common axis Axis of symmetry

Axis of symmetry of device B Common axis of
of symmetry of device A symmetry

A B B A A B A B A B A

(A) (B) (C)

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 Interdigitiation Patterns

A AA AAA AAAA
AB* ABBA ABBAAB* ABABBABA
ABC* ABCCBA ABCBACBCA* ABCABCCBACBA
ABCD* ABCDDCBA ABCBCADBCDA* ABCDDCBAABCDDCBA
ABA ABAABA ABAABAABA ABAABAABAABA
ABABA ABABAABABA ABABAABABAABABA ABABAABABAABABAABABA
AABA* AABAABAA AABAAABAAABA* AABAABAAAABAABAA
AABAA AABAAAABAA AABAAAABAAAABAA AABAAAABAAAABAAAABAA

Note: not all the patterns permit a stacked layout

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 Interdigitated Transistors: Exercises
Sketch the layout of two interdigitated transistors
having W1=3W2 and split W2 into 4 fingers. M1 and M2
have their source in common.

Sketch the layout of three interdigitized transistors

having the same width. Use the optimum number of
fingers. The three transistors have the source in
common.

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 Common Centroid

DA DB DA DB

DB DA DB DA

Gradients in features are compensated for (at first

approximation)
metal and poly interconnections are more complex
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 Common Centroid Arrays

A B B A
A B

B A
B A A B

Cross coupling Tiling (more sensitive to

high-order gradients)

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 Common Centroid Patterns

ABBA ABBAABBA ABBAABBA ABBAABBA

BAAB BAABBAAB BAABBAAB BAABBAAB
ABBAABBA BAABBAAB
ABBAABBA

ABA ABAABA ABAABA ABAABAABA

BAB BABBAB BABBAB BABBABBAB
ABAABA BABBABBAB
ABAABAABA

ABCCBA ABCCBAABC ABCCBAABC ABCCBAABC

CBAABC CBAABCCBA CBAABCCBA CBAABCCBA
ABCCBAABC CBAABCCBA
ABCCBAABC

AAB AABBAA AABBAA AABBAA

BAA BAAAAB BAAAAB BAAAAB
AABBAA BAAAAB
AABBAA

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 Dummy Devices on Ends
Ending elements have different boundary conditions
than the inner elements -> use dummy

b d

Dummies are shorted transistors

Remember their parasitic contribution!

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 Matched interconnections
Specific resistance of metal lines
Specific resistance of poly
Resistance of metal-contact
V = Z int I
Resistance of via

Minimize the interconnection impedance

Achieve the same impedance in differential paths
Keep short the width of fingers for high speed applications

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 Matched Metal Connection

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 Waffle Transistor

S Minimum capacitance
drain-substrate and
source-substrate

W not accurate
L not well defined
D
To be used in wide transistors
whose aspect ratio is not
relevant

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 Part II: Transistor and Basic Cell Layout

Transistors and Matched Transistors

Layout of a single transistor
Use of multiple fingers
Interdigitated devices
Common Centroid
Dummy devices on ends
Matched interconnect (metal, vias, contacts)
Surrounded by guard ring
Design for Layout
Stacked layout of analog cells
Stick diagram of analog cells
Example 1: two stages op-amp
Example 2: folded cascode

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 Stacked Layout
Systematic use of stack or transistors (multi-finger
arrangement)
Same width of the fingers in the same stack, possibly
different length
Design procedure
Examine the size of transistors in the cell
Split transistors size in a number of layout oriented fingers
Identify the transistors that can be placed on the same stack
Possibly change the size of non-critical transistors
Use (almost) the same number of finger per stack
place stacks and interconnect

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Stick Representation (one transistor)
s
EVEN ODD

d d s d s d s d s d

Ending drain S/D ending

s d s d s d s d s

Ending source D/S ending

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 Multi-transistor Stick Diagram
2
1 2 3 4 2 1 2 3 4
M1 M2
3 Same width M1 double
1 M3
4 2
1 2 1 2 3 2 3 4 3 4 3
M1 M2 M3 1
4

3 4 3 2 1 2 3 4 3 3 4 3 2 1 2 1 2 3 4 3
M3 M2 M1 M2 M3 M3 M2 M1 M2 M3
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 Example 1 (2 stages OTA)

Assume to layout a two stages OTA

30 30 108
M3 M4
M6
M1 M2
60 60
72
M5
M7
40

Width only are shown;

Compensation network and bias are missing (!)

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 Layout Oriented Design

30 30
Only width matters
108
M3 M4
M6 Possible stacks:
M1 M2 1 p-channel, 2 n-channel
60 60
72
change the size of M6 and M7
M5 to 80 and 120 respectively
M7
40
Width of each finger?
We want the same number of
fingers per stack (k).
M3, M4, M6 Wp1 = 180/k
M1, M2 Wn1=120/k
Wn2=120/k
M5, M7
for M3 and M4 use 2 fingers
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 Stack Design and Interconnections
VDD
M6 M3 M4 M6 2 2 8
M3 M4 O1
D3 M6
D3 O1 M1 M2
6 CS 6 OUT
8
M5
M7
4 GND
M1 M2

First attempt of
interconnections
(not completed)
M7 M5 M7

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 Use of one Metal Layer
VDD
VDD
M3 M4 O1
M3 M4 D3 M6
M1 M2
O1 CS OUT

M5
CS M2 M7
M1 OUT GND

Use metal for carrying

M5 M5 current!
Poly connections are
GND
not a problem (usually)

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 Stick Layout: Exercise

Draw the stick diagram of the two stages OTA in

the following three cases:
fingers of M6 and M7 all together

M6 =90 M7=60

M1 and M2 in a common centroid arrangement

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 From Stick to Layout
Input-Output
Well and its bias VDD
Substrate bias
Compensation
Bias voltage
Bias current

Rectangular shape
System oriented cell layout
Related cells with same height
Vdd and GND crossing the cell
In and Out properly placed GND
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 Example 2 (Folded Cascode)
20 30 30 Only Ws are shown
MP M4

M3
M6
60 60
M5

M1 M2 38
38
80 80 M7 M8

MN M11 M9 M10
16
16 25 25

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 Split of Transistors
20 30 30
MP 2 3
3
M3 M4
M5 M6
6
6
60 60

M1 M2 5 5
40 40
80 80 M7 M8
38
3 3
MN M11 M9 M10
16
16 2 2 25 24 24

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 Stack Design

M4 555555344PP334666666
MP 2 3
3
M3
M6 11221122112211221122
M5 6
10x2 6 22112211221122112211
M1 M2 5 5
M8
M7
777779xxoo99nno88888
MN M11 M9 M10
2 2 3 3

X=11; o=10

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 Interconnection: Exercise
Sketch the source-drain interconnections of the folded-cascode

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 Basic Cell Design: check-list
Draw a well readable transistor Define the expected height
diagram (or width) of the cell
Identify critical elements and Sketch the stick diagram
nodes
transistors of the same type in
Absolute and relative accuracy the same region
Minimum parasitic capacitance
Foresee room for substrate
Minimum interference
and well biasing
Mark transistors that must
substrate bias around the cell
match
well-bias surrounding the well
Mark symmetry axes
Define the connection layer
Analyze transistor sizing (Ws)
for input-output (horizontal,
Possibly, change transistor size vertical connections)
for a layout oriented strategy
Begin the layout now!!
Group transistors in stacks

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