Overview

n Timing
n Our designs are limited by getting data between FFs
Lecture 5: Timing n Combinational Logic delay, Routing delay, and FF
parameters dictate the maximum speed
n Clock Distribution
n H-Tree format for getting clocks at the same time
n Dedicated clock routing tries to reduce skew and jitter
David Black-Schaffer
n FF Timing
davidbbs@stanford.edu n Make sure the slowest path is fast enough for the FF
EE183 Spring 2003 based on the clock (MaxPath)
n Make sure the fastest path is not too fast for the FF
based on the clock (MinPath)
EE183 Lecture 5 - Slide 2

Logistics FSM Review

n Any questions?
n Lab 1 requirements clear?
n Demo due Friday at 5pm.
Well be in the lab from 3-5 on Friday.
A Finite State Machine is simply a state
register that holds the current state and
some combinational logic which
calculates the next state and outputs based
on the current state and the inputs.

n A feedback system which updates on each

clock

EE183 Lecture 5 - Slide 3 EE183 Lecture 5 - Slide 4

1
 always @(current_state_q or button)
begin

What is it really? case(current_state_q)

`STOP: begin
The next state must
go = 1'b0;
if (button) begin
ALWAYS be defined.
next_state_d = `GO;

n A bunch of MUXes which select the next else

end
begin
next_state_d = `STOP; Any output must be
state & outputs based on the current state end
end
defined in EVERY
(FFs) & inputs. `GO: begin
go = 1'b1; state.
if (button) begin
next_state_d = `STOP;

else
end
begin
If any states are ever
n Keep this in mind when writing your next_state_d
end
= `GO; not used they MUST
be included in a
verilog. end
default: begin
go = 1'b0; default statement.
next_state_d = `STOP;
end
endcase
an else for every if
a default for every case
EE183 Lecture 5 - Slide 5
every output must be defined in every state
EE183 Lecture 5 - Slide 6

Public Service Announcement Timing

n Xilinx Programmable World n What limits our speed?
n Tuesday, May 6th n RTL design - Register Transfer Logic
n Speed limited by the time it takes to get from one
n http://www.xilinx.com/events/pw2003/index.htm
register (flip flop) to another
n Guest Lectures n State machines and pipeline data stages
n Monday, April 28th n What gets in the way?
Ryan Donohue on Metastability and n Combinational logic delay
Synchronization n Routing delay
n Wednesday, May 7th n Clock skew and delay
Gary Spivey on ASIC & FPGA Design for Speed n FF setup and hold time requirements
n The content of these lectures will be on the Quiz

EE183 Lecture 5 - Slide 7 EE183 Lecture 5 - Slide 8

2
 Combination Logic Delay Routing Delay
n Time to get through gates n This can be (IS!) the real killer
n The more gates (more complicated logic) the slower
n FPGA wiring slow compared to ASIC
n One-hot encoding
n Lots of switches to go through
n Well, sort of:
n Wires dont go exactly where you want
n FPGA doesnt have gates we have those 4-input
LUTs (look-up-tables) n Routing can be ~50% of your total delay
n All functions of 4 inputs or less are the same speed
n Manual placement? NP-hard problem?
n >4 inputs and we have to hook up multiple CLBs
(routing delay) n Hope the tools work well!

EE183 Lecture 5 - Slide 9 EE183 Lecture 5 - Slide 10

Clock Distribution Skew

n How do we get the same clock signal n FPGA Structure: very regular, easy
everywhere at the same time? distribution CLK

n ASIC: Random logic, different #s of FFs

n H-Tree distribution
in different places
n Is is perfect? No, we have:
n Skew - static variation in time of arrival at different
FFs
n Due to path length differences
n Jitter - cycle-varying variation in arrival at the same
FF
n Oscillator/PLL inaccuracies, differential heating, cross-talk

EE183 Lecture 5 - Slide 11 EE183 Lecture 5 - Slide 12

3
 Jitter
EE183 Lecture 5 - Slide 13
FF Timing Constraints
n What happens if D and CLK change at the same
time?
n How close can these get?
n Determined by the Setup and Hold times
n What happens if we try to use Q right after the
clock?
n How long do we have to wait?
n Determined by Tclk->Q
n Do we care?
n Mostly concerned about MaxPath, but MinPath
violations can be serious in ASICs
n Also, this will be on the midterm Quiz
EE183 Lecture 5 - Slide 15
What is Faster?
n Is a 1.1GHz P4 faster than a 933MHz P3?
n Wall clock time is all that matters.*
n How long does it take to get your answer
n Faster clock speed doesnt mean you do more
n Pipelining: less of each instruction per clock, but more
instructions and more clocks = greater throughput
*Unless you have a really good marketing
department.
**Also, power matters a lot!
EE183 Lecture 5 - Slide 14
Setup and Hold Times
n Setup Time: the amount of time the
synchronous input (D) must be stable
before the active edge of the clock
n Hold Time: the amount of time the
synchronous input (D) must be stable
after the active edge of the clock
n If either is violated correct operation of the
FF is not guaranteed
n Metastability can result.
EE183 Lecture 5 - Slide 16
4
 Setup and Hold Diagram Tclk->Q
n Tclk->Q: the amount of time you have to
Tsetup Thold
wait after the CLK before the output (Q) is
valid
CLK n If you try to use the output before this you
will get inconsistent results depending on
D can change Stable D can change if Q changes

EE183 Lecture 5 - Slide 17 EE183 Lecture 5 - Slide 18

Tclk->Q Diagram Example Parameters

n DFF values:
Tsetup Thold n Tclk->q=1ns, T setup=1ns, T hold=1ns
n Clock skew is max 2ns and jitter is 2ns
CLK n Combinational logic
n max time: Tcl_pdmax=10ns
n min time: Tcl_pdmin=1ns
D can change Stable D can change

Q Stable Unstable New Q Stable

Tclk->Q

EE183 Lecture 5 - Slide 19 EE183 Lecture 5 - Slide 20

5
 MaxPath Timing Constraint
n Add up the components that result in the time
budget; the period must be greater than this
value.
n Tclk->q+Tcl_pdmax+Tsetup+Tskew<= Clock Period
n 1 + 10 + 1 + 2 <= Clock Period
n 14ns <= Clock Period
n Max Frequency is 71MHz
n Longest one is the Critical Path
EE183 Lecture 5 - Slide 21
MinPath and ShiftRegisters
n Shift Registers can easily fall prey to min
path timing violations.
n Fix the violations by increasing delay
between Ds and Qs
n Insert pairs of inverters
n FPGA DFF clk->q is big
enough so that MinPath
violations are rare.
EE183 Lecture 5 - Slide 23
MinPath Timing Constraint
n Consider what happens when the same
clock edge is considered at the far DFF.
n Tclk->q+Tcl_pdmin >= Tskew + Thold
n 1 + 1 >= 2 + 1
n Whoops!! The new value from FF A can
get there so fast that when the clock
arrives the new value may change before
it has been latched in to FF B.
n AKA, Hold-Time Violation
EE183 Lecture 5 - Slide 22
Impacts
n You can fix MaxPath timing constraint
violations by slowing down the clock after
the circuit is implemented.
n Give the logic more time to get the result to
the FF
n You cannot fix MinPath timing
constraint violations be modifying the
clock.
n How do you prevent the logic from changing
too quickly?
EE183 Lecture 5 - Slide 24
6
 Lecture 5 Key Points
n Speed is a function of how fast you can get from
FF to FF.
n Routing and combinational logic delay is what
will mostly bite you in this class.
n FFs themselves do have input and output timing
requirements of which you need to be aware

n Logistics
n Lab 1 DEMO due Friday at 5pm.
n Office Hours: Mon/Wed/Fri 10-11am,
Tue/Thur 7-9pm, and demos Fri 3-5pm
EE183 Lecture 5 - Slide 25