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Lect2UP230 (100327) PDF
Lect2UP230 (100327) PDF
Design Inputs
Boundary conditions:
1. Process specification (VT, K', Cox, etc.)
2. Supply voltage and range
3. Supply current and range
4. Operating temperature and range
Requirements:
1. Gain
2. Gain bandwidth
3. Settling time
4. Slew rate
5. Common-mode input range, ICMR
6. Common-mode rejection ratio, CMRR
7. Power-supply rejection ratio, PSRR
8. Output-voltage swing
9. Output resistance
10. Offset
11. Noise
12. Layout area
M6
M3 M4 Cc
Topology- M1 M2
vout
CL
vin
+
+ M7
VBias M5
-
DC Currents VSS
W/L ratios W
Component C R
values
060625-06
M6
M3 M4 Cc
vout
- M1 M2 CL
vin
+
+ M7
VBias M5
-
VSS Fig. 6.3-1
Notation:
Wi
Si = Li = W/L of the ith transistor
S6 2S7
4.) For balance, I6 must equal I7 S4= S5 called the balance conditions
5.) So if the balance conditions are satisfied, then VDG4 = 0 and M4 is saturated.
Op Amp Specifications
The following design procedure assumes that specifications for the following parameters
are given.
1. Gain at dc, Av(0)
Max. ICMR
2. Gain-bandwidth, GB and/or p3
VDD Vout(max)
3. Phase margin (or settling time) VSG4
+
VSG6
+
- -
4. Input common-mode range, ICMR M6 gm6 or
M3 M4 C Proper Mirroring
5. Load Capacitance, CL gm1
c I 6
VSG4=VSG6
GB =
6. Slew-rate, SR -
Cc vout
Cc 0.2CL CL
7. Output voltage swing vin M1 M2
(PM = 60)
+
8. Power dissipation, Pdiss Min. ICMR I 5 I5 = SRCc
Vout(min)
+
VBias M5 M7
-
VSS Fig. 160-02
j
j3 Loop
Gain RHP Zero Boost
j2 0dB log10
180 > 1 > 2 > 3
180
3 Loop
j1 2
1 Phase
Shift
z1 360 log10
060626-03 RHP Zero Lag
Solution of the problem:
The compensation comes from the feedback path through Cc, but the RHP zero
comes from the feedforward path through Cc so eliminate the feedforward path!
Use of Buffer to Eliminate the Feedforward Path through the Miller Capacitor
Model: C c
+1 Cc
VI
The transfer + +
function is given Inverting vOUT Vin gmIvin CI RI Vout Vo
gmIIVI RII CII
High-Gain - -
by the following Stage
V o(s) (gmI)(gmII)(RI)(RII)
=
V in(s) 1+s[RICI+RIICII+RICc+gmIIRIRIICc]+s2[RIRIICII(CI+Cc)]
Using the technique as before to approximate p1 and p2 results in the following
-1 -1
p1 RICI+RIICII+RICc+gmIIRIRIICc gmIIRIRIICc
and
-gmIICc
p2 CII(CI+Cc)
Comments:
Poles are approximately what they were before with the zero removed.
For 45 phase margin, |p2| must be greater than GB
For 60 phase margin, |p2| must be greater than 1.73GB
CMOS Analog Circuit Design P.E. Allen - 2010
Lecture 230 Design of Two-Stage Op Amps (3/27/10) Page 230-19
Use of Buffer with Finite Output Resistance to Eliminate the RHP Zero
Assume that the unity-gain buffer has an output resistance of Ro.
Model:
Cc Ro
+1 Cc
VI
+ Vout +
vOUT Vin gmIvin CI RI Ro Ro Vout
Inverting
gmIIVI RII CII
High-Gain - -
Stage
Fig. 430-03
It can be shown that if the output resistance of the buffer amplifier, Ro, is not neglected
that another pole occurs at,
-1
p4 Ro[CICc/(CI+Cc)]
and a LHP zero at
-1
z2 RoCc
Closer examination shows that if a resistor, called a nulling resistor, is placed in series
with Cc that the RHP zero can be eliminated or moved to the LHP.
Use of Nulling Resistor to Eliminate the RHP Zero (or turn it into a LHP zero)
Cc Rz
Cc Rz
VI
+ +
vOUT Vin gmIvin CI RI Vout
Inverting CII
gmIIVI RII
High-Gain - -
Stage
Fig. 430-04
Nodal equations:
VI sCc
gmIV in + RI + sCIV I + 1+sCcRz (VI - Vout) = 0
Vo sCc
gmIIV I + RII + sCIIV out + 1+sCcRz (Vout - VI) = 0
Solution:
V out(s) a{1-s[(Cc/gmII)-RzCc]}
V in(s) = 1+bs+cs2+ds3
where
a = gmIgmIIRIRII
b = (CII + Cc)RII + (CI + Cc)RI + gmIIRIRIICc + RzCc
c = [RIRII(CICII + CcCI + CcCII) + RzCc(RICI + RIICII)]
d = RIRIIRzCICIICc
W,J. Parrish, "An Ion Implanted CMOS Amplifier for High Performance Active Filters", Ph.D. Dissertation, 1976, Univ. of CA., Santa Barbara.
CMOS Analog Circuit Design P.E. Allen - 2010
Lecture 230 Design of Two-Stage Op Amps (3/27/10) Page 230-21
A Design Procedure that Allows the RHP Zero to Cancel the Output Pole, p2
We desire that z1 = p2 in terms of the previous notation.
Therefore,
1 -gmII j
=
Cc(1/gmII-Rz) CII
-p1
The value of Rz can be found as -p4 -p2 z1 Fig. 430-06
Cc+CII
Rz = Cc (1/gmII)
With p2 canceled, the remaining roots are p1 and p4(the pole due to Rz) . For unity-gain
stability, all that is required is that
Av(0) gmI
|p4| > Av(0)|p1| = gmIIRIIRICc = C
c
and (1/RzCI) > (gmI/Cc) = GB
Substituting Rz into the above inequality and assuming CII >> Cc results in
gmI
Cc > gmIICICII
This procedure gives excellent stability for a fixed value of CII ( CL).
Unfortunately, as CL changes, p2 changes and the zero must be readjusted to cancel p2.
CMOS Analog Circuit Design P.E. Allen - 2010
Lecture 230 Design of Two-Stage Op Amps (3/27/10) Page 230-23
Incorporating the Nulling Resistor into the Miller Compensated Two-Stage Op Amp
Circuit: VDD
M11 M3 M4 V
B
VA M6
M10 CM Cc vout
M8
VC vin- vin+
M1 M2
CL
IBias
M9 M5
M12 M7
Cc+CL 1 M10
z1 = p2 Rz = gm6ACC = gm6B M11
M3 M4
Which gives M6
vou
C c - M1 M2 M6B
gm6B = g
m6A C +C
vin CL
c L Cc
+
In the previous example, M8 M9
+ M7
gm6A = 950S, Cc = 3pF VBias M5
-
and CL = 10pF. VSS Fig. 6.3-4A
B.K. Ahuja, An Improved Frequency Compensation Technique for CMOS Operational Amplifiers, IEEE J. of Solid-State Circuits, Vol. SC-18,
No. 6 (Dec. 1983) pp. 629-633.
CMOS Analog Circuit Design P.E. Allen - 2010
Lecture 230 Design of Two-Stage Op Amps (3/27/10) Page 230-29
1+gm8
Iin =
G1G2
1+s Cc +C2 +Cc +gm6Cc
+s2
CcC2
Using the approximate method of solving for the roots of the denominator gives
-1 -6
p1 = C
Cc C2 gm6Cc gm6rds2Cc
c
gm8 G2+G2+ G1G2
+
gm6rds2Cc
- 6 gm8rds2G2
gm6
gm8rds
and p2 CcC2 = 6
=
C2 3 |p2|
gm8G2
where all the various channel resistance have been assumed to equal rds and p2 is the
output pole for normal Miller compensation.
Result:
Dominant pole is approximately the same and the output pole is increased by gmrds.
Concept:
3 3
Rout = rds7|| gm6gm8r
gm6gm8rds8
ds8
Therefore, the output pole is VDD VDD
approximately,
rds7 gm8rds8 rds7
gm6gm8rds8 Cc 3
|p2| 3CII vout vout
1
M8 GBCc 0 M6
CII
M6 CII
V2 - VDD Av(V1-V2)
Vout V1 Vout
V1 +
Vss VSS AddVdd
Fig. 180-02
V out = AddV dd + Av(V1-V 2) = AddV dd - AvV out Vout(1+Av) = AddV dd
V out Add Add 1
V dd 1+Av Av PSRR+ (Good for frequencies up to GB)
= =
Vout
M6 VDD Vdd 1
Cc Vout RoutCc
M3 M4 Cc Vout 0dB
M5 rds7
M7 Vss Path through Cgd7
VBias
is negligible
VBias connected to VSS VSS
What is Zout? Fig. 180-11
Vt
gmIV t
Zout = I It = gmIIV 1 = gmIIG +sC +sC
t I I c
GI+s(CI+Cc) Cc CII+Cgd7 It
Thus, Zout = gmIgMII
+ rds6||rds7 +
CI RI V1 gmIIV1 Vout Vt
gmIVout
- -
Fig.180-12
rds7
V out 1+Zout s(Cc+CI)+GI+gmIgmIIrds7 -GI
V ss = 1 = s(Cc+CI)+GI Pole at Cc+CI
The negative PSRR is much better than the positive PSRR.
CMOS Analog Circuit Design P.E. Allen - 2010
SUMMARY
The output of the design of an op amp is
- Schematic
- DC currents
- W/L ratios
- Component values
Design procedures provide an organized approach to creating the dc currents, W/L
ratios, and the component values
The right-half plane zero causes the Miller compensation to deteriorate
Methods for eliminating the influence of the RHP zero are:
- Nulling resistor
- Increasing the magnitude of the output pole
The PSRR of the two-stage op amp is poor because of the Miller capacitance, however,
methods exist to eliminate this problem
The two-stage op amp is a very general and flexible op amp