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BI GING
CU TRC MY TNH
(Computer Structure)
Cu trc My tnh
(Computer Structure)
Trnh by: inh ng Lng.
T: 058.832078
Mobile: 0914147520
Email: luongdd10@yahoo.com
Mc ch:
Tm hiu cu trc v t chc cc my tnh.
Tm hiu nguyn l hot ng c bn My tnh.
Gii thiu cu trc my tnh tin tin ca Intel.
Yu cu:
C kin thc lp trnh c bn.
Sinh vin c ti liu v lm vic theo nhm thc
hin bo co trn lp.
@www.williamstallings.com
@ocw.mit.edu
@www.intel.com
@www.asus.com
@www.gigabyte.com
@www1.guidePC.com
B x l : iu khin v x l s liu.
B nh : cha chng trnh v d liu.
H thng vo ra : trao i thng tin gia my tnh
vi bn ngoi.
Lin kt gia cc h thng : lin kt cc thnh phn
ca my tnh li vi nhau.
CC TRNH NG
DNG
H IU HNH
Nh Tk OS
PHN CNG MY TNH
M hnh c bn
X L
TRUNG TM
Cc thit b Cc thit b
nhp xut
B NH
CHNH
S cu trc my tnh
Peripherals Computer
Central Main
Processing Memory
Unit
Computer
Systems
Interconnection
Input
Output
Communication
lines
S cu trc CPU
CPU
Computer Arithmetic
Registers and
I/O Login Unit
System CPU
Bus
Internal CPU
Memory Interconnection
Control
Unit
Data
Control
Movement
Mechanism
Apparatus
Data
Processing
Facility
My bn:
l loi my thng dng nht hin nay.
bao gm my tnh c nhn (PC: Persional Computer)
v trm (Workstation Computer).
gi mua 100$ n 10.000$
My ch
l my phc v(server)
dng trong mng theo m hnh Clent/Server
c tc , hiu nng, b nh v tin cy cao
gi vi chc nghn n vi chc triu
GV: inh ng Lng Cu trc My tnh 19
1.2 Phn loi my tnh
My tnh nhng
c t trong nhiu thit b khc nhau iu khin
thit b lm vic
c thit k chuyn dng
v d: in thoi di ng, b iu khin cc thit gia
nh, Router nh tuyn,
Main
Input Memory
Output
Equipment
H thng my tnh
M hnh c bn ca my tnh.
Cc m hnh my tnh hin nay c thit k da trn
kin trc Von Neumann.
Cc c im kin trc ca Von Neumann:
D liu v chng trnh cha trong b nh c ghi.
B nh c nh a ch cho cc ngn nh khng ph
thuc vo ni dung ca chng.
My tnh thc hin lnh mt cch tun t.
y l b nh bn dn c tc nhanh v chng c
t m gia CPU v b nh chnh nhm tng tc truy
xut ca CPU ti b nh chnh.
Dung lng nh hn rt nhiu b nh chnh
Tc nhanh hn rt nhiu ln
Ngay nay Cache c tch hp vo trong b vi x l
v n trong sut vi ngi s dng.
B nh Cache thng thng c chia ra thnh 2 mc.
Cache c th c hoc khng
Chc nng v c im
Lu tr ti nguyn phn mm My tnh.
c kt ni vi h thng nh thit b vo ra.
Dung lng rt ln (vi trm GB)
Tc chm
Cc loi b nh ngoi
B nh t: a cng, a mm,
B nh quang: CD, VCD, DVD,
B nh bn dn: flash Disk, memory Card, pen
Disk,
GV: inh ng Lng Cu trc My tnh 38
H thng vo ra (Input/Output System)
Cu trc vo ra c bn
Begin
Nhn lnh
End
GV: inh ng Lng Cu trc My tnh 44
1. Thc hin chng trnh
0001: loader
0010: store
0101: add
Nhn lnh
N Y Chng trnh
Ngt? con phc v ngt
X l tn hiu ngt
Cm ngt: B x l b qua cc ngt tip theo trong khi
ang x l ngt.
Cc ngt vn ang i v c kim tra sau khi ngt
u tin c thc hin xong
Cc ngt c thc hin tun t nu cng th t u
tin.
Cc ngt trong my tnh my tnh c nh ngha
mc u tin khc nhau.
Ngt c mc u tin thp c th b ngt bi ngt c u
tin cao hn. V vy c th xy ra tnh trng ngt lng
nhau
GV: inh ng Lng Cu trc My tnh 54
3. Hot ng vo ra
Module
I/O
A CH A CH
BUS a ch :
Chc nng: dng vn chuyn a ch t CPU n
cc Module nh hay cc Module vo ra, nhm xc
nh ngn nh hay cng vo ra no cn truy xut trao i
thng tin. (y l BUS mt chiu).
rng ca BUS a ch (A0,A1,, An-1)
Cho bit kh nng qun l cc i s cc ngn nh. Nu
s dng rng bus a ch n ng th dung lng cc
i ca b nh c th qun l l 2n ngn nh hay tng
ng vi 2n byte nh (nu mi ngn nh 1 byte)
V d: Bus a ch ca mt s b VXL l
8088/8086 n=20 220(1MB)
80286 n=24 224(16MB)
80386Pentium n=32 232(4GB)
Pentium II, III,IV n=36 236(64GB)
BUS d liu:
Chc nng: vn chuyn lnh t b nh -> CPU, vn
chuyn d liu gia CPU, b nh v cng vo ra.
rng ca Bus d liu (D0,D1,.Dm-1)
Cho bit s byte c kh nng trao i ng thi
m=8,16,32,64,128 bit.
V d:
8088 -> m=8
8086 -> m=16
80386 -> m=32
Pentium -> m=64
GV: inh ng Lng Cu trc My tnh 62
2.3 Lin kt h thng
BUS iu khin:
Tp hp cc tn hiu iu khin gm c
Cc tn hiu pht ra t CPU iu khin Module nh
v Module vo ra.
Cc tn hiu t Module nh, Module vo ra gi n
CPU yu cu.
Ngoi ra cn l BUS cung cp ngun tn hiu xung
nhp (clock) vi cc BUS ng b.
Mt s tn hiu in hnh
B VXL
BUS b VXL
Cu ni
BUS
BUS b nh chnh
Cu ni
BUS
BUS vo/ra tc
chm
BUS ISA
Khe cm ISA
a mm
Super LPT
Bn phm Chut COM1
I/O COM2
ROM
GV: inh ng Lng Cu trc My tnh 67
Cu trc Pentium 4
Intel Pemtium 4
Processor
4.2 or 3.2 GB/s
RDRAM
Dual
AGP 4X
>1
GB/s
MCH chanel
4.0 GB/s
RDRAM
RDRAM
RDRAM
Inter Hub Architecture
ATA 100MB/s
2 IDE 6 Channel
ICH2 Audio
PCI
133MB/s
Flash BIOS
3.1 Cc h m c bn
3.2 M ho v lu tr trong my tnh
3.3 Biu din s nguyn
3.4 S hc nh phn
3.5 Biu din s du chm ng
3.6 Biu din k t
V d: 123,45
Phn nguyn : 123 : 10 = 12 d 3
12 : 10 = 1 d 2 123
1 : 10 = 0 d 1
=123,45
Phn phn : 0,45*10 = 4,5 45
0,5 *10 = 5
H nh phn(Binary)
B k t c s gm 2 s: 0,1
Dng tng qut: an-1an-2an-3a1a0,a-1 a-2a-m
n 1
A= i
a * 2 i
(ai = 0,1)
i= m
V d: 11011,0112 = 24+23+21+20+2-2+2-3 =27,375
Thp lc phn (hexadecimal)
B k t c s: 09,AF
Dng tng qut: an-1an-2an-3a1a0,a-1 a-2a-m
n 1
A= i
a * 16 i
(ai = 0..9, A..F )
V d: 89ABi =H=m 1000 1001 1010 1011B.
B cm B chuyn
bin tn i tng t
T/h vl hiu => s
(Sensor) (ADC)
My tnh
B chuyn
T/h vl B ti to i s=>
tn hiu tng t
(ADC
Hnh nh
GV: inh ng Lng Cu trc My tnh 77
Th t lu tr cc byte d liu MT
V d: lu tr mt t 32bit
0001 1010 0010 1011 0011 1100 0100 1101B
1 A 2 B 3 C 4 DH
Biu din trong ngn nh theo 2 cch
300 4D 300 1A
301 3C 301 2B
302 2B 302 3C
303 1A 303 4D
Little Endian Big Endian
GV: inh ng Lng Cu trc My tnh 79
Th t lu tr cc byte d liu MT
Lu tr ca cc b vi x l in hnh
Loi my Intel: 80x86, Petium -> little endian
Motorola 680x0 v cc b x l RISC -> big endian
Power PC & Itanium: tch hp c hai cch trn
S b mt v s b hai
N: Cho mt s nh phn N c biu din bi n bit. Ta
c
S b mt ca N bng (2n-1)-N
S b hai ca N bng 2n-N
V d: Cho s N = 0001 00012 c biu din bi n=8bit.
Xc nh s b 1 v b 2 ca N.
Ap dng cng thc 1111 1111 (2n-1)
0001 0001 N
s b mt ca N 1110 1110
Nhn xt: s b mt ca mt s N c xc nh
bng cch o cc bit trong N
Ap dng cng thc 1 0000 0000 (2n)
0001 0001 N
s b hai ca N 1110 1111
Nhn xt: s b hai ca mt s N c xc nh
bng cch ly s b mt ca N cng thm 1
S b 2 ca N =(s b 1 ca N)+1
B rng ca
trng (bit)
S 1 1 1
E 8 11 15
M 23 52 111
Tng cng 32 64 128
E cc i 255 2047 32767
E cc tiu 0 0 0
dch 127 1023 16383
S E M
e
S=1 phn nh tr l m
S=0 phn nh tr l dng
E: gi tr E nm trong 8 bit, l s m c dch chuyn
i 127
M: phn nh tr, gi tr nm trong 23 bit
Ta c s 2345,125 trong h thp phn. Hy biu din
chng di dng chun IEEE 32bit trong my tnh
GV: inh ng Lng Cu trc My tnh 94
3.4 Biu din s du chm ng
Mt s quy c
Nu e =255 v M<>0 -> khng phi l s
Nu e =255 v M=0 -> Gi tr m hoc dng v cng
Nu e =0 v M=0 -> gi tr bng 0
Di biu din: 2-127 n 2+127 hay tng ng 10-38 n
10+38
-2+127 -2-127 2-127 2+127
Overflow Underflow Overflow
B x l trung tm
4.1 Cu trc ca CPU
4.2 Tp lnh (Instruction File)
4.3 Hot ng ca CPU
4.4 Kin trc Intel
CPU
Register
ALU
Control
Unit
System bus
Kt qu
T.h iu khin
ALU
Thanh ghi c
GV: inh ng Lng Cu trc My tnh 111
c. n v iu khin
Chc nng:
Nhn lnh t b nh a vo thanh ghi lnh IP.
Tng ni dung thanh ghi PC mi khi nhn lnh song
Gii m lnh v xc nh thao tc m lnh yu cu
Pht ra tn hiu iu khin thc thi lnh.
Nhn cc tn hiu yu cu t BUS h thng v gii
quyt p ng yu cu .
M hnh kt ni n v iu khin
Cc c
T. h iu khin
Control bn trong CPU
Unit
Clock
Chc nng
Thc cht l vng nh c CPU nhn bit qua tn
thanh ghi v c tc truy xut cc nhanh.
Cha thng tin tm thi phc v cho hot ng thi
im hin ti ca CPU
S lng thanh ghi tu thuc vo b vi x l c th ->
tng hiu nng CPU
Thanh ghi chia 2 loi: Loi lp trnh c v loi
khng lp trnh c
Cc kiu thao tc
Thao tc chuyn d liu
Thao tc x l s hc v logic
Thao tc vo ra d liu qua cng
Thao tc iu khin r nhnh
Thao tc iu khin h thng
Thao tc x l s du chm ng
Thao tc chuyn dng khc: x l nh, m thanh, ting
ni,
Tp thanh ghi
OPCODE Thanh ghi
Ton hng
B nh
OPCODE a ch
Ton hng
B nh
OPCODE a ch a ch
Ton hng
B nh
ADD const
B nh my tnh
5.1 Tng quan b nh trong My tnh
5.2 B nh bn dn
5.3 B nh m nhanh (Cache)
5.4 B nh ngoi (b nh ph)
5.5 H thng nh trn my PC hin nay
Kiu b nh vt l:
B nh bn dn
B nh t
B nh quang
Cc c tnh vt l:
Kh bin/khng kh bin
Xo c/khng xo c
Tc
Registers
CPU Cache
Central Memory
Disk Cache
Peripheral
memories
Disks
CD/ROM
Archival Stores
Kch thc
B nh B nh trong
register
Tp
thanh ghi
B nh
Cache L1
B nh
Cache
chnh
B nh
mng
L2
2k t nh
(n bit t nh)
n ng d liu ra
GV: inh ng Lng Cu trc My tnh 141
5.2 B nh bn dn
Cc kiu ROM:
ROM mt n, PROM: Programmable ROM, EPROM:
Erasable PROM, EEPROM Electrically EPROM,
Flash Memory ( B nh cc nhanh): Ghi theo khi,
xo bng in.
k ng a ch
2k t nh
Read
Write (n bit t nh)
A0..An-1
Chip nh D0..Dm-1
2nx m bit
cs
WE OE
Cc tn hiu ca chip nh
Cc ng a ch: A0An-1 xc nh 2n ngn nh.
Cc ng d liu: D0Dm-1 di t nh (m bit)
=>dung lng chip nh = 2n x m bit
Cc tn hiu iu khin
o Tn hiu chn chip hot ng: CS (Chip Select)
o Tn hiu iu khin c hoc ghi (WE: Write
Enable; OE: Output Enable)
o Thng cc tn hiu iu khin tch cc vi mc 0
A0A11
Chip nh Chip nh
212 x 4 bit 212x 4 bit
D0D3
D 4D7
cs cs
WE OE WE OE
cs
WE
OE
A12 cs
A y0 WE OE
D0D7
B gii m
1->2
cs
G y1 Chip nh
212 x 8 bit
G A y1 y0
0 0 0 1
cs
0 1 1 0 WE OE
1 x
WE OE
Dliu ra
m bit B nh m bit
B hiu
chnh v a
d liu ra
B to m
M bit k bit
B to m
k bit Tbo li
k bit
B so
k bit snh
V d:
Xu gc: 1101011011 M(x)=x9+x8+x6+x4+x3+x+1(m=9)
a thc sinh G(x) = x4+x+1 10011 (r=4)
Xu gc: 11010110110000 x4M(x)
Chia mod2 11010110110000 10011
1100001010 -> thng
Nguyn tc:
Cache c tc truy xut nhanh hn rt nhiu b nh
chnh
Cache c t gia CPU v b nh chnh nhm tng
tc trao i thng tin gia CPU v b nh chnh.
Cache thng c t trong chip vi x l
Thao tc ca Cache
CPU yu cu ly ni dung ca mt ngn nh bng
vic a ra mt a ch xc nh nh.
CPU kim tra xem c ni dung cn tm trong Cache
Nu c: CPU nhn d liu t b nh Cache
Nu khng c: B iu khin Cache c Block nh
cha d liu CPU cn vo Cache.
Tip chuyn d liu t Cache n CPU
S thao tc cache, b nh chnh v CPU
a ch RA t CPU
hit
a BLOCK vo mt Line
Chuyn t ng RA trong Cache
ti CPU
Done Chuyn t a ch RA
ti CPU
GV: inh ng Lng Cu trc My tnh 167
5.4 B nh m nhanh
B nh chnh
B nh Cache
Block 1
Tag Line 1
Line 2 Block 2
CPU Line 3
Block 3
Block 4
Line C
Block M-2
Block M-1
Block M
T chc Cache
Gi s b nh chnh gm c 2n t nh c nh
a ch ( mi t nh c a ch duy nht rng n bit)
B nh chnh chia thnh M khi, mi khi c K t nh
M=2n/K
B nh Cache c C khe mi khe c K t nh.(C<<M)
Ti mt thi im lun c mt tp con cc khi nh
thng tr trong cache.
Nu mt t s c c th khi cha t s c
chuyn vo trong cache.
Cc kiu b nh ngoi
a t
a quang
B nh Flash
RAID
Xut x
RAID l cm t vit tt nhm t Redundant Array of
Inexpensive (Independent) Disks
Thut ng RAID c a ra trong mt bi bo ca
mt nhm cc nh nghin cu ti i hc tng hp
California, Hoa K.
RAID c xut nhm xa b khong trng ln tc
CPU v cc a in c tng i chm.
Hiu sut thi hnh vt tri so vi khi dng mt a
n ln t tin (SLED: Single Large Expensive Disk)
GV: inh ng Lng Cu trc My tnh 191
GiI THIU TNG QUAN V RAID
Khi nim
RAID: l cu trc a a vt l to nn mt a logic
c kch thc ln, tin cy v kh nng vn hnh cao
hn.
Mc ch
Nng cao hiu sut vn hnh ca ton b h thng.
Kh nng lm vic song song cc a.
An ton d liu tn dng tnh d tha d liu nhm ci
thin tin cy a.
Cung cp b nh ln
GV: inh ng Lng Cu trc My tnh 192
GiI THIU TNG QUAN V RAID
c im chng ca RAID
RAID l tp hp cc a vt l c nhn t h iu
hnh nh a logic n.
D liu c phn b trn mng cc a vt l. S
dng k thut Striping. (Striping l k thut phn chia
d liu trn hai hay nhiu a lm tng kh nng lm
vic song song h thng)
Dung lng a d tha c s dng lu tr thng
tin chn l nhm m bo kh nng phc hi d liu
trong trng hp c h hng v a.
GV: inh ng Lng Cu trc My tnh 193
GiI THIU TNG QUAN V RAID
C 6 mc chnh ca RAID
RAID 0
RAID 1
RAID 2
RAID 3
RAID 4
RAID 5
T/h iu khin
Thanh ghi
trng thi/iu khin
Cng
Cc ng /c ni
ghp
Cc ng /k Khi Logic iu khin vo/ra
c trng thi
sn sng
Module I/O N
sn sng?
Y
Trao i d liu
vi Module I/O
B m dl
Cc ng dl Thanh ghi dl
Cc ng /c Thanh ghi /c
Y/c Bus /K c
Chuyn nhng
Khi logic/ K /k ghi
Bus Y/c DMA
Ngt Chp nhn
T/h c/ghi DMA
BUS A CH
BUS D LIU
CPU
Thit b B nh
I/O
DMAC
YU CU YU CU
HOLD
HLDA
B x l vo ra
Vic iu khin vo ra c s dng bi mt b iu
khin vo ra chuyn dng.
B x l vo ra hot ng theo chng trnh ring
ca n.
Chng trnh ca b x l vo ra c th nm trong b
nh chnh hoc b nh ring.
Hot ng theo kin trc a x l