with sampling rates up to 100 kHz.

The CS5396 employs a seventhorder,

tri-level deltasigma modulator
and a digital filter, which makes
an external anti-aliasing filter unnecessary.
The differential architecture
produces exceptionally good noise
rejection: the maximum signal/noise
ratio of the IC is 105 dB and the
dynamic range is no less than
120 dB! We have intentionally chosen
the CS5396 for this design,
instead of the closely related CS5397,
since the former type has a linearphase
filter that is optimised for
audio applications. It has a passband
ripple of only 0.005 dB and a
stopband rejection of >117 dB.
On the output side, we also find a
pin-compatible successor to the previously
used IC. Here the CS8402
has given way to the brand new
CS8404A, which Crystal designates
as a 96 kHz digital audio transmitter.
This IC is especially intended to
be used for coding and transferring
audio data according to one of the
well known interface standards
(AES/EBU, IEC958, S/PDIF or EIAJ
CP-340). Inside the CS8404A, the
digital audio data are multiplexed
and encoded before being sent to
the output. In addition to the S/PDIF
output, which is electrically isolated
by a transformer, the circuit also has
an optical output.
Input section
The input stage of the converter has
been intentionally simplified in comparison
to the old 20-bit design,
with the result that it can process
only asymmetric signals. This means
that it is now possible to place Cinch
sockets on the printed circuit board,
which reduces the likelihood of interference
problems.
Now lets look at Figure 1, which
shows the complete schematic diagram
of the Audio ADC 2000. For
each channel, the input signal is first
DC decoupled, since the converter
has an asymmetric power supply
and each input stage thus has an
input offset. VCOM is used to set the
input stage to the proper voltage. For
this purpose, VCOM is supplied to
the opamps by separate decoupling
networks (R4/C4/C5 and
R10/C10/C11).
The CS5396 has one symmetric input
AUDIO
3/2001 Elektor Electronics 37
Measured results
A few measurements have been made in the digital domain using a special measurement
system from Crystal (CDBCapture+ board). In such cases, the signal from the
optical output
has been sampled and further processed.
The first figure, Figure A, shows a
FFT analysis of 16,384 samples taken
from the left channel with the converter
driven to just about full scale.
The THD+noise is here more than
104 dB down. Measurements on the
right channel show similar results, with
the THD+noise lying below 105 dB.
Figure B shows a FFT of a 20-kHz
signal at full drive. The only harmonic
that can be seen is a second harmonic
at 114 dB, and there are also a few
interference products (probably
crosstalk from the digital part of the
converter), but these lie below
120 dB! The right channel was clean,
with only a second harmonic at
123 dB.
Figure C shows an FFT of the
crosstalk from the right channel to the
left channel for a 20-kHz signal with
full drive. The channel separation here
is greater than 102 dB. In the other
direction (from left to right), this is
96 dB, but in the latter case only the
20-kHz component is visible.
Finally, Figure D presents a simple
statistical measurement in the form of
a histogram showing the distribution
of the output values with the input
shorted. This is a normal distribution
that shows a regular Gaussian shape.
0
-200
-180
-160
-140
-120
-100
-80
-60
-40
-20
0 5000 10000 15000 20000 25000 30000 35000 40000 48000
FREQUENCY DOMAIN
Frequency
Magnitude
010017 - A
0
-200
-180
-160
-140
-120
-100
-80
-60
-40
-20
0 5000 10000 15000 20000 25000 30000 35000 40000 48000
Frequency
Magnitude
FREQUENCY DOMAIN
010017 - B
0
-200
-180
-160
-140
-120
-100
-80
-60
-40
-20
0 5000 10000 15000 20000 25000 30000 35000 40000 48000
Frequency
Magnitude
FREQUENCY DOMAIN
010017 - C
288
0
16
32
48
64
80
96
112
128
144
160
176
192
208
224
240
256
272
-112 -80 -60 -40 -20 0 20 40 60 80 106
HISTOGRAM
Bin
Magnitude
010017 - D
A
B
C
D
for each channel. In order to allow asymmetric
signals to be connected, AINL and AINR
are provided with input signals via two
inverters (IC2 and IC4). A pleasant side effect
of this is that the input is thus made somewhat
more sensitive (700 mVrms full
scale).
Each of the input capacitors is made
up of three 3.3F MKT capacitors
connected in parallel. They combine
with the 10-k? input impedances
(R2 and R8) to form high-pass filters
with a corner frequency of 1.6 Hz. In
order to allow an (external) symmetrical
input stage to be connected, a
AUDIO
38 Elektor Electronics 3/2001
Figure 1. The actual converter consists primarily of a single IC, the CS5396-KS.
The well-known CS8404A is used for the S/PDIF output. TRNPT/FC1 CS8404A CBL/SBC
C1/FC0 EM1/C8 EM0/C9 C9/C15 SDATA FSYNC C6/C2 C7/C3 C/SBF IC6 TXP TXN MCK RST PRO
SCK 1918 16201724131412 151011 M0 21 M1 22 M2 23
8
7
5
2
3
4
1
6
V 9
U
R13
7 ?4
C27
100n
SMD
C28
10n
SMD
C29
100n
SMD
C25
10n
SMD
C26
100n
SMD
L1
10H
L2
10H
5VA
5V
C6
6n8
C22
100n
C24
100n
C12
6n8
SMD
SMD
C21
100 25V
C23
100 25V
OPA
IC1
2
3
6
7
4
1
5
OPA
IC2
3
2
6
7
4
1
5
C13
100n
C14
100n
12V
C15
100n
C16
100n
12V
C1
33
C2
33
C3
33
R3
10k0
R6
39?2
R5
39?2
R2
10k0
R4
4k7
C5
100n
C4
470
16V
K1
R1
1M
K3
OPA
IC3
2
3
6
7
4
1
5
OPA
IC4
3
2
6
7
4
1
5
C17
100n
C18
100n
12V
C19
100n
C20
100n
12V
C7
33
C8
33
C9
33
R9
10k0
R8
10k0
R10
4k7
C11
100n
C10
470
16V
K2
R7
1M
R12
K4
39?2
R11
39?2
CS5396-KS
CDIN/DFS
CCLK/SM
CS/PDN
SDATA2
SDATA1
AINL+
AGND0
AGND1
AGND2
AINL
TST01
TST02
AINR+
AINR
DACTL
ADCTL
MCLKA
MCLKD
IC5
LGND
DGND
VREF
VCOM
LRCK
SCLK
CAL
VL
23
17
28 25 22 12
VD
11
VA
24
19
27
26
21
18
10
15
16
13
14
20
3
4
5
1
8
2
9
6
7
D2 D1
D4 D3
5VA
D6 D5
D8 D7
5VA
L+
L
R+
R
627AP
627AP
627AP
627AP
1 2
3 4
5 6
7 8
9 10
K5
1 2
3 4
5 6
7 8
9 10
K6
IC9a
3 C
4
S 2 D
1
R 5
6
IC9b
11 C
10
S 12 D
13
R 9
8
JP1
5V
5V 5V'
1 2 1
IC10a
R14
120k
R15
100?
S2
CAL
C30
10
63V
D9
BAT85
3
4
1
5V
IC10b
L4
47H S1
8x 10k 1
42536897
R20
5V'
C34
100n
SMD
C33
47
25V
TOTX173
IC7
1
3
2
4
Tr1
20 : 2
R17
8k2
R16
7 ?4
C35
100n
R18
? 270
C36
47n
R19
75?
K7
L3
47H
5V
C32
100n
C31
1 63V
IC8
OSC
4
5
1
8
5V'
IC9
14
7
IC10
14
7
C37
100n
C38
100n
13 12 1
IC10f
11 10 1
IC10e
9 8 1
IC10d
5 6 1
IC10c
5V
C44
470
16V
C42
10
63V
C40
10
63V
C46
470
16V
C50
47
25V
C48
470
16V
C43
100n
C41
100n
C39
100n
C45
100n
C49
100n
C47
100n
L5
47H
R21
10?
D10
5V6
1W3
D11
5V6
1W3
12V IC11
7805 5V
5VA
010017 - 11
L
R
12V
12V
12V
12V
/ 2
/ 1
12V
12V 5V
S/PDIF
4x BAT85
4x BAT85
+12V
12V 12V
+5V
IC9 = 74HC74
IC10 = 74HC14 24.567MHz
20
2 010017 - 11a
Tr1
three-way pin header is provided on
the circuit board for each channel (K3
and K4). If this option is used, the
input stages (IC1IC4 and the associated
components) should not be
fitted. The pin headers can also be
used as test points.
Converter
As shown in the schematic diagram,
the A/D converter is liberally provided
with decoupling. SMDs are
used in part for this purpose, for the
supply voltage as well as for the reference
voltage and VCOM. Incidentally,
the CS5396 is also an SMD (28-
pin SOIC).
The converter is used in the standalone
mode, with the sampling rate
determined by the master clock. At
96 kHz, 64 times oversampling must
be used, so a master clock frequency
of 24.576 MHz is required.
Power Down (PDN) is not used, so
this pin is tied to ground. DFS determines
the output format; a High level
here selects the I2S-compatible
mode. S/M is Low to select Master
mode and thus ensure that the digital
outputs are all derived from the master
clock.
The tri-level deltasigma modulator
AUDIO
3/2001 Elektor Electronics 39
2x 15V
Tr1
4VA5
Tr2
9V
3VA3
B1
B80C1500
B2
B80C1500
C11
C12 C10
C9