Student Final Award List PrintId :d4f16ab42b4a211da1be

Subject Code :System Verilog for Design & Verification (ECT-664 )

Program Code : EC301 Sem. : 2 Section: 16MECVLSI

UID Hourly Hourly Hourly Element Element Element Element Attendan Mass Total Max Total Scaled
Test Test 2 Test 3 1(quiz) 2 3 4 ce Marks Bunk Marks Marks Marks
Obtd
Max. Marks 24 24 24 12 9 12 9 6 -9 x No. 40
of M.B.)
16MEC1014 23 23 24 4 8 10 7.5 6 120 105.5 35.17

16MEC1015 20 19 20 6 7 9 7 6 120 94 31.33

16MEC1018 22 24 23 5 8 9 8 6 120 105 35.01

16MEC1020 22 24 24 6 8 10 7.5 6 120 107.5 35.83

16MEC1025 11 12 11 7 7 8 6 0 120 62 20.67

16MEC1026 24 23 24 11 8 10 7 6 120 113 37.67

16MEC1031 21 24 23 12 8 11 7 6 120 112 37.34

Generated By........................................................... Approved Signature............................................... Received By ....................................................

(With Emp. code) (With Emp. Code) (With Emp. code)

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