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Verilog 2 - Design Examples: Courtesy of Arvind L03-1
Verilog 2 - Design Examples: Courtesy of Arvind L03-1
automatic tools to
synthesize a low-level
gate-level model
Gate Level
+1 +1
always @( posedge clk )
A_out <= A_in;
always @(
begin
posedge clk ) +1 +1
A_out = A_in;
B_out = B_in;
C_out = C_in; Will this synthesize?
end
Yes
assign B_in = A_out + 1;
assign C_in = B_out + 1; Is it correct?
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Verilog Design Examples
! Greatest Common Divisor
! Unpipelined SMIPSv1 processor
L03-14
What does the RTL
GCD in C implementation need?
L03-15
Step 1: Design an
appropriate port interface
input_available result_rdy
idle result_taken
operand_A result_data
operand_B
clk reset
designed to
be either busy
or waiting for
A A B B input or
sel en sel en B=0 A<B waiting for
output to be
picked up
zero? lt A = inA; B = inB;
A while ( !done )
sub begin
if ( A < B )
swap = A;
B
A = B;
B = swap;
else if (B != 0)
A = A - B;
else
done = 1;
End
Courtesy of Arvind Y = A; L03-18
Datapath module interface
module GCDdatapath#( parameter W = 16 )
( input clk,
A A B B
sel en sel en B=0 A<B
// Data signals
input [W-1:0] operand_A,
input [W-1:0] operand_B, zero? lt
output [W-1:0] result_data, A
sub
vcMux3#(W) A_mux
( .in0 (operand_A),
zero? lt
.in1 (B),
A
.in2 (sub_out), sub
.sel (A_sel),
.out (A_out) ); B
wire [W-1:0] A;
vcEDFF_pf#(W) A_pf
( .clk (clk),
.en_p (A_en),
.d_p (A_out),
.q_np (A) );
Courtesy of Arvind L03-20
Connect the datapath modules ...
input_availble
( Done = 1 )
A A B B
sel en sel en B=0 A<B
C RTL
Model Model
Identical?
localparam cs_sz = 8;
reg [cs_sz-1:0] cs; casez performs simple pattern
matching and can be very useful
always @(*)
begin
when implementing decoders
cs = {cs_sz{1'b0}};
casez ( imemresp_data )
// op0 mux op1 mux wb mux rfile mreq mreq tohost
// br type sel sel sel wen r/w val en
`ADDIU: cs ={br_pc4, op0_sx, op1_rd0, wmx_alu, 1'b1, mreq_x, 1'b0, 1'b0};
`BNE : cs ={br_neq, op0_sx2, op1_pc4, wmx_x, 1'b0, mreq_x, 1'b0, 1'b0};
`LW : cs ={br_pc4, op0_sx, op1_rd0, wmx_mem, 1'b1, mreq_r, 1'b1, 1'b0};
`SW : cs ={br_pc4, op0_sx, op1_rd0, wmx_x, 1'b0, mreq_w, 1'b1, 1'b0};
`MTC0 : cs ={br_pc4, op0_x, op1_x, wmx_x, 1'b0, mreq_x, 1'b0, 1'b1};
endcase
end