Data Processing Instructions

EC271 Microprocessors
Arulalan Rajan
Dept. of E&C Engg, NITK Surathkal
Lecture - 16, 1st February 2017
Data Processing & Control Flow Instructions

Arithmetic Instructions
#TWNCNCP4CLCP&GRVQH'%'PII0+6-5WTCVJMCN
ADD r0, r1, r2
ADD r0, r1, r2 5KTT9GMPQYKV2NGCUG
ADC r0, r1, r2
ADC r0, r1, r2 r0:= r1 + r2 + C
ADC r0, r1, r2 r0:= r1 + r2 + C
SUB r0, r1, r2
ADC r0, r1, r2 r0:= r1 + r2 + C
SUB r0, r1, r2 0QVCICKP9GMPQYVJKUVQQ
ADC r0, r1, r2 r0:= r1 + r2 + C
SBC r0, r1, r2
ADC r0, r1, r2 r0:= r1 + r2 + C
SBC r0, r1, r2 r0:= r1 - r2 + C - 1
ADC r0, r1, r2 r0:= r1 + r2 + C
SBC r0, r1, r2 r0:= r1 - r2 + C - 1
RSB r0, r1, r2
ADC r0, r1, r2 r0:= r1 + r2 + C
SBC r0, r1, r2 r0:= r1 - r2 + C - 1
RSB r0, r1, r2 r0:= r2 - r1
ADC r0, r1, r2 r0:= r1 + r2 + C
SBC r0, r1, r2 r0:= r1 - r2 + C - 1
RSB r0, r1, r2 r0:= r2 - r1
RSC r0, r1, r2
ADC r0, r1, r2 r0:= r1 + r2 + C
SBC r0, r1, r2 r0:= r1 - r2 + C - 1
RSB r0, r1, r2 r0:= r2 - r1
RSC r0, r1, r2 r0:= r2 - r1 + C - 1
ADC r0, r1, r2 r0:= r1 + r2 + C
SBC r0, r1, r2 r0:= r1 - r2 + C - 1
RSB r0, r1, r2 r0:= r2 - r1
RSC r0, r1, r2 r0:= r2 - r1 + C - 1
C : Current value of Carry bit in CPSR

Logical Operations
Logical Operations
AND r0, r1, r2
ORR r0, r1, r2
Logical Operations
AND r0, r1, r2
ORR r0, r1, r2 9J[5KTT9J[!
Logical Operations
AND r0, r1, r2
EOR r0, r1, r2
Logical Operations
AND r0, r1, r2
EOR r0, r1, r2 r0:= r1 xor r2
Logical Operations
AND r0, r1, r2
BIC r0, r1, r2
Logical Operations
AND r0, r1, r2
BIC r0, r1, r2 r0:= r1 and NOT r2
Logical Operations
AND r0, r1, r2
BIC: Bit Clear
Logical Operations
AND r0, r1, r2

Every 1 in R2 clears corresponding
BIC: Bit Clear
bit in R1
Logical Operations
AND r0, r1, r2

Every 1 in R2 clears corresponding
BIC: Bit Clear
bit in R1
#0&$+%CTGGSWKXCNGPVKPUVTWEVKQPU
Register Movement
Register Movement
MOV r0, r1 r0:= r1
Register Movement
MOV r0, r1 r0:= r1
MVN r0, r1 r0:=Not(r1)
Register Movement
MOV r0, r1 r0:= r1
/18/80CTGGSWKXCNGPVKPUVTWEVKQPU
Register Movement
MOV r0, r1 r0:= r1
/18/80CTGGSWKXCNGPVKPUVTWEVKQPU
--diag_warning 1645 assembler command-line option to check when
an instruction substitution occurs
Compare Instructions
CMP r0, Operand 2 r1 - Operand2
CMP r0, Operand 2 r1 - Operand2

CMN r0, Operand 2 r0 + Operand2
4GUWNVUCTGFKUECTFGF
4GIKUVGTUCTGPQVWRFCVGF
(NCIUWRFCVGF
0<%8
%/2%/0CTGGSWKXCNGPV
Bit Test Instructions
Bitwise AND on Rn and
TST{cond} Rn, Operand 2 Operand 2
(same as ANDS)
(same as ANDS)
Bitwise EXOR on Rn and
TEQ{cond} Rn, Operand 2 Operand 2
(same as EORS)
(same as ANDS)
(same as EORS)
4GUWNVUCTGFKUECTFGF
(same as ANDS)
(same as EORS)
4GUWNVUCTGFKUECTFGF
(same as ANDS)
(same as EORS)
4GUWNVUCTGFKUECTFGF
(NCIUWRFCVGF
0<
(same as ANDS)
(same as EORS)
4GUWNVUCTGFKUECTFGF
(NCIUWRFCVGF
0<
%HNCIOC[DGWRFCVGFFWTKPIECNEWNCVKQPQHQRGTCPF
(same as ANDS)
(same as EORS)
4GUWNVUCTGFKUECTFGF
(NCIUWRFCVGF
0<
6'30GHHGEVQP%8
(same as ANDS)
(same as EORS)
4GUWNVUCTGFKUECTFGF
(NCIUWRFCVGF
0<
6'30GHHGEVQP%8
6JGPYJCVKUVJGWUGQH6'3!!
Control Flow Instructions
Do not process data
Do not process data
Nor moves the data around
Do not process data
Processor executes instructions sequentially
Do not process data
Determines which instructions get executed next
Do not process data
Determines which instructions get executed next
Recall: All ARM instructions can be conditionally

executed
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Condition 1 0 1 L 24 bit singed word Offset
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 = Branch
1 = Branch
with Link
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 = Branch
1 = Branch
with Link
Uses Link Register, whenever a subroutine is executed and

getting back to original sequence of code is required
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 = Branch
1 = Branch
with Link

B{L}{<cond>} <target_address>
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 = Branch
1 = Branch
with Link

B{L}{<cond>} <target_address>
Range of branch Instructions: +/- 32MBytes

Data Processing Instructions

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Data Processing Instructions

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EC271 Microprocessors

Lecture - 16, 1st February 2017

Data Processing & Control Flow Instructions

ADC r0, r1, r2

ADC r0, r1, r2 r0:= r1 + r2 + C

ADC r0, r1, r2 r0:= r1 + r2 + C

SUB r0, r1, r2

ADC r0, r1, r2 r0:= r1 + r2 + C

SUB r0, r1, r2 0QVCICKP9GMPQYVJKUVQQ

ADC r0, r1, r2 r0:= r1 + r2 + C

SUB r0, r1, r2 0QVCICKP9GMPQYVJKUVQQ

SBC r0, r1, r2

ADC r0, r1, r2 r0:= r1 + r2 + C

SUB r0, r1, r2 0QVCICKP9GMPQYVJKUVQQ

SBC r0, r1, r2 r0:= r1 - r2 + C - 1

ADC r0, r1, r2 r0:= r1 + r2 + C

SUB r0, r1, r2 0QVCICKP9GMPQYVJKUVQQ

SBC r0, r1, r2 r0:= r1 - r2 + C - 1

RSB r0, r1, r2

ADC r0, r1, r2 r0:= r1 + r2 + C

SUB r0, r1, r2 0QVCICKP9GMPQYVJKUVQQ

SBC r0, r1, r2 r0:= r1 - r2 + C - 1

RSB r0, r1, r2 r0:= r2 - r1

ADC r0, r1, r2 r0:= r1 + r2 + C

SUB r0, r1, r2 0QVCICKP9GMPQYVJKUVQQ

SBC r0, r1, r2 r0:= r1 - r2 + C - 1

RSB r0, r1, r2 r0:= r2 - r1

RSC r0, r1, r2

ADC r0, r1, r2 r0:= r1 + r2 + C

SUB r0, r1, r2 0QVCICKP9GMPQYVJKUVQQ

SBC r0, r1, r2 r0:= r1 - r2 + C - 1

RSB r0, r1, r2 r0:= r2 - r1

RSC r0, r1, r2 r0:= r2 - r1 + C - 1

ADC r0, r1, r2 r0:= r1 + r2 + C

SUB r0, r1, r2 0QVCICKP9GMPQYVJKUVQQ

SBC r0, r1, r2 r0:= r1 - r2 + C - 1

RSB r0, r1, r2 r0:= r2 - r1

RSC r0, r1, r2 r0:= r2 - r1 + C - 1

C : Current value of Carry bit in CPSR

EOR r0, r1, r2

EOR r0, r1, r2 r0:= r1 xor r2

EOR r0, r1, r2 r0:= r1 xor r2

BIC r0, r1, r2

EOR r0, r1, r2 r0:= r1 xor r2

BIC r0, r1, r2 r0:= r1 and NOT r2

EOR r0, r1, r2 r0:= r1 xor r2

BIC r0, r1, r2 r0:= r1 and NOT r2

BIC: Bit Clear

EOR r0, r1, r2 r0:= r1 xor r2

BIC r0, r1, r2 r0:= r1 and NOT r2

EOR r0, r1, r2 r0:= r1 xor r2

BIC r0, r1, r2 r0:= r1 and NOT r2

MOV r0, r1 r0:= r1

MOV r0, r1 r0:= r1

MVN r0, r1 r0:=Not(r1)

MOV r0, r1 r0:= r1

MVN r0, r1 r0:=Not(r1)

MOV r0, r1 r0:= r1

MVN r0, r1 r0:=Not(r1)

CMP r0, Operand 2 r1 - Operand2

CMP r0, Operand 2 r1 - Operand2

Nor moves the data around

Nor moves the data around

Processor executes instructions sequentially