BACK ANNOTATION

Once the board design is completed, one can export information from the PCB design to the
schematic by performing a back annotation. Back annotation in PCB Editor is called feedback, For
an FPGA design back annotation is taking the delays (some time the pin numbers, too) from the
layout (after place&route phase) and entering them into the description (schematic or HDL-based),
this way allowing to do more realistic simulation. For discrete components design back annotation
is just updating the circuit from the pcb .

Before performing back annotation, one must rename the refdes because we placed the components
in different position, during soldring the identification of components mey create an uncertainity
due to random arrangment at different position.

(fig 1) for auto renaming

So to rename the refdes (select all the components on the board) go to Logic Auto rename
Refdes (fig 1). In that check all the fileds shown in below figures. (click on more to get setup ,
specify the direrctions as required, leave blank the top layer idenifier and bottom layer identifier)
select user default grid in grid specfication (fig 2). Press rename, thus renaming is done.

For export the logic of board layout to schematic, go to setup userpreference logic (in side
menu), select capture in schematic editor, press Apply OK.

(fig 2) auto rename dialog box

Select File Export - Logic (fig 3) . There in cadence select Design entry CIS, and sepecify the
board file (fig 4), also in other specify the board file location in comparision design and the
export directory.Click on Export Cadence(other) (figure 5).

(fig 3) (fig 4) (fig 5)

for exporting logic from allegro to capture

Open Capture select the .dsn file in project manager window, go to tools Back Annotate
(fig_6),specify the board file, type Allegro in netlist directory, and specify the Output file.(check
both the fields as shown in below figure) (fig 7 & fig 8), Press OK.

(fig 6) for back annitation

(fig 7) (fig 8)