Experimental PWM Method Validation of a 9-level
4.16 kV Series Connected H-bridge Grid Simulator
J. Leonard, J.C. Fox, R. Hadidi, B. Gislason
Duke Energy eGRID Center
Clemson University
N. Charleston, SC USA
Abstract— Controllable ac sources, sometimes referred to as
grid simulators, are becoming more common for grid integration
testing of inverters as new grid interactive inverter functions
develop. Due to the relatively niche application, high power grid
simulators are often made by repurposing commercial drives
with additional systems integration by the manufacturer or end
user including filters, transformers, and control features.
Simulation models, invaluable for pre-test simulations and future
retrofits to the drive, are not usually provided with the drive and
must therefore be developed by end users. Pulse-width
modulation details are often overlooked in this process, using
defaults within the simulation environment. Validating the digital
implementation of PWM, including sampling method, is
beneficial as it can have significant effects on control bandwidth
especially on multi-level and interleaved converters. The grid
simulator considered here utilizes 9-level series-connected H-
bridge topology. Experimental setup and results are shown for
two carrier frequencies, 600 Hz and 2 kHz, verifying an effective
phase shifted carrier each with double-edge sampling.
I. INTRODUCTION
Grid integration certification tests for distributed resources
(DRs) are becoming more involved as interconnection
requirements call for more grid event ride-through capability.
Recent test standards call for a simulated electric power system
(EPS) capable of frequency deviation of several Hz and fast
voltage events such as low voltage ride-through (LVRT) and
zero voltage ride-through (ZVRT) to test DRs [1-2]. These
requirements for a simulated EPS lean toward bidirectional
electronic AC sources, potentially interfaced to a digital real-
time simulator for Power Hardware-In-the-Loop (PHIL) [3-4].
High power amplifiers, above 1 MW, are likely made from
small, parallelized amplifiers [5] or larger repurposed industrial
converters [3][6-7]. In either case they likely rely on switch-
mode converter topologies for low losses at high power.
Developing a validated simulation model helps in pre-test
simulations to develop protection settings and test sequences.
However, models with sufficient detail for grid simulator
applications are rarely supplied by converter manufacturers
requiring end users to develop their own.
This paper focuses on experimental validation of the PWM
sampling method for a 9-level series-connected H-bridge
(SCHB) grid simulator. Previous work developed a Real-Time
Digital Simulator (RTDS) model of the converter for controller
hardware-in-the-loop testing [8] but additional experimental
validation of the PWM system was desired. Additionally, the
978-1-5090-0261-0/16/$31.00 ©2016 IEEE
M.H. McKinney
Department of Electrical Engineering
The Citadel
Charleston, SC USA
modularity of the converter has the potential for future
modification to other topologies which may require the
communication channel and PWM configuration be pushed to
the limit. Experimentally validating the PWM sampling
method and revising the simulation model aids testing of new
topologies in simulation prior to prototyping in hardware.
The discussion begins with the SCHB topology with phase
shifted PWM carriers followed by simulation modeling of the
expected PWM sampling method in PLECS and RTDS. The
RTDS model was used for Controller Hardware-In-the-Loop
testing prior to hardware testing on the amplifier using medium
voltage differential probes and a mixed signal oscilloscope to
time the communication channel to the final amplifier output.
Simulation results and oscilloscope captures from hardware
tests are presented verifying the expected PWM sampling
method.
II. PHASE SHIFTED CARRIER PWM FOR SCHB INVERTERS
The grid simulator consists of four 4.16 kV VersaBridge
power amplifier units (PAUs) from TECO Westinghouse
Motor Company (TWMC) [7]. Each PAU has two 9-level
series connected H-bridge (SCHB) inverters made up of four
series connected slices shown in Fig. 1a. Slices house a four-
winding isolation transformer and three power cubes, one for
each phase, with a nominal 1000 V dc link. Figure 1b shows
the circuit diagram for the PAU phase A output filter,
duplicated for phases B and C with respective phase labels.
The output filter includes two 120 µH balancing inductors to
improve current sharing between the two PAU inverters.
Finally, measurements at channel callouts in the filter diagram
are shown in Fig. 1c with traces pre and post filter for a 60 Hz
signal from the grid simulator controller.
The complete system uses an interface controller,
developed by Clemson, to send command references to the
TWMC control system, thoroughly described in [7-8].
Command reference packets are updated at 12 kHz and carry
three duty cycle values for the H-bridge output stage of the
PAU, bypassing the native motor drive controls to interface
directly with the PWM system. Each cube active front end is
controlled locally at the slice level and regulates the dc link
capacitor voltage to 1000 V dc nominally. This enables
bidirectional power flow for the PAU output required for
testing sources, such as PV inverters, or bidirectional power
flow such as energy storage systems.
 Slice 8 power derating. One detail left to be verified was the sampling
method within the PWM system in conjunction with the
Bridge A
Slice 7 C A8
Clemson interface controller. Figure 2 shows three graphs for
Bridge A
Slice 6 CB A
A7
600 Hz, 1500 Hz, and 2000 Hz PWM switching frequency
4160 V Bridge A
Slice 5 Input CB A
A6
carriers overlaid on 12 kHz synchronization for command
Bridge A Bridge B
Slice 4
4160AV
Input CB A
C A5 B8
packets. There are several possibilities for signal flow between
AB CA Bridge A Bridge B
Slice 3
4160AV
Input C
B A
CB A
A4 B7
the incoming command packets and the final IGBT gate pulses.
AB CA Bridge A Bridge B
4160AV
Slice 2 Input
B
CB A BC
CB A
A3 B6
The commanded duty cycle can pass directly to a comparator,
AB CA Bridge A Bridge B Bridge C
Slice 1 4160AV
Input
B C
CB A BC
CB A
C A2 B5 C8
similar to continuous sampling, or loaded into an intermediate
AB CA Bridge A Bridge B Bridge C
4160AV
Input
B C
A
C
B A
C
B A A1 B4 C7
B AB BC
AB CA
register. Since the PAU control system is based on National
CA Bridge B Bridge C
4160AV
4160 VInput
B C
CB A
C
B A
B3 C6
BC

A
Input
A B C
AB CABC

BC
CB A
C
B A
Bridge B Bridge C
B2 C5 N Instruments RIO controllers using FPGAs, both methods are
B C
AB
A
CA

BC CA B A
C
B A
Bridge B Bridge C
B1 C4 possible as opposed to a DSP with hardwired PWM
AB
B C B C
BC
C
B A
Bridge C
C3 subsystems. For comparison, documentation for the Texas
B
C
C
BC
C
B A
Bridge C
C2 Instruments C2000 DSP family refers to these intermediate
Bridge C N registers as shadow registers [10-11]. Figure 3 shows the
B A
C1
CA AB
assumed PWM system diagram for one inverter with twelve
BC
subsystems, one for each cube, which will be experimentally
verified. Designations for cube IGBTs are given in Fig. 4. The
TWMC controller receives new command packets at 12 kHz,
updating Index A, B, and C of Fig. 3. To generate firing pulses,
the original modulation index and a duplicate negated index are
compared with a triangle carrier, or counter since the control
system is digital. As shown in Fig. 3, all three cubes within a
slice use the same carrier phase for H-bridge PWM, phase
shifting only occurs between slices. The unknown is the
presence or absence of a sample and hold (S/H) block between
the incoming command packets, updated at 12 kHz, and the
comparator block and if it is present, at what instance is the
S/H triggered. There is also dead-time between Q1-Q2 and Q3-
Q4 IGBT turn-on to prevent shoot through but is not shown.
Possibilities for S/H triggering are discussed next.
A. Shadow Registers Disabled
The simplest PWM method is to remove the S/H block in
Fig. 3 and compare the most up-to-date modulation index with
the carrier to generate firing pulses. However, this has
unintended consequences for modulation indices that change
very fast, such as a low voltage ride-through sequence where
the magnitude can change from 1 to 0 and back to 1 per unit.
Without the S/H block it is possible that a fast-changing
modulation index will produce switching events faster than the
designed switching frequency. This is discussed further in the
simulation results section.
B. Single Edge Sampling on One Carrier
The remaining PWM systems discussed here have a S/H
block, creating a shadow register prior to the block that is
updated at 12 kHz but now the value compared with the carrier
Fig. 1: (top) TWMC PAU, two parallel 9-level inverters, three power cubes and is only loaded at certain times, TI refers to the value after the
one transformer per slice (middle) PAU output filter, one for each phase A,
B, C (bottom) oscilloscope capture on phase A filter for 2.4 kV rms l-n output.
S/H as the active register. Figure 2 has numbered labels on
groups of S/H events corresponding to possible S/H triggering
methods. The simplest is triggering the S/H when one carrier is
The VersaBridge specification indicated the PAU output at its peak or at a valley, for example (1) or (2) in Fig. 2 but not
stage uses a phase shifted PWM scheme, 45° separation both. For the other three carriers, there is still an issue of
between each slice, with a nominal 600 Hz switching possible unintended switching. This case is not like any of the
frequency for motor drive applications. This PWM method is TI PWM types.
well known [9] and has benefits of thermal balancing between C. Single Edge Sampling on Each Carrier
cubes over other schemes. The switching frequency for the This condition is very similar to the TI Type 0 PWM
output H-bridges is adjustable through a control system system where the active registers of each slice are loaded at the
parameter to improve output harmonics with a tradeoff of peak or valley of its own carrier. In the case of Fig. 2 this is (1)

Fig. 2: Plots for assumed PAU PWM with 12 kHz control packet timing as
vertical lines (top) 600 Hz carriers with possible comparator sample and hold
timing (middle) 1500 Hz carriers (bottom) 2000 Hz carriers.
and (3) combined in the case of peak, or (2) and (4) combined
in the case of valley. Unintended switching events are avoided
by triggering S/Hs separately for each carrier at the peak or
valley, meaning S/Hs within a slice trigger simultaneously
based on that slice carrier and other slices do the same.
Another benefit is controller bandwidth since the system output
is updated more frequently with regard to a change at the
modulation index compared to single edge sampling on one
carrier.
D. Double Edge Sampling on One Carrier
This case is similar to case B, where all S/H blocks are
triggered from one carrier, this time at the peak and valley of
one carrier. In Fig. 2 this would be S/H triggering at (1) and
(2). Again, this does not fall into any of the TI PWM types,
similar to case B. This configuration has more controller
updates to active registers than case B but less than case C.
E. Double Edge Sampling on Each Carrier
The final case for S/H triggering is similar to case C, where
S/H blocks within a slice have their own triggers, but here are
triggered on the peak and valley of individual carriers. In Fig. 2
this corresponds to all labeled points (1) – (4). This is similar to
TI Type 1 PWM where the active register can be updated with
a new value at the peak and valley of the carrier. During
discussions with TWMC this case seemed to be the most likely
due to the 12 kHz index update rate for control packets. If it
were the other PWM cases this update rate would be much
faster than necessary. This fast update rate also leaves room for
higher switching frequencies beyond the nominal 600 Hz.
Looking back at Fig. 2, the H-bridge PWM carrier frequency
Fig. 3: Diagram of PWM system for four PAU slices. Each three-phase index is
shared between all slices while each carrier is local to one slice.
Fig. 4: Power cube H-bridge output stage with switch designation.
can be increased to 1500 Hz while maintaining one control
packet per S/H trigger. This is due to four carriers with two
S/H events, Eq. 1, where is the switching frequency period.
Increasing the frequency beyond this critical frequency further
reduces voltage ripple but will yield two sequential S/H events
sampling the same control packet. The number of triggers per
period is specific to the 9-level topology with four carriers and
PWM method, single (four per period) or double edge (eight
per period) on each carrier. Control update rate here is specific
to this grid simulator design, Clemson’s grid simulator
controller interfaced with the TWMC controller, but other high
power grid simulators face the same issue of interfacing a
higher level controller command packet, or analog signal, to
the power stage controller.
12
= = 1500 (1)
8
III. SIMULATION MODELING
Two simulation packages, PLECS and RSCAD for RTDS,
were used to model the possible PWM systems. The latter was
used as part of a controller hardware-in-the-loop (CHIL)
pretest before hardware experiments with the PAU. Prior
development of the CHIL configuration is described in [8].
A. Implementing PWM Sampling Methods in PLECS
The PLECS simulation environment has a very straight
forward modulation blockset with built-in features for each
PWM sampling type. Simulation results are from a PLECS
model using the Symmetrical PWM block. Unfortunately the
default sampling method is Natural, most closely related to
continuous sampling, which can catch the uninitiated off guard
when the intended DSP target actually uses a sampled PWM
method. The next subsection discusses one drawback to this
type of PWM system. Changing to double edge sampling is as
easy as changing a drop-down list in the block parameters to
Regular (double edge). Sampling events aren't natively
available to plot via the block probe signals but alternative
implementations using triggered subsystems with direct
connection between an input and output port for S/H allow
further insight into timing of S/H triggers. This type of
triggered subsystem was used for the next subsection.
Fig. 5: PLECS simulation for a 600 Hz PWM carrier with a 600 Hz square
wave duty cycle of magnitude 0.5 and corresponding cube outputs for given
S/H triggering methods.
B. Effects of PWM Sampling for Fast Changing Duty Cycle
Section II briefly mentioned problems associated with
disabling or bypassing S/H blocks between shadow registers
and active registers, allowing any change in controller update
to immediately pass to the PWM comparator. Figure 5 shows
the possible PWM sampling methods for a fast-changing
modulation index, in this case a sign toggle, and its effect on
cube output. The top plot shows a 600 Hz carrier with two
indices, the positive is the modulation index and the negative is
the signal following the -1 gain block from the Fig. 3 PWM
diagram. The continuously sampled system does not maintain a
constant switching frequency which is likely an undesirable
design condition. Cube output with single edge sampling is
dependent on the timing of the duty cycle sign toggle and
whether sampling occurs at the peak or valley of the carrier.
The double edge sampled method maintains a constant
switching frequency for each IGBT and updates the active
register more often than single edge sampling.
C. Delay Differences in Single and Double Edge Sampling
Another observable difference between single and double
edge sampling is response to a duty cycle change. Figure 6
shows two cases for response to a duty cycle step change from
0 to 0.75 comparing single edge sampling at the carrier valley
and double edge sampling. Recall that the grid simulator
controller sends new control packets at 12 kHz. For a 600 Hz
carrier frequency this can cause artificial delay since the new
non-zero duty cycle may have arrived just after a S/H trigger
event. If the PWM system uses single edge sampling this
possibility exacerbates the potential for delayed response
compared to the double edge method which only waits half a
switching period before triggering a new S/H event.
Fig. 6: PLECS simulation for a 600 Hz PWM carriers with modulation index
step change from 0 to 0.75 (top) single edge sampling PWM (bottom) double
edge sampled PWM.
D. Implementing PWM Sampling in RSCAD
An RSCAD model of the PAU was developed in [8] for
controller hardware-in-the-loop (CHIL) testing for the grid
simulator controller. External to the RTDS racks is a GTFPGA
card that mimics the communication channel between the grid
simulator controller and the TWMC master controller. The
GTFPGA connects to RTDS over optical fiber to use received
values within the model. Presently the PAU model spans
multiple cards in the small time-step so the duty cycle from the
control packet (received via the GTFPGA) propagates to
RSCAD PWM generators in the large time-step. Similar to the
PLECS defaults, the RSCAD PWM system is a continuous
sampling without any S/H blocks so additional blocks must be
added to model for single or double edge methods.
In order to synchronize the timing of the S/H blocks with
each carrier, a separate square wave generator synchronized to
the PWM angle generator was implemented which feeds a
monostable pulse block 50 µs wide. The monostable pulse
block output then triggers a S/H block similar to Fig. 3.
An alternative method relies on a recent RSCAD update
that allows PWM generation to reside solely in the small time- Fig. 7: Experimental setup to measure cubes A1-A4 open circuit output
step, the new ANGRAMP3 and TRIWAV4 blocks. Within the voltages on PAU using oscilloscope, medium voltage probes and logic analyzer
inputs from FPGA controller.
small time-step bridge box, a set of comparators determine if
the carrier is greater than 0.97 or less than -0.97 to fire a
monostable pulse block to finally trigger a S/H subsystem. The
0.97 value is slightly less than 1 to guarantee there will always S/H registers on each slice using Eq. 2. However, this does not
be a sampling event regardless of the final small time-step definitively determine whether this is single (case II.C.) or
value. Along with a GTFPGA block in the same small time- double (case II.E) edge sampling since both methods can
step bridge box this includes the entire PWM system without potentially have four sequential S/H triggers if the non-zero
any need to pass signals back and forth to the large time-step. packet is sent just before the first S/H trigger in a group of four
carrier peaks or valleys. Furthermore, Fig. 8 shows the effect of
IV. EXPERIMENTAL RESULTS communication delay between the packet transmission event
indicated by a rising edge on the 12 kHz clock and the first
Experimental results were taken by first taking one PAU cube output change. As discussed above, switching frequencies
out of service and removing the series connection buswork beyond 1500 Hz will not have multiple command packets per
between cube outputs. Next a set of medium voltage S/H trigger in a double edge system so testing above 1500 Hz
differential probes were attached to cube output terminals on is required to measure communication delays. Otherwise,
A1-A5 as shown in Fig. 7. The grid simulator FPGA controller artificial delays are present as in the case of Fig. 6.
was modified for additional digital outputs to synchronize cube
voltage measurements with the 12 kHz synchronization The second test used a 600 Hz switching frequency and a
channel for the TWMC master, a new control packet is sent to time varying duty cycle as well as channel D1 on the
the PAU on each rising edge of this signal. Test profiles to oscilloscope. The controller sends a sequence of control
identify the PWM method had already been tested with the packets with incrementing magnitudes, resets the magnitude
CHIL configuration so the optical fiber connections previously sequence and toggles the sign, then repeats. In this case the
mated to the RTDS GTFPGA TWMC mock were connected packet sequence is 0.15, 0.15, 0.15, 0.3, 0.3, 0.6, 0.6, 0.6, 0.9,
back to the real TWMC master. 0.9, -0.15, -0.15, -0.15, -0.3, -0.3, -0.6, -0.6, -0.6, -0.9, -0.9
then repeats. The duplicated values were intended due to the
Figure 8 shows the oscilloscope capture for a step change number of 12 kHz events between each assumed S/H event for
test from 0 to -1 for 2 kHz switching frequency. The event was a 600 Hz carrier. Refer to Fig. 2 to see there is a 3-2-3-2 set of
triggered using digital channel D2 from the grid simulator samples between each S/H event if the PWM method is indeed
controller which indicates a non-zero duty cycle to be sent on double edge sampling on each carrier. Figure 9 shows the
the next rising edge of channel D0. Channel D1 was not used steady-state condition oscilloscope capture for this sequence.
for this test. Outputs on cubes A1-A4 change sequentially, not Channel D1 is tied to the negate enable in the FPGA controller.
simultaneously which indicates S/H triggering in the PAU There is noticeable delay between D1 returning to zero and the
PWM system. The timing between cube turn-on events is next positive pulse. This is due to the addition of
approximately 62.4 µs which further indicates there are local communication delay and the output pulse being centered near
1 1 the zero crossing of the carrier rather than immediately after
= = ∙ = 62.5 (2) the S/H event. This test is sure indication that two new control
8 2 8
packets reach the PWM comparator within a single carrier
 period, as well as a different value for each carrier which
confirms a double edge sampling method for each individual
carrier.
V. CONCLUSION
Developing validated simulation models takes a conscious
effort to analyze each subsystem of a converter including
PWM. Simulations and controller testing were performed to
de-risk experimental testing on a 9-level SCHB inverter
followed by a series of tests using the developed test
sequences. The initial assumption of a double edge sampling
for each carrier was confirmed by measuring the medium
voltage output of four individual power cubes. Future work
includes validation of dead-time and possible minimum pulse-
width limits from the grid simulator controller.
REFERENCES
[1] IEEE Standard Conformance Test Procedures for Equipment
Fig. 8: Oscilloscope capture for step change in duty cycle from 0 to -1 for Interconnecting Distributed Resources with Electric Power Systems, in
fsw = 2 kHz. Channel D1 not used for this test. IEEE Std 1547.1-2005 , vol., no., pp.1-62, July 1 2005.
[2] Inverters, Converters, and Controllers for Use in Independent Power
Systems, UL Std 1741, 2001.
[3] Steurer, M.; Edrington, C.S.; Sloderbeck, M.; Wei Ren; Langston, J., "A
Megawatt-Scale Power Hardware-in-the-Loop Simulation Setup for
Motor Drives," in Industrial Electronics, IEEE Transactions on , vol.57,
no.4, pp.1254-1260, April 2010.
[4] Lehfuss, F.; Lauss, G.; Kotsampopoulos, P.; Hatziargyriou, N.; Crolla,
P.; Roscoe, A., "Comparison of multiple power amplification types for
power Hardware-in-the-Loop applications," in Complexity in
Engineering (COMPENG), 2012 , vol., no., pp.1-6, 11-13 June 2012.
[5] Ametek, 'NREL Purchases Second AC/DC High Power Source from
Ametek', April 2015.
[6] ABB, ' Simulating extreme conditions in one of the world’s largest grid
simulators with a variable speed drive ', June 2015.
[7] Ledezma, E.; Kaiyu Wang; Keister, T.; Edwards, R.; Pipho, R.; Palle,
B.; Kulkarni, D.; Salem, T.E.; Fox, J.C.; Parsa, L., "Development of a
Modular Configurable Multi-megawatt Power Amplifier," in Industrial
Electronics Society, IECON 2013 - 39th Annual Conference of the
IEEE, vol., no., pp.631-636, 10-13 Nov. 2013.
[8] Leonard, J.; Hadidi, R.; Fox, J.C., " Real-Time Modeling of Multi-level
Megawatt Class Power Converters for Hardware-In-the-Loop Testing,"
in 2015 International Symposium on Smart Electric Distribution
Fig. 9: Oscilloscope capture for incrementing magnitude duty cycle with sign Systems and Technologies (EDST), Sept. 2015
toggling sequence. Channel D2 not used for this test.
[9] D. G. Holmes and T. A. Lipo, Pulse Width Modulation for Power
Converters: Principles and Practice, Wiley - IEEE Press, 2003.
[10] C2000 Real-Time Control Peripherals Reference Guide - SPRU566L,
Texas Instruments, p. 30, June 2015.
[11] TMS320x2833x, 2823x Enhanced Pulse Width Modulator (ePWM)
Module Reference Guide - SPRUG04A, p. 23, July 2009.