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APR
VERILOG CODES FOR 4TH SEM ELECTRONIC AND
19 COMMUNICATION STUDENTS (VTU)
HERE U WILL FIND ALL THE VERILOG CODES NECESSARY FOR YOUR SYLLABUS

// EXPT NO 1.VERLOG CODE FOR ALL BASIC GATES

module basic_gates(a,b, op_and,op_or,op_nand,op_xor,op_nor,op_not,op_xnor);
input a,b;//Two inputs a and b
output op_and,op_or,op_nand,op_xor,op_nor,op_not,op_xnor;
assign op_and=a & b;
assign op_or=a | b;
assign op_nand=~(a & b);
assign op_nor=~(a | b);
assign op_not=~a;
assign op_xor=a ^ b;
assign op_xnor=~(a ^ b);
endmodule

// EXPT 2A. VERILOG CODE FOR THE IMPLEMENTATION OF HALF ADDER.

module half_adder(a,b, sum,cout);
input a,b;
output sum,cout;
sum=a ^ b;
cout=a & b;
endmodule

//EXPT 2B. VERILOG CODE FOR FULL ADDER USING STRUCYURAL MODULING.
// component ha(half adder).
module ha(a,b, s,c);
input a,b;
output s,c;
assign s=a^b;
assign c=a&b;
endmodule
// full adder using two half adders and or gate
module full_adder_structural(a,b,cin, sum,cout);
input a,b,cin;
output sum,cout;
wire c1,c2,s1;
ha u1(a,b,s1,c1);
ha u2(s1,cin,sum,c2);
or (cout,c1,c2);
endmodule

//EXPT 2C. VERILOG CODE FOR FULL ADDER (DATA FLOW MODEL).
module full_adder_data_flow(a,b,cin, sum,cout);
input a,b,cin;
output sum,cout;
assign sum=a ^ b ^ cin;
assign cout=( a & b ) | ( b & cin ) | ( cin & a );
endmodule
//EXPT NO 2D. VERILOG CODE FOR THE FULL-ADDER(BEHAVIORAL MODEL).
module full_adder_behavioral(a,b,cin,sum,cout);
input a,b,cin;
output reg sum,cout;// o/p are to be declared as registers
reg T1,T2,T3,S1;// as variables in VHDL
always@(a,b,cin)
begin
T1=a&b;
T2=b&cin;
T3=cin&a;
Cout=T1 | T2 | T3;
S1=a^b;
sum=S1^cin;
end
endmodule
// EXPT 2E. VERILOG CODE FOR FULL-ADDER (MIXED STYLE OF MODEL).
module full_adder_mixed(a,b,cin, sum,cout);
input a,b,cin;
output sum, cout;
reg cout;
wire s1;// as signal in vhdl
reg t1,t2,t3;// as variables in vhdl
xor u1(s1,a,b);// structural xor gate
assign sum=s1 ^ cin;// data flow
// carry using behavioral description
always@(a,b,cin)
begin
t1=a & b;
t2=a & cin;
t3=cin & b;
cout=t1 | t2 | t3;
end
endmodule

// EXPT 3. VERILOG CODE FOR 8:1 MUX

module MUX8TO1(sel, A,B,C,D,E,F,G,H, MUX_OUT);
input [2:0] sel;
input A,B,C,D,E,F,G,H;
input reg MUX_OUT;
always@(A,B,C,D,E,F,G,H,sel)
begin
case(sel)
3'd0:MUX_OUT=A;
3'd1:MUX_OUT=B;
3'd2:MUX_OUT=C;
3'd3:MUX_OUT=D;
3'd4:MUX_OUT=E;
3'd5:MUX_OUT=F;
3'd6:MUX_OUT=G;
3'd7:MUX_OUT=H;
default:; // indicates null
endcase
end
endmodule

/* EXPT 4. VERILOG CODE FOR 2 TO 4 DECODER( SYNCHRONOUS WITH ENABLE).*/

module decoder_2to4(i, en, y);
input [1:0] i;
input en;
output reg [3:0] y;
always@(i,en)
begin
if(en==1)
y=4'd0;
else
case(i)
2'd0:y=4'b0001;
2'd1:y=4'b0010;
2'd2:y=4'b0100;
default:y=4'b1000;
endcase
end
endmodule
// EXPT NO 5A. VERILOG CODE FOR 8 TO 3 ENCODER (WITHOUT PRIORITY).
module encoder_8to3_without_priority(i, en, y);
input [7:0] i;
input en;
output reg [2:0] y;
always@(i,en)
begin
if(en==1)
y=4'd0;
else
case(i)
8'b00000001:y=3'd0;
8'b00000010:y=3'd1;
8'b00000100:y=3'd2;
8'b00001000:y=3'd3;
8'b00010000:y=3'd4;
8'b00100000:y=3'd5;
8'b01000000:y=3'd6;
8'b10000000:y=3'd7;
default:;
endcase
end
endmodule
// EXPT 5B. VERILOG CODE FOR 8 TO 3 ENCODER (WITH PRIORITY).
module encoder_8to3_with_priority(i, en, y);
input [7:0] i;
input en;
output reg [2:0] y;
always@(i,en)
begin
if(en==1)
y=3'd0;
else
casex(i)
8'b1xxxxxxx:y=3'd7;
8'b01xxxxxx:y=3'd6;
8'b001xxxxx:y=3'd5;
8'b0001xxxx:y=3'd3;
8'b00001xxx:y=3'd4;
8'b000001xx:y=3'd2;
8'b0000001x:y=3'd1;
default:y=3'd0;
endcase
end
endmodule
// EXPT 6. VERILOG CODE FOR 4 BIT BINARY TO GRAY CONVERTER.
module binary_to_gray_4bit(b, g);
input [3:0] b;
output [3:0] g;
assign g[3]=b[3];
assign g[2]=b[3] ^ b[2];
assign g[1]=b[2] ^ b[1];
assign g[0]=b[1] ^ b[0];
endmodule
// 7a. VHDL CODE FOR 1:8 DEMULTIPLEXER.
module demux_1to8(i, sel, y);
input i;
input [2:0] sel;
output reg [7:0] y;
always@(i,sel)
begin
y=8'd0;
case(sel)
3'd0:y[0]=i;
3'd1:y[1]=i;
3'd2:y[2]=i;
3'd3:y[3]=i;
3'd4:y[4]=i;
3'd5:y[5]=i;
3'd6:y[6]=i;
default:y[7]=i;
endcase
end
endmodule

// 7B. COMBINATIONAL VERILOG CODE FOR N BIT COMPARATOR.

module comparator(a,b, alb,agb,aeb);
parameter N=3;
input [N:0] a,b;
output reg alb,agb,aeb;
always@(a,b)
begin
if(aelse alb=1'b0;
if(a>b) agb=1'b1;
else agb=1'b0;
if(a==b) aeb=1'b1;
else aeb=1'b0;
end
endmodule
// SEQUENTIAL CIRCUITS.
// EXPT NO 8. VERILOG CODE FOR FOLLOWING FLIP-FLOPS.
// 8A). SR FLIP-FLOP
module sr_flipflop(s,r,clk, q,qbar);
input s,r,clk;
output reg q,qbar;
reg [20:0] clk_div=21'd0;
reg int_clk;
wire [1:0] temp;
always@(clk
begin
clk_div=clk_div+1;
int_clk=clk_div[20];
end
always@(int_clk)
begin
temp={s,r};
case(temp)
2'b00:begin q=q; qbar=qbar; end
2'b01:begin q=1,b0; qbar=~q; end
2'b10:begin q=1'b1; qbar=~q; end
default:begin q=1'bz; qbar=1'bz; end
endcase
end
endmodule
// 8B). D FLIP-FLOP
module d_ff(d,clk, q,qb);
input d,clk;
output reg q,qb;
reg [22:0] clk_div=23'd0;
reg int_clk;
always@(posedge(clk))
begin
clk_div=clk_div+1;
int_clk=clk_div[21];
end
always@(posedge(int_clk))
begin
if(d==0)
q=1'b0;
else
q=1'b1;
qb=~q;
end
endmodule
// 8C).JK FLIP-FLOP.
module jk_ff(jk, clk, q,qb);
input [1:0] jk;
input clk;
output reg q,qb;
reg [22:0] clk_div=23'd0;
reg int_clk;
always@(posedge(clk))
begin
clk_div=clk_div+1;
int_clk=clk_div[21];
end
always@(posedge(int_clk))
begin
case(jk)
2'b01:q=1'b0;
2'b10:q=1'b1;
2'b11:q=~q;
default:q=q;
endcase
qb=~q;
end
endmodule
// 8d). T FLIP-FLOP.
module t_ff(t,clk, q,qb);
input t,clk;
output reg q,qb;
reg [22:0] clk_div=23'd0;
reg int_clk;
always@(posedge(clk))
begin
clk_div=clk_div+1;
int_clk=clk_div[21];
end
always@(posedge(int_clk))
begin
if(t==0)
q=1'b0;
else
q=~q;
qb=~q;
end
endmodule
// 9. VERILOG CODE FOR 8 BIT ALU.
module alu_8_bit(x,y, opcode, yout);
input [7:0] x,y;
input [2:0] opcode;
output reg [15:0] yout;
always@(x,y,opcode)
begin
case(opcode)
3'b000:yout=x+y;
3'b001:yout=x-y;
3'b010:yout=x*y;
3'b011:yout=x&y;
3'b100:yout=x|y;
3'b101:yout=~x;
3'b110:yout=x^y;
default:yout=~(x&y);
endcase
end
endmodule
// EXPT NO 10 A.DESIGN 4 BIT BINARY COUNTER (SYNCHRONOUS RESET).
module binary_count_sync(clk,rst, count);
input clk,rst;
output reg [3:0] count;
reg [21:0] clk_div=22'd0;
reg int_clk;
always@(posedge(clk))
begin
clk_div=clk_div+1;
int_clk<=clk_div[20];
end
always@(posedge(int_clk))
begin
if(rst==1)
count=3'd0;
else
count=count+1;
end
endmodule
// EXPT NO 10 B.BINARY COUNTER WITH ASYNCHRONOUS RESET.
module binary_count_ashyn(clk,rst, count);
input clk,rst;
output reg [3:0] count;
reg [21:0] clk_div=22'd0;
reg int_clk;
always@(posedge(clk) )
begin
clk_div=clk_div+1;
int_clk=clk_div[20];
end
always@(posedge(int_clk),posedge(rst))
begin
if(rst==1)
count=4'd0;
else if(int_clk==1)
count=count+1;
end
endmodule

// EXPT NO 10 C. VRILOG CODE FOR ANY SEQUENCE COUNTER

module any_sequence_counter(clk, q);
input clk;
output reg [3:0] q;
reg [21:0] clk_div=22'd0;
reg int_clk;
reg temp;
always@(posedge(clk))
begin
clk_div=clk_div+1;
int_clk=clk_div[20];
end
always@(posedge(int_clk))
begin
case(temp)
4'b0000:temp=4'b0010;
4'b0010:temp=4'b0100;
4'b0100:temp=4'b1000;
4'b1000:temp=4'b1100;
4'b1100:temp=4'b1110;
default:temp=4'b0000;// first sequence is 0000
endcase
q=temp;
end
endmodule
// EXPT 11. BINARY UP DOWN COUNTER
module binary_up_down_counter(clk,up_down, q);
input clk,up_down;
output reg [3:0] q;
reg [21:0] clk_div=22'd0;
reg int_clk;
integer temp=0;
always@(posedge(clk))
begin
clk_div=clk_div+1;
int_clk=clk_div[20];
end
always@(int_clk)
begin
if(up_down==1)
if(temp==9)
temp=0;
else
temp=temp+1;
else
if(temp==0)
temp=9;
else
temp=temp-1;
end
always@(temp)
begin
case(temp)
0:q=4'd0;
1:q=4'd1;
2:q=4'd2;
3:q=4'd3;
4:q=4'd4;
5:q=4'd5;
6:q=4'd6;
7:q=4'd7;
8:q=4'd8;
9:q=4'd9;
default:;
endcase
end
endmodule

Posted 19th April 2009 by yajnesh padiyar

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