Thin Solid Films 519 (2011) 5161–5164

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Thin Solid Films

j o u r n a l h o m e p a g e : w w w. e l s ev i e r. c o m / l o c a t e / t s f

The influence of hafnium doping on bias stability in zinc oxide thin film transistors
Woong-Sun Kim a, Yeon-Keon Moon a, Kyung-Taek Kim a, Sae-Young Shin a, Byung Du Ahn b,
Je-Hun Lee b, Jong-Wan Park a,⁎
a
Department of Materials Science and Engineering, Hanyang University, 17 Haengdang-dong, Seoungdong-ku, Seoul 133-791, Republic of Korea
b
Samsung Electronics Co., Ltd., LCD Business, San 24 Nongseo-dong, Giheung-gu, Yongin, Gyonggi-do 446-711, Republic of Korea

a r t i c l e i n f o a b s t r a c t

Available online 15 January 2011 We investigated the influence of hafnium doping on negative bias temperature instability (NBTI) and positive
bias temperature instability (PBTI) in zinc oxide thin film transistors (TFTs). Hafnium zinc oxide (HZO) TFTs
Keywords: exhibited turn-on voltage (VON) shifts of 0 V for negative stress bias and + 3 V for positive stress bias,
Thin film transistor (TFT) compared with −5 V and + 9 V, respectively, for ZnO TFTs. The enhanced improvement of the VON shift may
Oxide semiconductor be due to a reduction in interface trap density resulting from the suppression of oxygen vacancy related
Hafnium zinc oxide (HZO)
defects caused by the high binding energy of Hf ions.
Negative bias temperature instability (NBTI)
Positive bias temperature instability (PBTI)
© 2011 Elsevier B.V. All rights reserved.

1. Introduction must be minimized, effective approaches to solve the instability

Thin film transistors (TFTs) based on oxide semiconductors have
recently attracted a great deal of attention, particularly use in active-
matrix TFT-based backplanes such as active-matrix liquid crystal
displays (AM-LCDs) used in ultradefinition flat panel products with,
high frame rates and large sizes. Among oxide semiconductors, zinc-
based materials have been studied as active channel materials for
TFTs due to their high performance parameters (high mobility, low
cost, high transparency and low temperature processibility) com-
pared to conventional amorphous silicon and polycrystalline silicon
TFTs [1–4].
To achieve efficient manufacture of ZnO-based TFTs, it is crucial to
overcome problems of voltage independent stability and reliability.
Any shift in the turn-on voltage (VON) of the driving transistor in on-
or off-bias stressed conditions will cause a reduction in output drain
current, leading to device malfunction. In commercial AM-LCD
devices, the total stress time of the negative gate bias is more than
500 times that of the positive gate bias. Several studies of bias-induced
instabilities in ZnO-based TFTs have reported deterioration in
electrical characteristics [5–8]. These studies suggest that bias-
induced instability can be suppressed by inserting a protection layer
or by changing gate dielectrics. A recent report found that Zr doping in
InZnO semiconductor materials can lead to improved stability under
long-term bias stresses [9]. Zr may play a role in the InZnO film to
control the net electron carrier concentration by suppressing carrier
generation. Although the bias induced VON shift in ZnO-based TFTs
⁎ Corresponding author.
E-mail address: jwpark@hanyang.ac.kr (J.-W. Park).
problem have not been reported in the literature.
In this study, we report new hafnium zinc-oxide (HZO) semicon-
ductor materials that have been developed for use as active-channel
layers to resolve both negative and positive bias temperature
instability (NBTI and PBTI) issues related to ZnO-based TFTs. These
devices were fabricated with HZO films deposited in a two-step
process in order to investigate bias stability improvement. For com-
parison, an HZO (the atomic ratio of Hf in HZO films: 0.8 at. %) film
10 nm thick was first grown on the dielectric, and then the intrinsic
30-nm-thick ZnO film was deposited onto the HZO film. A second
sample was deposited in the reverse order. We found that the Hf in
the HZO thin films acts to control the trap density in the interfacial
layer by suppressing defect related oxygen vacancies.
2. Experimental details
Sputtering was performed at room temperature in an argon
atmosphere devoid of oxygen. A 4 inch diameter ceramic target, 4 cm
from the substrate, was used at a base pressure of 2.7 × 10− 4 Pa, a
working pressure of 6.6 × 10− 1 Pa, and a plasma discharge power
density of 0.5 W/cm2. ITO electrodes were used for both the source
and drain electrodes, and these were deposited by DC magnetron
sputtering at room temperature. Finally, the device was subjected to
thermal annealing at 300 °C and 400 °C for 60 min in ambient air. All
electrical characterizations were performed with a semiconductor
parameter analyzer (Agilent HP 4145B) at room temperature in the
dark. The atomic ratio of Hf in the HZO film (analyzed by inductively
coupled plasma mass spectroscopy) was 0.4 at.%. The structural
properties of the HZO films were analyzed using X-ray diffraction
(XRD) and high resolution transmission electron microscopy
(HRTEM).

0040-6090/$ – see front matter © 2011 Elsevier B.V. All rights reserved.
doi:10.1016/j.tsf.2011.01.079
5162 W.-S. Kim et al. / Thin Solid Films 519 (2011) 5161–5164
3. Results and discussion
Fig. 1 shows a cross-sectional schematic of a bottom gate-type HZO
TFT with a staggered structure prepared on heavily doped n-type
silicon substrates having an O2 plasma treated gate insulator. Before
depositing the HZO channel layer, O2 plasma treatment (500 W,
0.1 torr) was carried out using electron cyclotron resonance (ECR)
type remote plasma on a Si3N4/n-Si substrate. Thin films of HZO (40-
nm-thick) were deposited using DC magnetron sputtering. The
predominant diffraction peaks correspond to the (002) orientation,
which indicates that this film had a c-axis orientation polycrystalline
structure regardless of Hf insertion, as shown in Fig. 2.
Fig. 3(a)–(d) shows the evolution of transfer curves as a function
of applied stress time for HZO TFTs and the reference ZnO TFTs and
Table 1 shows the device parameters for the TFTs. The devices were
stressed under either a −20 V or +20 V bias stress gate source
voltage relative to the turn on voltage (VON) and a 0.1 V drain source
bias at 60 °C. Fig. 3(a) and (c) shows the shift of the transfer curves
under the negative bias stress for ZnO TFT annealed at 300 °C and HZO
TFT annealed at 400 °C. Fig. 3(b) and (d) shows similar data for
positive stress. While Fig. 3(a) and (b) shows a considerable shift of
the transfer characteristics, Fig. 3(c) and (d) reveals little change in
the device properties. The VON of the ZnO TFTs gradually shifts −5 V
under negative bias stress and 9 V under positive bias stress, while the
VON of the HZO TFTs maintains close to the initial state under negative
bias stress and shows a small shift of 3 V under positive bias stress
(total stress time 3 h). The VON shift is larger for the positive bias
than the negative bias, possibly because the applied positive stress
corresponds to very severe test conditions, as a drain current of
approximately 1 × 10− 6 A is required to manifest the full white gray
color in active-matrix organic light-emitting diode (AMOLED) devices
[10]. Despite the fact that the device was exposed to harsh conditions
(i.e., the Hf content was very low, and the devices were fabricated
without a passivation layer) they showed little change from initial
properties compared to ZnO TFTs. From Fig. 3(a)–(d), it is clear that Hf
doping significantly improves both the NBTI and PBTI of the ZnO TFTs.
It can also be seen that all devices show parallel VON changes in the
negative and positive directions (for negative and positive stress,
respectively) with increasing stress time without any significant
changes in field-effect mobility, subthreshold swing (SS), or ION/OFF
ratio.
The stability of TFTs under gate bias stress is of crucial importance
for their exploitation and it is noted that the two mechanisms
responsible for this instability are defect creation and simple charge
trapping. As in previous reports, the devices showed a negative or
positive rigid log (ID)–VGS transfer curve shift and a negligible change
in SS values; these phenomena are explained by simple charge
Fig. 1. A cross-sectional schematic of a bottom-gate-type HZO TFT with a staggered
structure.
Fig. 2. X-ray diffraction (XRD) patterns of ZnO and HZO films deposited on silicon
nitride substrates. The inset shows a cross-sectional high resolution transmission
electron microscope (HRTEM) image of the HZO films.
trapping rather than defect creation [11–14]. Many groups using
many different material systems have reported a positive or negative
parallel VON shift under low field gate bias stressing (~1 MV/cm) with
little or no change in SS, μ, etc., and rapid recovery without annealing,
suggesting simple charge trapping without creation of new defects.
The shift in VON accompanying the change in SS comes from the
creation of defects within the channel material, while the parallel shift
in VON without strong changes in the SS value is attributed to simple
charge trapping in the gate dielectric or at the interface between the
channel layer and the dielectric. Although, previous reports have
discussed instability mechanisms including electron trapping within
the gate dielectric, charge trapping within the dielectric requires
relatively high electric fields and the devices fabricated herein
spontaneously recover their initial state after a period of relaxation
of couple of hours without any annealing procedure (data not shown).
Thus, we could exclude the possibility of defect creation and charge
injection in the gate insulator layer [15]. Also, the devices fabricated in
the present study have the same dielectric with different instabilities.
We note that a VON shift without SS change may be caused by simple
charge trapping at the interface or bulk trap rather than the dielectric,
and that Hf doping might reduce the trap density.
To evaluate whether the interface trap density or the bulk trap
density is the main contributor to the deterioration in bias stability,
two-step deposited HZO films containing 0.8 at.% Hf were fabricated
with the following structures: HZO 40 nm (A), ZnO 30 nm/HZO 10 nm
(B), and HZO 30 nm/ZnO 10 nm (C). An SiO2 layer of 10 nm was
deposited using PECVD on an Si3N4/n-Si substrate before depositing
the HZO channel layer.
Fig. 4 shows the VON shifts for devices A, B and C as a function of
stress time and Table 2 shows the device parameters for the TFTs. The
devices were tested under the negative bias stress conditions
described above. While device C showed a significant deterioration
in the VON value, device A exhibited a smaller VON shift of −6 V. No
device showed significant changes in SS or μFE values. As mentioned
above, VON shifts after bias stress can be attributed to simple charge
trapping rather than to defect creation. If the reduction of the total
trap density including interface and bulk trap of devices A, B, and C is
the origin of the enhanced stability independently, devices A and B,
which have the same interface, and devices A and C, which have the
same bulk quality, should have similar stable properties. However, the
similar VON shifts for devices A and B suggest a reduction in the
interface trap density rather than a reduction of the bulk trap density.
The small amounts of charge trapping observed for devices A and B,
 W.-S. Kim et al. / Thin Solid Films 519 (2011) 5161–5164 5163

Fig. 3. The evolution of transfer curves for (a) ZnO TFTs and (c) HZO TFTs as a function of the applied negative bias temperature stress time, and (b) ZnO TFTs and (d) HZO TFTs as a
function of the applied positive bias temperature stress time.

which have the same interface, might be related to the fact that the stability. However, we also note that the VON shifts of the ZnO TFTs
interface trap density is lower than that for device C. The decreases in were more unstable under stress conditions. ZnO TFTs, which have
the VON shifts of devices A and B indicate a reduction in the interface polycrystalline phases, show inferior characteristics, with VON shifts
trap density owing to the higher oxygen binding energy of Hf ions over 10 V [6]. Although the HZO films also have a polycrystalline
compared to Zn ions. Therefore, suppressing the generation of oxygen phase, the HZO TFTs annealed 400 °C showed excellent bias stability
vacancy related defects with Hf doping can effectively decrease trap improvement. Therefore, the Hf elements in HZO films can affect the
formation at the interface.
Fig. 5 illustrates the influence of post-deposition annealing on VON
variation. The stabilities of the ZnO TFTs and the HZO TFTs (annealed
at 300 and 400 °C, respectively) were compared. The ZnO device
showed both large positive and negative shifts in VON after bias stress
application. However, HZO TFTs exhibited more stable characteristics
after the application of both positive and negative bias stress.
Obviously, the higher annealing temperature resulted in better
stability characteristics, which might be due to the reduction in trap
density at the interface. For the devices annealed at higher
temperatures, the VON changes decreased, indicating improved bias

Table 1
Comparison of the electrical properties including μFE, ION/IOFF, SS, and VON of ZnO and
HZO TFTs.

Channel layer μFE (cm2/Vs) ION/IOFF SS (V/decade) VON (V)

ZnO TFT annealed at 300 °C 0.72 1.04 × 108 2.06 −3

ZnO TFT annealed at 400 °C 6.50 3.75 × 107 2.04 −3
HZO TFT annealed at 300 °C 2.18 7.76 × 108 2.00 −2
Fig. 4. The logarithmic dependence of the VON shift for the three devices: HZO 40 nm
HZO TFT annealed at 400 °C 9.22 8.50 × 107 1.09 −6
(A), ZnO 30 nm/HZO 10 nm (B), and HZO 30 nm/ZnO 10 nm (C).
5164 W.-S. Kim et al. / Thin Solid Films 519 (2011) 5161–5164

Table 2 compare improvements in VON shifts. The parallel shift in the VON
Comparison of the electrical properties including μFE, ION/IOFF, SS, and VON of ZnO and under bias stress for the ZnO TFTs suggests simple charge trapping
HZO TFTs deposited by a two-step process.
into the interfacial layer as the origin of the instability, rather than
Channel layer μFE (cm2/Vs) ION/IOFF SS (V/decade) VON (V) bulk charge trapping in the channel layer. The HZO TFT annealed at
Device A 2.76 3.37 × 108 2.01 −2 400 °C exhibited excellent stability under both negative and positive
Device B 2.08 2.25 × 107 2.00 −3 stress due to the higher binding energy of Hf ions with oxygen.
Device C 6.33 7.77 × 105 2.06 −1 Further, HZO semiconductors may be promising candidates to solve
important stability issues.

reduction of trap density especially in the interface between the Acknowledgement

dielectric and channel layer.
The SS was extracted from the linear portion of the IDS versus VGS
plot using the following equation [SS = dVGS / d log IDS (V/decade)].
The HZO TFTs annealed at 300 °C and 400 °C revealed SS values of 2.01
and 1.09 V/decade, while the ZnO TFTs annealed at 300 °C and 400 °C
showed similar SS values. Thus we suggest that the interface trap
density value for the HZO TFTs was smaller than that for the ZnO TFTs.
This lower interface trap density might explain why Hf doping can
reduce the VON shift caused by charge trapping. When the appropriate
annealing treatment is applied, Hf ions can act as stabilizers against
bias stress by binding oxygen in the HZO films.
4. Conclusions
In summary, we investigated the effects of Hf doping on both
negative and positive bias stability in HZO TFTs. Compared to ZnO
TFTs, HZO TFTs showed enhanced stability improvement, even at low
doping levels. Two-step deposited samples were fabricated to
This research was supported by the Basic Science Research
Program through the National Research Foundation of Korea (NRF)
funded by the Ministry of Education, Science and Technology (2009-
0072367).
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Fig. 5. The logarithmic dependence of the VON shift for ZnO and HZO TFTs annealed at
300 °C and 400 °C as a function of time: (a) negative stress and (b) positive stress.