A skilled FPGA Engineer having experience in Porting Verilog/VHDL based ASIC RTL onto custom

FPGA platform.
Good understanding of the low speed peripherals like I2C/SPI and beginner in PCIe, DDR3
protocols.
Debugging experience in multi FPGA hardware board issues using lab equipments such as
oscilloscopes, logic analyzer, debugging software (Reveal).
Strong understanding of FPGA architecture and Lattice tools.
Verification of AMBA-AXI4 protocol as Post graduation Project.
Experience of developing Layouts of digital blocks like Inverter, NAND, NOR etc. and digital
circuits like Adders, Subtractor, Flip-flops.
Performed Physical verification checks like DRC, LVS.
Exposure on layout design tool such as Micro Magic and layout simulation tool IRSIM, ngspice. 
Familiar with physical design implementation, physical design strategies, and static timing analysis
 Knowledge of ASIC design flow, digital circuit design, and Chip Partitioning  Basic knowledge of
Design for Test, Clock Tree, Memory BIST, DFT Rule Checking.