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Development Manager - Over 13 Years' Experience In: Amit Tripathi
Development Manager - Over 13 Years' Experience In: Amit Tripathi
Linux & Firmware Development / DSP Programming & Algorithm Optimization Domain Preference: Audio /
Video CODEX
SKILL SET PROFILE SUMMARY
Profiling / Optimization of Large Excellent track record of working on projects involving
Scale Embedded Software Systems Optimization of Audio / Video Codes, Speech and DSP
C-code Optimization algorithms
Assembly Coding Currently involved in Designing and integration of LoRa based
wireless communication protocol on Linux.
Wireless Standard and Protocol
Extensively worked on DTV product, involving identification of
Development
critical stability and performance stats of latest released TV
Testing, Defect Analysis, Debugging firmware on the basis of results of automated integrated
& Bug Fixing monitoring software.
Test Data Analysis Proven success in optimization of Audio Codec on ARMv6
Process Defect Identification Processor involving optimization of SBADPCM (G.722), Half
Project Management Rate & NAMR Codec, AMR-WB+ (Extended Adaptive Multi-rate
Product Lifecycle Management Wideband), AMR-NB (Adaptive Multi Rate Narrowband) and
G711 & G729 Codec
C & Assembly Programming
Helped increase revenue growth & market share of
Multimedia Solutions & Multimedia organization, by optimizing product performance,
Framework Development understanding complex requirements, utilizing best coding
Cost Estimation, Risk Management practices and through complex integrations
Project and Process Audits Highly skilled in improving processes by identifying process
defects
Skilled in end-to-end Product Development Life Cycle
including defining the software architecture, design,
implementation, verification and validation meeting time to
market and quality goals
Dynamic, flexible & approachable with excellent planning,
analytical, problem solving and communication skills; skilled
to interface directly with external partners, suppliers, and both
internal & external customers
TECHNICAL SKILLS
WORK EXPERIENCE
Responsibilities:
Defining requirements, contributing to definition of electronics hardware design, design embedded system
software architecture & algorithm solutions
Setting-up test plans; performing validation testing to confirm that system and functional requirements
are met
Estimating development, resources and timing to achieve the desired results; helping define embedded
system level and algorithm requirements to meet product performance and reliability requirements
Identifying & improving embedded controls standards and processes
Inventing & developing embedded control system strategies and lead architecture design to achieve
solutions; using debugging and simulation tools to perform design iterations and optimization
Verifying solutions through simulation, sub-system, hardware-in-the-loop and vehicle level testing
Driving implementation consistency across multiple resources contributing to the same embedded system
architecture
Documenting improvements to the engineering standard work processes
Utilizing FMEA process to enhance design robustness; contributing to continued enhancement of Core
Embedded Software to support additional product features
Accomplishments:
Achieved fantastic track record for delivering projects on committed dates meeting high quality
expectations and high level of customer satisfaction on consistent basis
Played a key role in keeping control over quality parameters such as factory defect rate, call rate & defect
on arrival for released product as part of Life Cycle Management (LCM) and in implementation of
Corrective & Preventive actions (CAPA) during Product Life Cycle Management
Put strong emphasis on quality and stability improvements to the product; led and mentored a dedicated
team of engineers whose main focus was on improving product stability
Mentored project teams on technical, quality processes and shared best practices as part of knowledge
sharing / continuous team improvements
ACADEMIC DETAILS
2000-2004: Bachelor of Technology (Electronics & Communication Engineering) from Prof. Ram Meghe
Institute of Technology & Research, Badnera, Amravati University with 69.7 % marks
1999-2000: 12th (Math and Biology) from Anglo hindi junior college, Yavatmal with 73 % marks
PERSONAL DETAILS
PROJECT DETAILS
Title: Implementation of Dyninst API for Linux based MIPS and ARM Platform
Project Scope:
Dyninst - API is open source code supported for various platforms; the main goal of project was to provide
runtime code analysis and debugging support for the MIPS/ARM-Linux platform
The complete Dyninst-API was ported and real time testing was conformed on arm/mips-Linux platform
Developed internal tool to profile and trace applications & Linux operating system with the help of
Samsung Russia using probe and dynamic instrumentation mechanism
Worked on following Applications:
o Runtime Debugger
o Performance Measurement Tool
Title: Optimization of Acoustic Echo Cancelation
Project Scope:
The aim of the project was to provide fast and cost efficient voice quality enhancement using low cost
conexant kite camera hardware having AEC for those TV with embedded camera
It also aimed to provide ARM v7 neon architecture specific optimized software solution of voice quality
enhancement for the smart TV having no embedded camera or Skype specific cameras
The project mainly involved:-
o ARM v7 neon based architecture specific C optimization of AEC
o Floating point ACE c code convertion to fixed point
o Assembly coding of critical modules of AEC like NLMS algorithm, VAD, pre-processing and post
processing filters
o Cross compilation for Linux supportive operating system for ARMv7 neon based 32 bit architecture
Title: Design, Implementation and Optimization of HARQ for Wimax on Base Station
Project Scope:
Design and coding on Base Station supporting SCDMA and WiMax both on single P4 platform for Hybrid
Automatic Repeat request with chase combining method as per WiMax standard 802.16e chapter 8.4.9
supporting 8 Sub channels
Special care was taken for optimization of a module which had functionality to perform de-puncturing, de-
multiplexing, de-interleaving on packed block with 4-bit LLR
For fulfilling the MIPS criteria complete HARQ code dividing into multiple thread and also CTC Decoder was
implemented on hardware up link side.
While for down link HARQ CTC Encoder design and optimization was in progress
A huge memory requirement for HARQ supporting 8 sub channels was managed by implementing it on
C6713 processor