L-Edit

&
Design Rules
Kuwait University
Electrical Engineer Department
By Eng. Ahmad Haitham

1
 L Edit
L-Edit
„ L-Edit is an Integrated Circuit Layout
Tool used to draw the two dimensional
geometry of the masks or layers to fabricate
an integrated circuit.

„ Different layers
y are represented
p
by different colors and patterns. Sample
p of Metal Mask
2
 L Edit
L-Edit
„ Manufacturingg constraints can be defined
in L-Edit as design rules.

„ L-Edit files are saved as file_name.tdb

(Tanner Database).

„ L-Edit can import and export two industry

standard mask layout formats (GDSII and
CIF).
„ GSII:(Gerber Data Stream Information Interchange).
„ CIF: (Caltech Interchange Format) 3
 L Edit Modules
L-Edit
„ L Edit The
L-Edit: Th llayoutt editor
dit
„ L Edit ⁄ DRC:
L-Edit DRC The
Th design
d i rule
l checker
h k
„ L-Edit
L Edit ⁄ Extract:
E t t TheTh layout
l t extractor
t t to t
SPICE
„ L-Edit ⁄ SPR: an automatic standard cell
placement and routing package
4
L-Edit
L Edit Window

5
L-Edit Toolbars

6
 Layer Palette
Graphical menu of the available layers.
layers

7
Things to Know:

„ The most important scale or dimension

in the layout is called lambda (λ).
(λ)

„ Lambda (λ) must equal half of (L), the

channel length of the MOSFET, i.e, half
the size of technology used.

L=2*λ
8
 L-Edit Window

You must set the length of the square to represent

One lambda or one Locator Unit

9
 Design Parameters Setup
(1- Technology)
From Menu
F M >>
Setup >> Design >> Create a name for
Technology fabrication
process

This is the unit in

The technology.
Select Lambda

10
 Technology Parameters Setup
* You need to know that when you export your
file to DGSII. The default for GDSII is that
one internal unit is 1 nm (1/1000 lambda)

Or Lambda= 1000 internal unit

* The technology length L= 2* Lambda

L= 0.5 Microns 1 Lambda = 0.25 Micron

* (L-edit max size is from

-536,870,912 to +536,870,912 internal units)

* Internal units are what is actually used in

L-Edit to store information

* This is not what displayed to you.

11
 Design Parameters Setup
(2 Grid)
(2-
From Menu >>Setup >>
Design >>Grid

These are jus the dots shown on the screen

Make the length of the Grid in the working area

to be equal one Locator Unit

To set one locator Unit=lambda

So one locator Unit=1000 internal units

•Its better to set the mouse snap grid 0.5 lambda,

i.e 0.5 Locaor units

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CMOS
Design
g
Rules

13
„ In general, there are three main classes of design
rule specifications
specifications. These are

„ Minimum Width.
Width Which is the smallest
dimension permitted for any layer in the layout
drawing

„ Spacing. Which is the smallest distance

permitted
itt d b
between
t the
th edges
d off two
t layers.
l

„ Surround. This apply to layers placed within

Surround
larger ones (such as contacts).

„ Every layer has a minimum width and minimum

spacing value in between all in terms of Lambda.
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 NMOS Layout:
Layers: Poly,
Poly Active,
Active Nselect
Nselect,, Pselect
Pselect,, Metal,
Metal Active Contact

1λ
2λ 2λ (W)
2λ

3λ
2λ (L)
(L)
L must equal to 2λ Minimum spacing from Active to Nselect or Pselect is 2λ
All contacts must be 2λx2λ Minimum Metal 1 surround Contact is 1λ 15

Minimum Metal1
Metal1 width =
=33λ W must be greater than 3λ
 PMOS Layout:
y
Layers: Poly, Active, Nselect
Nselect,, Pselect
Pselect,, Metal, Active Contact, NWell

3λ

6λ 2λ (W)
2λ
1λ
2λ

2λ (L)
(L)
16
Minimum spacing from Active to Nwell edge is 6λ
CMOS Layout Rules - NWell

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CMOS Layout Rules - Active

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CMOS Layout Rules - Poly

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CMOS Layout Rules – Select

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CMOS Layout Rules - Contact to Poly & Contact to Active

21
CMOS Layout Rules - Metal1

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CMOS Layout Rules - Via

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CMOS Layout Rules - Metal2

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 Layout
y Example
p
Draw the layout of a CMOS inverter given the following:
L= 0.5µm, Wn= 1.0 µm, and Wp= 2.5 µm.

25
Stick Diagram
Vdd = 5V

pMOS

Vin

N MOS

26
 R
Run L
L-EDIT
EDIT
by Double click on its icon

27
 Design Setup

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As mentioned before from: From Menu >>Setup >> Design >>
• Draw a Vertical Ploy layer that
representt the
th gate
t off the
th opposing
i
PMOS & NMOS.

• The width of this poly must be

Equal to L=2λ.

• The vertical height should be fixed

depends on The maximum spacing
required to draw your Layout.

• Select this height= 70λ.

2λ

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 2λ
4λ

• Draw Metal1 layers for the VDD &

VSS power supplies.

• The minimum width for Metal1=3λ,

but to distinguish the power supply than
otherMetal1 wiring, make its width=4λ.

•Keep a 2λ extension of ploy as shown.

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4λ
2λ
• Draw the NMOS as discussed L= 0.5 µm, i.e. λ= 0.25 µm
before
Wn= 1.0 µm, i.e. Wn= 4λ

4λ

31
•Click the home button to view the
whole layout

NMOS

32
 • Draw the PMOS as discussed before
before.

10λ

L= 0.5 µm, i.e. λ= 0.25 µm 33

Wp= 2.5 µm, i.e. Wn= 10λ

 PMOS

•Click the home button to view the

whole layout

NMOS

34
 Connect the drain of
PMOS to the drain of
NMOS by Metal1 layer
3λ of 3λ width

35
Make 6λ by 6λ Ploy Why? To make extra Metal
4λ by
b 4λ Metal1
M t l1 Connection to the gate.
2λ by 2λ Poly Contact

36
Do the same to the other end of
The Poly

37
Why?
Wh ?
To make extra
connection to the
output to use it
later.

38
Naming The Nodes

• Click to Port
• Click the Metral1 of the object
j yyou
want to give a Name.

39
40
 L-Edit Design Rule Check
You have to run Design Rule Check (DRC) most of the time if your
are adding, removing or editing layers in the layout.

or from here

This action opens a dialog box that allows you to specify the format of
the output.
output
41
 L Edit Extractor
L-Edit
„ L-Edit can be used to generate SPICE-compatible circuit file
listings using the Extract option in the setup window of the
menu bar.
bar

„ L-Edit
L Edit does not automatically identify the ground to 0 V or
power supply to 3 V. So the generated file must be edited to
identifyy the corresponding
p g voltages.
g

„ You should add the MOS MODEL parameters depending on

the technology used before a SPICE simulation is performed.

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 L Edit Extractor
L-Edit
„ Running the Extractor:

or from here

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L Edit Extractor
L-Edit

Enter the name of the

extractor definition file

Enter the name of the

SPICE output file.
• name.cir for PSPICE AD
•name.sp for TSPICE

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L-Edit Extractor

Select

•Comments: Write Nodes Names

•Write Nodes as: Integers

•Write
i Node parasitic
i i Capacitance.
C i

•Place device labels on layer:

y Metal1

•Then Click Run

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 L-Edit
L Edit Extractor
The following window will appear:

Click: Ignore All

46
Run PSPICE AD

47
Run PSPICE AD

48
 The generated SPICE file
The Nodes corresponding integers
* NODE NAME ALIASES
* 1 = GND (33.499,-18.499)
* 2 = VDD (0.999,43.5) The generated parasitic capacitors
* 3 = VOUT (40.999,51.5)
(40 999 51 5)
* 4 = VIN (21.499,51.5) The generated two MOSFETs

Cpar1 2 0 7
7.800125f
800125f
Cpar2 3 0 7.73725f

M3 3 4 2 2 PMOS L=0.5u
L 0 5 W=2.5u
W 2 5 AD=5.9375p
AD 5 9375 PD=9.75u
PD 9 75 AS=6.25p
AS 6 25 PS=10u
PS 10
M4 3 4 1 1 NMOS L=0.5u W=1u AD=3.25p PD=8u AS=3.25p PS=8u

* Total Nodes: 4
* Total Elements: 4
* Extract Elapsed
p Time: 0 seconds
.END
49
 The modified SPICE file
* NODE NAME ALIASES
* 1 = GND (33.499,-18.499)
VG 1 0 DC 0
* 2 = VDD (0.999,43.5)
VDD 2 0 DC 3
* 3 = VOUT (40 (40.999,51.5)
999 51 5)
* 4 = VIN (21.499,51.5)
VIN 4 0 DC 0
.DC
DC VIN 0 3 0.1 01
.PROBE
Cpar1 2 0 7.800125f
Cpar2 3 0 7.73725f
7 73725f
M3 3 4 2 2 PMOS L=0.5u W=2.5u AD=5.9375p PD=9.75u AS=6.25p PS=10u
M4 3 4 1 1 NMOS L=0.5u W=1u AD=3.25p PD=8u AS=3.25p PS=8u
H
Here P
Paste
t th
the 0.5u
0 5 model
d l
* Total Nodes: 4
* Total Elements: 4
*EExtract Elapsed
El d Time:
Ti 0 seconds
d
.END 50
 0.5 µm NMOS SPICE MODEL
.MODEL NMOS NMOS ( LEVEL = 7
+VERSION = 3.1 TNOM = 27 TOX = 1.39E-8
+XJ = 1.5E-7 NCH = 1.7E17 VTH0 = 0.77269
+K1 = 0.7297494 K2 = -0.0506893 K3 = 31.4631363
+K3B = -11.2621866 W0 = 1E-8 NLX = 1E-9
+DVT0W = 0 DVT1W = 0 DVT2W = 0
+DVT0 = 1.806584 DVT1 = 0.4071509 DVT2 = -0.2695432
+U0 = 530.4792998 UA = 2.711027E-13 UB = 3.086214E-18
+UC = 6.526596E-11 VSAT = 9.92744E4 A0 = 0.5982151
+AGS = 0.1815599 B0 = 1.260889E-6 B1 = 1.247614E-6
+KETA = -9.95193E-3 A1 = 0 A2 = 1
+RDSW = 2.265793E3 PRWG = -0.0421807 PRWB = 0.0840864
+WR = 1 WINT = 2.28694E-7 LINT = 3.4243E-8
+XL = 0 XW = 0 DWG = -2.179541E-8
+DWB = -1.061163E-8 VOFF = -0.1276 NFACTOR = 1.601
+CIT = 0 CDSC = 2.4E-4 CDSCD = 0
+CDSCB = 0 ETA0 = 0.02354 ETAB = -1.35983E-3
+DSUB = 0.2295 PCLM = 1.4773229 PDIBLC1 = -0.3225681
+PDIBLC2 = 3.242849E-3 PDIBLCB = 3.28937E-3 DROUT = 0.3630621
+PSCBE1 = 5.88417E8 PSCBE2 = 1.020647E-4 PVAG = 0.3914131
+DELTA
DELTA = 0.01
0 01 MOBMOD = 1 PRT = 0
+UTE = -1.5 KT1 = -0.11 KT1L = 0
+KT2 = 0.022 UA1 = 4.31E-9 UB1 = -7.61E-18
+UC1 = -5.6E-11 AT = 3.3E4 WL = 0
+WLN = 1 WW = 0 WWN = 1
+WWL = 0 LL = 0 LLN = 1
+LW = 0 LWN = 1 LWL = 0
+CAPMOD = 2 XPART = 0.4 CGDO = 1.9E-10
+CGSO = 1.9E-10 CGBO = 1E-11 CJ = 4.266435E-4
+PB = 0.99 MJ = 0.4481178 CJSW = 3.152209E-10
+PBSW = 0.5007282
0 5007282 MJSW = 0.1339493
0 1339493 )

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 0.5 µm PMOS SPICE MODEL
MODEL PMOS PMOS ( LEVEL = 7
+VERSION = 3.1 TNOM = 27 TOX = 1.39E-8
+XJ = 1.5E-7 NCH = 1.7E17 VTH0 = -0.972531
+K1 = 0.5616782 K2 = 2.773863E-4 K3 = 12.7986171
+K3B = -0.4723902 W0 = 1E-8 NLX = 1E-9
+DVT0W = 0 DVT1W = 0 DVT2W = 0
+DVT0 = 0.811011 DVT1 = 0.188458 DVT2 = -0.1862226
+U0 = 364.2897131 UA = 6.556695E-9 UB = 2.005454E-19
+UC = -5.21416E-12 VSAT = 1.805928E5 A0 = 0.6916524
+AGS = 0.217888 B0 = 2.404098E-6 B1 = 5E-6
+KETA = -3.409663E-3 A1 = 0 A2 = 1
+RDSW = 2.846814E3 PRWG = -0.0499675 PRWB = -0.1304146
+WR = 1 WINT = 2.508674E-7 LINT = 1.459153E-8
+XL = 0 XW = 0 DWG = -2.24102E-8
+DWB = 2.268096E-8 VOFF = -0.1446 NFACTOR = 0.9027
+CIT = 0 CDSC = 2.4E-4 CDSCD = 0
+CDSCB = 0 ETA0 = 4.973E-3 ETAB = -3.342697E-3
+DSUB = 0.1147 PCLM = 3.1538098 PDIBLC1 = 0.6370303
+PDIBLC2 = 1.376041E-3 PDIBLCB = 0.2184 DROUT = 0.6256738
+PSCBE1 = 1.235615E10 PSCBE2 = 1.210011E-9 PVAG = 7.1862598
+DELTA = 0.01 MOBMOD = 1 PRT = 0
+UTE = -1.5 KT1 = -0.11 KT1L = 0
+KT2 = 0.022 UA1 = 4.31E-9 UB1 = -7.61E-18
+UC1 = -5.6E-11 AT = 3.3E4 WL = 0
+WLN = 1 WW = 0 WWN = 1
+WWL = 0 LL = 0 LLN = 1
+LW = 0 LWN = 1 LWL = 0
+CAPMOD = 2 XPART = 0.4 CGDO = 2.42E-10
+CGSO = 2.42E-10 CGBO = 1E-11 CJ = 7.303593E-4
+PB = 0.9569 MJ = 0.5047944 CJSW = 2.120694E-10
+PBSW = 0.8208359 MJSW = 0.1000002 )

52
Voltage Transfer Characteristics

53
Power Dissipation versus VIN

54
 Transient Analysis
„ Replace the DC source of VIN by a
p
pulse.

55
 Transient Analysis
In the spice file, replace
VIN 4 0 DC 0
.DC VIN 0 3 0.1

By:
VIN 4 0 Pulse ( 0 3 1p 1p 1p 0.5u 1u)
.TRAN
TRAN .02u
02u 2u

56
Transient Analysis

57
Transient Analysis

58
 Homework Assignments
1- Redo the design of the layout for CMOS inverter given the
following: L= 0.5µm, Wn= 1.5 µm, and Wp= 2.5 µm. Extract
to spice and plot the voltage transfer characteristics,
characteristics power
dissipaion versus VIN, Vout and VIN versus time and the
average
g ppower dissipation
p at 4 µ
µs ggiven the ppulse of 1µs
µ
period.

2- In the same file but in a new cell, draw the layout of the
2_inputs NAND gate that has the same speed of the inverter.
Extract to spice, apply two pulses as inputs, plot both inputs
versus time and Vout versus time to prove that your layout
really present 2_inputs
2 inputs NAND gate
gate.
59
 Stick Diagrams
Hint: VDD

Out

A B
GND

NAND22
NAND
60