VLSI

VLSI Testing
Testing
Fault
Fault Simulation
Simulation

Virendra Singh
Indian Institute of Science
Bangalore
virendra@computer.org

E0 286: Test & Verification of SoC Design

Lecture - 4
Jan 25, 2008 E0-286@SERC 1
 Fault
Fault Model
Model -- Summary
Summary
Fault models are analyzable approximations of
defects and are essential for a test
methodology.
For digital logic single stuck-at fault model
offers best advantage of tools and experience.
Many other faults (bridging, stuck-open and
multiple stuck-at) are largely covered by
stuck-at fault tests.
Stuck-short and delay faults and technology-
dependent faults require special tests.
Memory and analog circuits need other
specialized fault models and tests.

Jan 25, 2008 E0-286@SERC 2

 Fault Simulation

Jan 25, 2008 E0-286@SERC 3

 Simulation
Simulation Defined
Defined
„ Definition: Simulation refers to modeling of a
design, its function and performance.
„ A software simulator is a computer program;
an emulator is a hardware simulator.
„ Simulation is used for design verification:
„ Validate assumptions
„ Verify logic
„ Verify performance (timing)
„ Types of simulation:
„ Logic or switch level
„ Timing
„ Circuit
„ Fault

Jan 25, 2008 E0-286@SERC 4

 Simulation
Simulation for
for Verification
Verification

Specification

Synthesis

Response Design Design

analysis changes (netlist)

Computed True-value
Input stimuli
responses simulation

Jan 25, 2008 E0-286@SERC 5

 Modeling
Modeling Levels
Levels
Modeling Circuit Signal Timing Application
level description values
Architectural
Function, Programming 0, 1 Clock and functional
behavior, RTL language-like HDL boundary verification

Logic Connectivity of 0, 1, X Zero-delay Logic

Boolean gates, unit-delay, verification
and Z multiple-
flip-flops and and test
transistors delay

Switch Transistor size 0, 1 Zero-delay Logic

and connectivity, and X verification
node capacitances

Timing Transistor technology Analog Fine-grain Timing

data, connectivity, voltage timing verification
node capacitances
Circuit Continuous Digital timing
Tech. Data, active/ Analog
time and analog
passive component voltage,
circuit
connectivity current
verification
Jan 25, 2008 E0-286@SERC 6
 True-Value
True-Value Simulation
Simulation
Algorithms
Algorithms
™ Compiled-code simulation
¾ Applicable to zero-delay combinational logic
¾ Also used for cycle-accurate synchronous sequential
circuits for logic verification
¾ Efficient for highly active circuits, but inefficient for
low-activity circuits
¾ High-level (e.g., C language) models can be used
™ Event-driven simulation
¾ Only gates or modules with input events are
evaluated (event means a signal change)
¾ Delays can be accurately simulated for timing
verification
¾ Efficient for low-activity circuits
¾ Can be extended for fault simulation
Jan 25, 2008 E0-286@SERC 7
 Compiled-Code
Compiled-Code Algorithm
Algorithm

™ Step 1: Levelize combinational logic and

encode in a compilable programming language
™ Step 2: Initialize internal state variables (flip-
flops)
™ Step 3: For each input vector
Set primary input variables
Repeat (until steady-state or max. iterations)
¾ Execute compiled code
Report or save computed variables

Jan 25, 2008 E0-286@SERC 8

 Event-Driven
Event-Driven Algorithm
Algorithm
Scheduled Activity
events list
a =1 e =1 t=0 c=0 d, e
c =1 0 2
1
g =1
2
2 2 d = 1, e = 0 f, g
d=0

Time stack
3
4 f =0
b =1 4 g=0

5
g 6 f=1 g
0 4 8
Time, t 7

8 g=1
Jan 25, 2008 E0-286@SERC 9
 Time Wheel ((Circular
Time Wheel Stack))
Circular Stack

Current max
time t=0
pointer Event link-list
1

4
5
6
7

Jan 25, 2008 E0-286@SERC 10

 Efficiency
Efficiency of
of Event-
Event-
driven
driven Simulator
Simulator
Simulates events (value changes) only
Speed up over compiled-code can be ten
times or more; in large logic circuits about
0.1 to 10% gates become active for an input
change

Steady 0
Steady 0 Large logic
block without
(no event)
0 to 1 event activity

Jan 25, 2008 E0-286@SERC 11

 Problem
Problem and
and Motivation
Motivation
Fault simulation Problem: Given
¾ A circuit
¾ A sequence of test vectors
¾ A fault model
Determine
¾ Fault coverage - fraction (or percentage) of
modeled faults detected by test vectors
¾ Set of undetected faults
Motivation
¾ Determine test quality and in turn product quality
¾ Find undetected fault targets to improve tests

Jan 25, 2008 E0-286@SERC 12

 Fault
Fault simulator
simulator in
in a
a VLSI
VLSI
Design
Design Process
Process
Verified design Verification
netlist input stimuli

Fault simulator Test vectors

Modeled Remove Test Delete

fault list tested faults compactor vectors

Fault Low Test

coverage generator Add vectors
?
Adequate
Stop
Jan 25, 2008 E0-286@SERC 13
 Fault
Fault Simulation
Simulation Scenario
Scenario
Circuit model: mixed-level
™ Mostly logic with some switch-level for high-
impedance (Z) and bidirectional signals
™ High-level models (memory, etc.) with pin faults

Signal states: logic

™ Two (0, 1) or three (0, 1, X) states for purely
Boolean logic circuits
™ Four states (0, 1, X, Z) for sequential MOS circuits

Timing
™ Zero-delay for combinational and synchronous
circuits
™ Mostly unit-delay for circuits with feedback

Jan 25, 2008 E0-286@SERC 14

 Fault
Fault Simulation
Simulation Scenario
Scenario

Faults
™ Mostly single stuck-at faults
™ Sometimes stuck-open, transition, and path-delay
faults; analog circuit fault simulators are not yet in
common use
™ Equivalence fault collapsing of single stuck-at
faults
™ Fault-dropping -- a fault once detected is dropped
from consideration as more vectors are simulated;
fault-dropping may be suppressed for diagnosis
™ Fault sampling -- a random sample of faults is
simulated when the circuit is large

Jan 25, 2008 E0-286@SERC 15

 Fault
Fault Simulation
Simulation Algorithms
Algorithms
™ Serial

™ Parallel

™ Deductive

™ Concurrent

Jan 25, 2008 E0-286@SERC 16

 Serial
Serial Algorithm
Algorithm
Algorithm: Simulate fault-free circuit and save
responses. Repeat following steps for each
fault in the fault list:
™ Modify netlist by injecting one fault
™ Simulate modified netlist, vector by vector,
comparing responses with saved responses
™ If response differs, report fault detection and
suspend simulation of remaining vectors
Advantages:
™ Easy to implement; needs only a true-value
simulator, less memory
™ Most faults, including analog faults, can be
simulated

Jan 25, 2008 E0-286@SERC 17

 Serial
Serial Algorithm
Algorithm
¾ Disadvantage: Much repeated computation;
CPU time prohibitive for VLSI circuits
¾ Alternative: Simulate many faults together

Test vectors Fault-free circuit Comparator f1 detected?

Circuit with fault f1

Comparator f2 detected?
Circuit with fault f2

Comparator fn detected?
Circuit with fault fn

Jan 25, 2008 E0-286@SERC 18

 Parallel
Parallel Fault
Fault Simulation
Simulation
™ Compiled-code method; best with two-
states (0,1)
™ Exploits inherent bit-parallelism of logic
operations on computer words
™ Storage: one word per line for two-state
simulation
™ Multi-pass simulation: Each pass simulates
w-1 new faults, where w is the machine
word length
™ Speed up over serial method ~ w-1
™ Not suitable for circuits with timing-critical
and non-Boolean logic

Jan 25, 2008 E0-286@SERC 19

 Parallel
Parallel Fault
Fault Simulation
Simulation
Bit 0: fault-free circuit
Bit 1: circuit with c s-a-0
Bit 2: circuit with f s-a-1

1 1 1
c s-a-0 detected
a 1 0 1
1 1 1 1 0 1
b e 1 0 1
c s-a-0
g
0 0 0

d f s-a-1 0 0 1

Jan 25, 2008 E0-286@SERC 20

 Thank You

Jan 25, 2008 E0-286@SERC 21