VLSI

VLSI Testing
Testing
Yield
Yield Analysis
Analysis &
& Fault
Fault Modeling
Modeling

Virendra Singh
Indian Institute of Science
Bangalore
virendra@computer.org

E0 286: Test & Verification of SoC Design

Lecture - 2
 VLSI
VLSI Chip
Chip Yield
Yield
™ A manufacturing defect is a finite chip area with
electrically malfunctioning circuitry caused by errors
in the fabrication process.
™ A chip with no manufacturing defect is called a good
chip.
™ Fraction (or percentage) of good chips produced in a
manufacturing process is called the yield. Yield is
denoted by symbol Y.
™ Cost of a chip:
Cost of fabricating and testing a wafer
--------------------------------------------------------------------
Yield x Number of chip sites on the wafer

Jan 18, 2008 E0-286@SERC 2

 Clustered
Clustered VLSI
VLSI Defects
Defects

Good chips
Faulty chips

Defects
Wafer
Unclustered defects Clustered defects (VLSI)
Wafer yield = 12/22 = 0.55 Wafer yield = 17/22 = 0.77

Jan 18, 2008 E0-286@SERC 3

 Yield
Yield Parameters
Parameters
„ Defect density (d ) = Average number of defects per
unit of chip area
„ Chip area (A)
„ Clustering parameter (α)
„ Negative binomial distribution of defects,
p (x ) = Prob (number of defects on a chip = x )
Γ (α+x ) (Ad /α) x
= ------------- . ----------------------
x ! Γ (α) (1+Ad /α) α+x
where Γ is the gamma function
α = 0, p (x ) is a delta function (maximum clustering)
α = ∞ , p (x ) is Poisson distribution (no clustering)
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 Yield
Yield Equation
Equation

Y = Prob ( zero defect on a chip ) = p (0)

Y = ( 1 + Ad / α ) − α

Example: Ad = 1.0, α = 0.5, Y = 0.58

- Ad
Unclustered defects: α = ∞, Y = e

Example: Ad = 1.0, α = ∞, Y = 0.37

too pessimistic !
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 Defect
Defect Level
Level or
or Reject
Reject Ratio
Ratio

™ Defect level (DL) is the ratio of faulty chips

among the chips that pass tests.
™ DL is measured as parts per million (ppm).
™ DL is a measure of the effectiveness of tests.
™ DL is a quantitative measure of the manufactured
product quality. For commercial VLSI chips a DL
greater than 500 ppm is considered
unacceptable.

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 Determination
Determination of
of DL
DL

™ From field return data: Chips failing in the field

are returned to the manufacturer. The number of
returned chips normalized to one million chips
shipped is the DL.
™ From test data: Fault coverage of tests and chip
fallout rate are analyzed. A modified yield model
is fitted to the fallout data to estimate the DL.

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 Modified
Modified Yield
Yield Equation
Equation
„ Three parameters:
¾Fault density, f = average number of stuck-at
faults per unit chip area
¾Fault clustering parameter, β
¾Stuck-at fault coverage, T
„ The modified yield equation:

Y (T ) = (1 + TAf / β) - β
Assuming that tests with 100% fault coverage
(T =1.0) remove all faulty chips,

Y = Y (1) = (1 + Af / β) - β

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 Defect
Defect Level
Level
Y (T ) - Y (1)
DL (T ) = --------------------
Y (T )

β
( β + TAf )
= 1 - --------------------
β
( β + Af )
Where T is the fault coverage of tests, Af is the
average number of faults on the chip of area A, β
is the fault clustering parameter. Af and β are
determined by test data analysis.

Jan 18, 2008 E0-286@SERC 9

 Yield
Yield and
and Fault
Fault Coverage
Coverage

30
25
Defect Level

20
15
10
5
0
0 10 20 30 40 50 60 70 80 90 100
Fault Coverage
Jan 18, 2008 E0-286@SERC 10
 Computed
Computed DL
DL
237,700 ppm (Y = 76.23%)
Defect level in ppm

Stuck-at fault coverage (%)

SEMATECH Chip (Courtesy: IBM)

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 Revenues
Time
Time to
to Market
Market

Loss of
Revenues

Time to
Time in Months
Market ΔT
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 Failure Rate Vs Product Lifetime

Infant
Mortality Working Life Span Wearout
Failure Rate

1-20 weeks 10-20 years

Product Life Time

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 Definitions
Definitions

™ Defect: A defect in an electronic system is

the unintended difference between the
implemented hardware and its intended
design

™ Error: A wrong output signal produced by

defective system is called error. An error is
an effect whose cause is some defect

™ Fault: A representation of a defect at the

abstracted function level is called a fault

Jan 18, 2008 E0-286@SERC 14

 Why
Why Model
Model Faults?
Faults?

™ I/O function tests inadequate for

manufacturing (functionality versus
component and interconnect testing)
™ Real defects (often mechanical) too
numerous and often not analyzable
™ A fault model identifies targets for testing
™ A fault model makes analysis possible
™ Effectiveness measurable by experiments

Jan 18, 2008 E0-286@SERC 15

 Some
Some Real
Real Defects
Defects in
in Chips
Chips
™ Processing defects
¾ Missing contact windows
¾ Parasitic transistors
¾ Oxide breakdown
¾ . . .
™ Material defects
¾ Bulk defects (cracks, crystal imperfections)
¾ Surface impurities (ion migration)
¾ . . .
™ Time-dependent failures
¾ Dielectric breakdown
¾ Electromigration
¾ . . .
™ Packaging failures
¾ Contact degradation
¾ Seal leaks
¾ . . .

Ref.: M. J. Howes and D. V. Morgan, Reliability and Degradation -

Semiconductor Devices and Circuits, Wiley, 1981.
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 Electromigration

(a)

(b)

(c)

(a) Open in a line

(b) Short between two lines (whisker)
(c) Short between lines on different layers (hillock)

Jan 18, 2008 E0-286@SERC 17

 Mapping Physical Defect into
Faults 1

RL Z
B
A Z
A
R1
A Z
R2 B Z
A (b)
(a)

™ Both the defective resistance in bipolar

and a the oxide breakdown in oxide
between the source and drain of the NMOS
transistor form a short failure mode
™ Both cases are mapped into a stuck-at
fault
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 Mapping Physical Defect into
Faults 2

A
A
A
Z Z Z

Poly Metal Diffusion

¾ Physical defect: A missing metal

o NMOS is missing the gate
¾ Failure mode: an open
¾ Fault: open
¾ A possible circuit representation is shown
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 Mapping Physical Defect into
Faults 3
L1 L1

L2 L2

(a) (b)

Stuck-at 1 Stuck-at 0
Vdd GND
(c)

Bridging Fault
(d)

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 Observed
Observed PCB
PCB Defects
Defects
Defect classes Occurrence frequency (%)

Shorts 51
Opens 1
Missing components 6
Wrong components 13
Reversed components 6
Bent leads 8
Analog specifications 5
Digital logic 5
Performance (timing) 5

Ref.: J. Bateson, In-Circuit Testing, Van Nostrand Reinhold, 1985.

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 Failure Classification
IC Failures

M ode D uration

Incorrect D esign Perm anant

H ard
Param eter D egradation
Tem poraty
Soft

Transient

Interm ittent

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 Common
Common Fault
Fault Models
Models

Single stuck-at faults

Transistor open and short faults
Memory faults
PLA faults (stuck-at, cross-point, bridging)
Functional faults (processors)
Delay faults (transition, path)
Analog faults

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 Single
Single Stuck-at
Stuck-at Fault
Fault
™ Three properties define a single stuck-at fault
Only one line is faulty
The faulty line is permanently set to 0 or 1
The fault can be at an input or output of a gate
™ Example: XOR circuit has 12 fault sites ( ) and
24 single stuck-at faults
Faulty circuit value
Good circuit value
c j
s-a-0 0(1)
a d 1(0)
1 g h
z
0 1 i
b e 1

f k
Test vector for h s-a-0 fault
Jan 18, 2008 E0-286@SERC 24