VLSI

VLSI Testing
Testing
Fault
Fault Simulation
Simulation

Virendra Singh
Indian Institute of Science
Bangalore
virendra@computer.org

E0 286: Test & Verification of SoC Design

Lecture - 5
Jan 28, 2008 E0-286@SERC 1
 Problem
Problem and
and Motivation
Motivation
Fault simulation Problem: Given
¾ A circuit
¾ A sequence of test vectors
¾ A fault model
Determine
¾ Fault coverage - fraction (or percentage) of
modeled faults detected by test vectors
¾ Set of undetected faults
Motivation
¾ Determine test quality and in turn product quality
¾ Find undetected fault targets to improve tests

Jan 28, 2008 E0-286@SERC 2

 Parallel
Parallel Fault
Fault Simulation
Simulation
™ Compiled-code method; best with two-
states (0,1)
™ Exploits inherent bit-parallelism of logic
operations on computer words
™ Storage: one word per line for two-state
simulation
™ Multi-pass simulation: Each pass simulates
w-1 new faults, where w is the machine
word length
™ Speed up over serial method ~ w-1
™ Not suitable for circuits with timing-critical
and non-Boolean logic

Jan 28, 2008 E0-286@SERC 3

 Parallel
Parallel Fault
Fault Simulation
Simulation
Bit 0: fault-free circuit
Bit 1: circuit with c s-a-0
Bit 2: circuit with f s-a-1

1 1 1
c s-a-0 detected
a 1 0 1
1 1 1 1 0 1
b e 1 0 1
c s-a-0
g
0 0 0

d f s-a-1 0 0 1

Jan 28, 2008 E0-286@SERC 4

 Deductive
Deductive Fault
Fault Simulation
Simulation
™ One-pass simulation
™ Each line k contains a list Lk of faults
detectable on k
™ Following true-value simulation of each
vector, fault lists of all gate output lines
are updated using set-theoretic rules,
signal values, and gate input fault lists
™ PO fault lists provide detection data
™ Limitations:
„ Set-theoretic rules difficult to derive for non-
Boolean gates
„ Gate delays are difficult to use

Jan 28, 2008 E0-286@SERC 5

 Deductive
Deductive Fault
Fault Simulation
Simulation

Notation: Lk is fault list for line k

kn is s-a-n fault on line k

1 {a0} Le = La U Lc U {e0}
a = {a0 , b0 , c0 , e0}
1 {b0 , c0}
b e 1
{b0} c 1
g
d f 0
Lg = (Le Lf ) U {g0}
U
{b0 , d0}
{b0 , d0 , f1} = {a0 , c0 , e0 , g0}
Faults detected by
the input vector

Jan 28, 2008 E0-286@SERC 6

 Concurrent
Concurrent Fault
Fault Simulation
Simulation
™ Event-driven simulation of fault-free circuit and
only those parts of the faulty circuit that differ in
signal states from the fault-free circuit.
™ A list per gate containing copies of the gate from
all faulty circuits in which this gate differs. List
element contains fault ID, gate input and output
values and internal states, if any.
™ All events of fault-free and all faulty circuits are
implicitly simulated.
™ Faults can be simulated in any modeling style or
detail supported in true-value simulation (offers
most flexibility.)
™ Faster than other methods, but uses most
memory.
Jan 28, 2008 E0-286@SERC 7
 Conc.
Conc. Fault
Fault Simulation
Simulation
a0 b0 c0 e0
0 1 1 1
0 0 0 0
1 0 0 1
1
a 1 1
1 1
b 1 e 1
c 1
1 g
0
0

d
1 0
f a0 b c0 e0
0 0 0 0 0
0 1 0 0
0 1 0 0

1 1 1
0 1 1
b0 d0 f1 0
g0 1 1
d0
0 1
f1
0 1 1 1

Jan 28, 2008 E0-286@SERC 8

 Fault
Fault Sampling
Sampling

„ A randomly selected subset (sample) of

faults is simulated.
„ Measured coverage in the sample is used
to estimate fault coverage in the entire
circuit.
„ Advantage: Saving in computing resources
(CPU time and memory.)
„ Disadvantage: Limited data on undetected
faults.

Jan 28, 2008 E0-286@SERC 9

 Motivation
Motivation for
for Sampling
Sampling

„ Complexity of fault simulation depends on:

„ Number of gates
„ Number of faults
„ Number of vectors
„ Complexity of fault simulation with fault
sampling depends on:
„ Number of gates
„ Number of vectors

Jan 28, 2008 E0-286@SERC 10

 Random
Random Sampling
Sampling Model
Model
Detected Undetected
fault fault

All faults with

a fixed but Random
unknown picking
coverage

Np = total number of faults Ns = sample size

(population size) Ns << Np
C = fault coverage (unknown) c = sample coverage
(a random variable)

Jan 28, 2008 E0-286@SERC 11

 Probability
Probability Density
Density of
of
Sample
Sample Coverage,
Coverage, cc
(x--C )2
-- ------------
1 2σ 2
p (x ) = Prob(x < c < x +dx ) = -------------- e
σ (2 π) 1/2

2 C (1 - C)
Variance, σ = ------------
Ns Sampling
p (x )

σ σ
error
Mean = C

x
C -3σ C x C +3σ 1.0
Sample coverage
Jan 28, 2008 E0-286@SERC 12
 Fault
Fault simulator
simulator in
in a
a VLSI
VLSI
Design
Design Process
Process
Verified design Verification
netlist input stimuli

Fault simulator Test vectors

Modeled Remove Test Delete

fault list tested faults compactor vectors

Fault Low Test

coverage generator Add vectors
?
Adequate
Stop
Jan 28, 2008 E0-286@SERC 13
 Thank You

Jan 28, 2008 E0-286@SERC 14