VLSI Testing

Delay Test

Virendra Singh
Indian Institute of Science
Bangalore
virendra@computer.org

E0286: Testing and Verification of SoC Designs

Lecture 22
Mar 24, 2008 E0286@SERC 1
 Definitions
™Controlling value (cv) : An input of a gate
is said to have a controlling value if it
uniquely determines the output of the gate
independent of other inputs
¾For example, 0 for AND or NAND

™A path R in a circuit is a sequence

(g0g1……gr), where g0 is a PI, g1g2.. are
gate outputs, gr is a PO
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 Definitions
™An on-input of path R is a connection
between two gates along path R

™A side-input (off-input) of path R is any

connection to a gate along path R other than
its on-input

™A path that starts at a primary input and ends

at a side-input of path R is called a side-path
of R
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 Transition Delay Fault

¾Two faults per gate; slow-to-rise and

slow-to-fall.
¾Tests are similar to stuck-at fault tests.
For example, a line is initialized to 0 and
then tested for s-a-0 fault to detect slow-
to-rise transition fault.
¾Models spot (or gross) delay defects.

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 Transition Delay Test

Path P1
1

D’ 1
D’

P2 1
1
D
1 D’ D’
2 3
SA0 P3
1

Mar 24, 2008 E0286@SERC 5

 Transition Delay Test
Single lumped inertial delay modeled for each gate
PI transitions assumed to occur without time skew

Path P1
0

D’ 1
0

D
P2 1

D
1 D’ D’
2 3
SA0 P3
1

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 Transition Delay Test

Path P1
X0

0D’ 1
00

1D
P2 1

1D
01 0D’ 0D’
2 3
SA0 P3
01

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 Path Delay Fault

Cheng’s classification
¾Robustly testable
¾Non-robustly (NR) testable
¾Functional sensitizable (FS) testable
¾Functionally unsensitizable
(functionally redundant)

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 Path Delay Fault
Robust testable : detect target PDF
independent of delays in rest of the circuit.
™It must satisfies the following conditions
¾It launches the desired transition at primary
input
¾All side inputs of target path settle to non-
controlling values under V2
¾Whenever the logic transition at an on-input
is from non-controlling to controlling value
(ncv to cv), each side-input should maintain
steady non-controlling value (ncv)
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 Path Delay Fault

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 Path Delay Fault
Non-Robust (NR ) testable :
™It must satisfies the following conditions
¾It launches the desired transition at primary
input
¾All side-inputs of target path settle to non-
controlling values (ncv) under V2

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 Path Delay Fault
Functional Sensitizable (FS) testable:
™ Detection of faults on paths that are sensitizable
under FS criterion depends on the delays on
signals outside the target path
™ It must satisfies the following conditions
¾It launches the desired transition at primary
input
¾Whenever the logic transition at an on-input
is non-controlling value (ncv) under vector
V2, each side-input should have non-
controlling value (ncv) under V2
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 Path Delay Fault

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 Path Delay Fault
™Functionally unsensitizable

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 Path Delay Fault

On-input Side-inputs testability

cv -> ncv Stable cv Untestable
Stable ncv Robust
cv -> ncv
ncv -> cv Untestable
ncv -> cv Stable cv Untestable
Stable ncv Robust
cv -> ncv NR
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ncv -> cv FS
 Thank You

Mar 24, 2008 E0286@SERC 16