library ieee;

use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity segundo is
port ( pulso : inout std_logic:='0';
clk : in std_logic);

end entity;

architecture divisor of segundo is

signal count : integer :=1;
begin
process(clk) begin
if(clk'event and clk='1') then
count <=count+1;
if(count = 50000000) then --count = frec de reloj/frec
deseada
PULSO <= not PULSO;
count <=1;
end if;
end if;
end process;

end architecture;