FF_JK.

vhdl

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity FF_JK is
port(
j,k,p,r,clk : in bit;
q,qp : out bit
);
end FF_JK;

architecture behavior of FF_JK is

signal s : bit;
begin
process (p,r,clk)
begin
if p='1' then
s<='1';
elsif r='1' then
s<='0';
elsif clk='0' and clk' event then
if j='1' and k='1' then
s <= not s;
elsif j='1' and k='0' then
s <='1';
elsif j='0' and k='1' then
s <='0';
elsif j='0' and k='0' then
s <= s;
end if;
end if;
end process;
q <= s;
qp <= not s;
end behavior;

FF_JK_tb.vhdl

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity FF_JK_tb is
end FF_JK_tb;

architecture test of FF_JK_tb is

component FF_JK
 port(
j,k,p,r,clk : in bit;
q,qp : out bit
);
end component;
signal j,k,p,r,q,qp,clk : bit;
begin
ffjk1 : FF_JK port map(j=>j,k=>k,p=>p,r=>r,q=>q,qp=>qp,clk=>clk);
process
begin
j<='1';
k<='0';
p<='0';
r<='1';
clk<='1';
wait for 10 fs;

j<='1';
k<='0';
p<='0';
r<='0';
clk<='0';
wait for 10 fs;

j<='1';
k<='0';
p<='0';
r<='0';
clk<='1';
wait for 10 fs;

j<='1';
k<='1';
p<='0';
r<='0';
clk<='0';
wait for 10 fs;

j<='0';
k<='0';
p<='0';
r<='0';
clk<='1';
wait for 10 fs;

clk<='0';
wait for 10 fs;

j<='1';
 k<='1';
p<='0';
r<='0';
clk<='1';
wait for 10 fs;

clk<='0';
wait for 10 fs;

j<='1';
k<='0';
p<='1';
r<='0';
clk<='1';
wait for 10 fs;

j<='0';
k<='1';
p<='0';
r<='0';
clk<='0';
wait for 10 fs;

assert false report "Reached end of test";

wait;

end process;

end test;

FF_D.vhdl

library ieee;
use ieee.std_logic_1164.all;

entity FF_D is
port(
clk, d,p,r : in bit;
q,nq : out bit
);

end FF_D;

architecture behavior of FF_D is

component FF_JK
port(
j,k,p,r,clk : in bit;
q,qp : out bit
);
end component;
signal a0 : bit;
begin
a0<= not d;
ffjk1: FF_JK port map(d,a0,p,r,clk,q,nq);

end behavior;

FF_D_tb.vhdl

library ieee;
use ieee.std_logic_1164.all;

entity FF_D_tb is

end FF_D_tb;

architecture test of FF_D_tb is

component FF_D
port(
clk, d,p,r : in bit;
q,nq : out bit
);

end component;
signal clk,d,p,r,q,nq : bit;
begin
ffD: FF_D port map(clk=>clk,d=>d,p=>p,r=>r,q=>q,nq=>nq);
process
begin
for i in 0 to 30 loop
 clk<='0';
wait for 10 fs;
clk<='1';
wait for 10 fs;
end loop;
assert false report "Reached end of test";
wait;
end process;
process
begin
wait for 215 fs;
d<='1';
wait for 40 fs;
d<='0';

wait;
end process;
end test;

FF_T.vhdl

library ieee;
use ieee.std_logic_1164.all;

entity FF_T is
port(
clk, t,p,r : in bit;
q,nq : out bit
);
end FF_T;

architecture behavior of FF_T is

component FF_JK
port(
j,k,p,r,clk : in bit;
q,qp : out bit
);
end component;
signal a0 : bit;
begin
a0<= t;
ffjk1: FF_JK port map(t,a0,p,r,clk,q,nq);

end behavior;

FF_T_tb.vhdl

library ieee;
use ieee.std_logic_1164.all;

entity FF_T_tb is

end FF_T_tb;

architecture test of FF_T_tb is

component FF_T
port(
clk, t,p,r : in bit;
q,nq : out bit
);

end component;
signal clk,t,p,r,q,nq : bit;
begin
ffD: FF_T port map(clk=>clk,t=>t,p=>p,r=>r,q=>q,nq=>nq);
process
begin
for i in 0 to 30 loop
clk<='0';
wait for 10 fs;
clk<='1';
wait for 10 fs;
end loop;
assert false report "Reached end of test";
wait;
 end process;
process
begin
wait for 15 fs;
t<='1';
wait for 20 fs;
t<='0';

wait for 15 fs;

t<='1';
wait for 20 fs;
t<='0';
wait for 15 fs;
t<='1';
wait for 20 fs;
t<='0';
wait for 15 fs;
t<='1';
wait for 20 fs;
t<='0';
wait for 15 fs;
t<='1';
wait for 20 fs;
t<='0';
wait;
end process;
end test;
Cont_a_250.vhdl
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity cont_a_250 is
port (
clk,res : in bit;
q: out signed(7 downto 0)
);
end cont_a_250;

architecture behavior of cont_a_250 is

signal qs,e: signed(7 downto 0);

begin
process (clk)
begin
if clk' event and clk='0' then
if res='1' then
qs<="00000000";
else
qs<=e;
end if;
end if;
end process;
e<="00000000" when qs="11111010" else
qs+1;

q<=qs;

end behavior;

cont_a_250_tb.vhdl

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity cont_a_250_tb is
end cont_a_250_tb;

architecture test of cont_a_250_tb is

component cont_a_250
port (
clk,res : in bit;
q: out signed(7 downto 0)
);
end component;
signal clk : bit := '0';
signal res : bit := '0';
signal q : signed(7 downto 0);
begin
contador: cont_a_250 port map(clk=>clk,res=>res,q=>q);
process
begin
res<='1';
wait for 25 fs;
res<='0';
assert false report "Reached end of test";
wait;
end process;
process
begin
for i in 0 to 1500 loop
clk<='0';
wait for 10 fs;

clk<='1';
wait for 10 fs;
end loop;

assert false report "Reached end of test";

wait;
end process;

end test;
Cont_d_264.vhdl

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity cont_d_264 is
port (
clk,res : in bit;
q: out signed(8 downto 0)
);
end cont_d_264;

architecture behavior of cont_d_264 is

signal qs,e: signed(8 downto 0);

begin
process (clk)
begin
if clk' event and clk='0' then
if res='1' then
qs<="100001000";

else
qs<=e;
end if;
end if;
end process;
e<="100001000" when qs="000000000"else
qs-1;

q<=qs;
end behavior;

cont_d_24_tb.vhdl

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity cont_d_264_tb is
end cont_d_264_tb;

architecture test of cont_d_264_tb is

component cont_d_264
port (
clk,res : in bit;
q: out signed(8 downto 0)
);
end component;
signal clk : bit := '0';
signal res : bit := '0';
signal q : signed(8 downto 0);
begin
contador264: cont_d_264 port map(clk=>clk,res=>res,q=>q);
process
begin
res<='1';
wait for 25 fs;
res<='0';
assert false report "Reached end of test";
wait;
end process;
process
begin
for i in 0 to 1500 loop
clk<='0';
wait for 10 fs;

clk<='1';
wait for 10 fs;
end loop;

assert false report "Reached end of test";

wait;
end process;
end test;