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C 5 MSI PLD C: Hapter AND Omponents
C 5 MSI PLD C: Hapter AND Omponents
Introduction
Inputs
Outputs
x y z D0 D1 D2 D3 D4 D5 D6 D7
00
0 1 0 0 0 0 0 0 0
0 0 1 0 1 0 0 0 0 0 0
0 1 0 0 0 1 0 0 0 0 0
0 1 1 0 0 0 1 0 0 0 0
1 0 0 0 0 0 0 1 0 0 0
1 0 1 0 0 0 0 0 1 0 0
1 1 0 0 0 0 0 0 0 1 0
1 1 1 0 0 0 0 0 0 0 1
x y z C S
0 0 0 0 0
0 0 1 0 1
0 1 0 0 1
0 1 1 1 0
1 0 0 0 1
1 0 1 1 0
1 1 0 1 0
1 1 1 1 1
- Since there are 3 inputs and total of 8 minterms, we need a 3-to-line decoder.
- Figure 5 – 9 shows the implementation of a full-adder with a decoder.
- The OR gate for output S forms the sum of minterms 1, 2, 4, and 7.
- The OR gate for output C forms the sum of minterms 3, 5, 6, and 7.
Demultiplexers
- It is a circuit that receives information on a single line and transmits this information
on one of 2n possible output lines.
- The selection of a specific output line is controlled by the bit values of n selected
lines.
- Most IC decoders include one or more enable inputs to control the circuit operation.
- A 2-to-4-line decoder with an enable input constructed with NAND gates is in Fig. 5 –
10, Page 169.
- All outputs are equal to 1 if enable input E is 1, regardless of the values of inputs A
and B.
- When the enable input is 0, the circuit operates as a decoder with complemented
outputs.
- The X’s under the A and B are don’t-care conditions.
- Normal decoder operation occurs only when E = 0, and the outputs are selected
when they are in the 0 state.
Truth Table
E A B D0 D1 D2 D3
1 X X 1 1 1 1
0 0 0 0 1 1 1 D0 = 0, complemented outputs
0 0 1 1 0 1 1 D1 = 0,
0 1 0 1 1 0 1 D2 = 0,
0 1 1 1 1 1 0 D3 = 0,
- If the selection lines AB = 10, output D2 will be the same input value as E,
all other outputs are maintained at 1.
- A decoder with an enable input is referred to as a decoder/demultiplexer because
they are obtained from the same circuit.
- It is the enable input that makes the circuit a demultiplexer.
- Decoder/demultiplexer circuits can be connected together to form a large decoder
ciruit.
Encoders
- It is a digital circuit that performs the inverse operation of a decoder.
- An encoder has 2n (or fewer) input lines and n output lines.
- The output lines generate the binary code corresponding to the input value.
- Example: An encoder of an octal-to-binary truth table is as follows:
- It has eight inputs, one for each of the octal digits, and three outputs that generate
the corresponding binary numbers.
Truth Table of Octal-to-Binary Encoder
Inputs Outputs
D0 D1 D2 D3 D4 D5 D6 D7 x y z
10
0 0 0 0 0 0 0 0 0
0 1 0 0 0 0 0 0 0 0 1
0 0 1 0 0 0 0 0 0 1 0
0 0 0 1 0 0 0 0 0 1 1
0 0 0 0 1 0 0 0 1 0 0
0 0 0 0 0 1 0 0 1 0 1
0 0 0 0 0 0 1 0 1 1 0
0 0 0 0 0 0 0 1 1 1 1
- It is assumed that only one input has a value of 1 at any given time.
- It is implemented with OR gates whose inputs are determined directly from the truth
table.
- When input is 1, 3, 5, 7 output z = 1.
- When input is 2, 3, 6, 7 output y = 1.
- When input is 4, 5, 6, 7 output x = 1.
- Then the Boolean functions are:
z = D1 + D3 + D5 + D7
y = D2 + D3 + D6 + D7
x = D4 + D5 + D6 + D7
- See Fig. 5 –13 Page 171.
- Only one input can be active at any given time. If two inputs are active
simultaneously, the output produces an undefined combination.
- Priority order solves the problem. If both D3 and D7 are at the same time, the output
will be 111 because D7 has higher priority than D3.
Multiplexers
-
Multiplexing means transmitting a large number of information units over a smaller
number of channels or lines. It is abbreviated as MUX.
-
A digital multiplexer is a combinational circuit that selects binary information from
one of many input lines and directs it to a single output line.
-
There are 2n input lines and n selection lines whose bit combinations determine
which input is selected.
-
A 4-to-1-line is in Fig. 5 –16 Page 174. Each of the four input lines, I0 to I3, is applied
to one input of an AND gate.
-
Selection lines s1 and s0 are decoded to select a particular AND gate.
-
The table lists the input-to-output path for each possible bit combination of the
selection lines.
Function Table
s1 s0 Y
0 0 I0
0 1 I1
1 0 I2
1 1 I3
-
Fig. 5 – 16 (c), shows the MSI function that is used in the
design of a digital system.
-
Ex:
If s1 s0 = 10, then AND gate is associated with input I2 has two of its inputs equal to 1
and the third input is connected to I2.
The other three AND gates have at least one input equal to 0, which makes their
outputs equal to 0.
The OR gate output is now equal to the value of I2, thus providing a path from the
selected input to the output.
-
A multiplexer is also called a data selector, since it selects one of many inputs and
steers the binary information to the output line.
-
A 2n-to-1-line MUX is constructed from an n-to-2n decoder by adding to it 2n input
lines, one to each AND gate.
-
The output of the AND gates are applied to a single OR gate to provide the 1-line
output.
-
It is then implied that it also contains n selection lines.
-
A MUX may have an enable input to control the operation of the unit.
-
When the enable unit is in a given binary state, the outputs are disabled. The
enable input sometimes called strobe, which can be used to expand two or more
multiplexers to a digital multiplexer with a large number of inputs.
Ex:Design a combinational circuit using a ROM. The circuit accepts a 3-bit number and
generates an output binary number equal to the square of the input square.
Inputs
Outputs
A2 A1 A0 B5 B4 B3 B2 B1 B0 Decimal
0
0 0 0 0 0 0 0 0 0
0 0 1 0 0 0 0 0 1 1
0 1 0 0 0 0 1 0 0 4
0 1 1 0 0 1 0 0 1 9
1 0 0 0 1 0 0 0 0 16
1 0 1 0 1 1 0 0 1 25
1 1 0 1 0 0 1 0 0 36
1 1 1 1 1 0 0 0 1 49
A2 A1 A0 F1 F2 F3 F4
0 0 0 0 0 0
0
0 0 1 0 0 0 0
0 1 0 0 0 0 1
0 1 1 0 0 1 0
1 0 0 0 1 0 0
1 0 1 0 1 1 0
1 1 0 1 0 0 1
1 1 1 1 1 0 0
00 01 11 10
0 1
1 1 1 1
F1 = AC + AB + BC
00 01 11 10
0 1 1
1 1 1
F2 = B’C’ + A’C’ + ABC
00 01 11 10
0 0 0 0
1 0
F’1 = B’C’ + A’C’ + A’B’
00 01 11 10
0 0 0
1 0 0
F’2 = B’C + A’C + ABC
C C
00 01 11 10
00 1
01 B
A 11 1 1 B
A 10
D D
w = ABC’ + A’B’CD’
C C
00 01 11 10
00
01 1 B
A 11 1 1 1 1 B
A 10 1 1 1 1
D D
x = A + BCD
C C
00 01 11 10
00 1 1 1
01 1 1 1 1 B
A 11 1 B
A 10 1 1 1
D D
y = A’B + CD + B’D’
C C
00 01 11 10
00 1 1
01 B
A 11 1 1 B
A 10 1
D D
z = ABC’ + A’B’CD’ + AC’D’ + A’B’C’D’
= w + AC’D’ + A’B’C’D
- The table below shows the PAL programmable table for the 4 Boolean functions.
1 1 1 0 - - w = ABC’
2 0 0 1 0 - + A’B’CD’
3 - - - - -
4 1 - - - - x=A
5 - 1 1 1 - + BCD
6 - - - - -
7 0 1 - - - y = A’B’
8 - - 1 1 - + CD
9 - 0 - 0 - + B’D’
10 - - - - 1 z=w
11 1 - 0 0 - + AC’D’
12 0 0 0 1 - + A’B’C’D
- The table is divided into 4 sections with three products in each.
- The first two sections need only two product terms to implement the Boolean
function.
- The last two sections need three product terms. (Function w was reduced to 3
terms.)
- The fuse map is shown in Fig. 5 – 31.
- For each 1 or 0 in the table, we mark the corresponding intersection in the diagram
with the symbol for an intact fuse.
- For each dash, we mark the diagram with blown fuses in both the true and
complement inputs.
- If the AND gates is not used, we leave its input fuses intact.