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PLL PDF
PLL PDF
Nagendra Krishnapura
1610kHz
fc
530kHz
88MHz
88.2MHz
108MHz
5kHz
channel channel
spacing spacing
0.2MHz 0.2MHz
GSM uplink band GSM downlink band
890MHz
935MHz
890.2MHz
935.2MHz
915MHz
960MHz
Tuned to the desired channel frequency plus an
intermediate frequency (IF)
Generate equally spaced frequencies from a reference
frequency
Waveform shape not very important
Spurious output and noise must be sufficiently low
Nagendra Krishnapura Phase locked loop frequency synthesizers
Frequency divider
Vref
R(N-1)
fref fref/N
Vref/N N
R frequency
divider
R(N-1)
frequency difference
zero, at steady state
cos(2πfreft) fref Vctl KvcoVctl+fo
frequency cos(2πfoutt) slope = Kvco
measure + Σ K2 dt
fout
-
fout/N fo
frequency
measure N
Vctl
cos(2πfout/N t)
Sinusoid: cos(θ(t))
Phase: θ(t)
1 dθ(t)
Instantaneous frequency: fi = 2π dt
Typically expressed as fi = fo + fe (t)
fo : average frequency
fe : instantaneous frequency error
R
Phase θ(t) = 2πfo t + Φo + 2π fe (t)dt
Phase θ(t) = 2πfo t + Φo + φ(t)
Φo : phase offset-ideal ramp versus time
φ(t): instantaneous phase
50
40
30
20
10
−10
0 2 4 6 8 10
dt
K2
fout/N = fref at steady state fout/N
frequency
measure N
cos(2πfout/N t)
Vctl = Kpd(φref-φout/N)
cos(2πfout/N t + φout/N)
fout/N = fref at steady state
Vctl
2πfot
Vctl + θvco
+
2πKvco dt Σ
φ1 Kpd(φ1-φ2)
phase
φ2 detector
Kpd: phase detector gain
Kpd : Phase detector gain in V/radian
Ideal phase detector: assumed to have an output
Vpd = Kpd (φ1 − φ2 )
2πfout/N t+Φvco/N
1/N
2πfot
1/N
2πfout/N t+Φout/N+φout/N
φout/N
1/N
φout(s)/N
1/N
1 QA
A A D Q
A
ref RST
B -1 0 +1 A
B RST
div
QB
B B 1
D Q
output=QA-QB
Tref Tref
+1 +1
A -1
A -1
+1 +1
B B
-1 -1
+1 +1
QA QA
+1 +1
QB QB
Φref-Φdiv Φdiv-Φref
A leading B A lagging B
1 QA
A A D Q
A
ref RST
B -1 0 +1 A
B RST
div
QB
B B 1
D Q
output=QA-QB
+1
pdout Average value = ∆Φ/π
-1 Tref Output periodic at fref
∆Φ = Φref-Φdiv
∞
∆Φ X n∆Φ
Vout (f ) = sinc δ(f − nfref )
2π n=−∞ 2π
∞
∆Φ ∆Φ X n∆Φ
Vout (t) = + sinc cos(2πnfref t)
2π π 2π
n=1
0.4
0.2
−0.2
0 2 4 6 8 10
∆Φ=π/8
0.5
−0.5
0 2 4 6 8 10
f/fref
φvco/N
1/N
50
40
30
20
10
−10
0 2 4 6 8 10
φvco(s)/N
1/N
Loop gain
2πKpd Kvco
L(s) =
Ns
Closed loop bandwidth (Hz)
Kpd Kvco
f−3dB =
N
Nagendra Krishnapura Phase locked loop frequency synthesizers
Type I PLL
dB
2πKpdKvco/N
ω
L/(1+L)
|φout/φref|
dB
20log(N)
ω
2πKpdKvco/N
(loop bandwidth)
In our system,
L(s)
Hclosedloop (s) = Hideal (s)
1 + L(s)
Where Hideal (s) is the ideal closed loop gain (with L = ∞). This
can be approximated as
b1 = a1 |H(j2πfref )|
Kpd Kvco /jNfref
= a1 N
1 + Kpd Kvco /jNfref
Kpd Kvco
≈ a1 N
jNfref
Nf−3dB ∆Φ
= 2∆Φ sinc
fref 2π
frequency
divider
Voff
Vctl (ffree+KvcoVoff)+KvcoVctl Vctl ffree’+KvcoVctl
Σ
VCO VCO
ffree’ = ffree+KvcoVoff
monitor ∆Φ and
continuously adjust
Voff until ∆Φ=0
+ output signal at fout
−
(fout=Nfref at
input signal steady state)
at fref Voff
Kpd∆Φ
Kpd Σ
∆Φ = Φref-Φout/N
phase ffree’ VCO
detector
N
frequency
divider
integral
phase
detector In steady state,
Kpd,I ∆Φ dt Voff = (fout-ffree)/KvcoKpd
∆Φ Kpd,I dt
output signal at fout
(fout=Nfref at
input signal steady state)
at fref Voff
Kpd∆Φ
Kpd Σ
∆Φ = Φref-Φout/N
phase ffree’ VCO
detector
In steady state,
∆Φ = 0 N
frequency
divider
In steady state,
∆Φ = 0 N
zero at
steady state 2πfot
Kpd,I dt
2πfreft+Φref + Vctl + 2πfout t+Φout
+
+ Σ Σ 2πKvco dt Σ
- +
Kpd
2πfout/N t+Φout/N
1/N
zero at
steady state
Kpd,I dt
2πfreft+Φref + Vctl 2πfout t+Φout
+ Σ Σ 2πKvco dt
- +
Kpd
2πfout/N t+Φout/N
1/N
Kpd,I
s
φref(s) + vctl(s) 2πKvco φout(s)
+ Σ Σ
s
- +
Kpd
φout(s)/N
1/N
p1 > 2πKpdKvco/N
Kpd,I more poles can be used
s
φref(s) + vctl(s) 1 Vctl 2πKvco φout(s)
+ Σ Σ
1+s/p1 s
- +
Kpd
φout(s)/N
1/N
Tref
reference
iout reference
iout
+1 tri-state tri-state
phase phase
reference
-1 divider o/p
detector + divider o/p
detector
+
R1 proportional R1
∆Φ = Φref-Φdiv proportional
output
+1 + integral
divider o/p -
output
-1 C1
reference
iout
tri-state
+Icp phase
pdout -
divider o/p
detector +
-Icp C1 integral
output
proportional +IcpR
output
-
-IcpR
integral
slope=Icp/C
output
Vdd
Icp
1 QA (UP)
D Q
A
ref RST iout
+
B RST R1
div proportional
QB (DN) + integral
D Q output
1
C1
Icp -
1
D Q CLK Q
CLK RST
CLK S Q Q
R Q
Q S RESET
Q R
Tref Tref
+1 +1
A -1
A -1
+1 +1
B B
-1 -1
+1 +1
QA QA
+1 +1
QB QB
QA and QB
∆Φ = Φref-Φdiv
simultaneously
on
A leading B A lagging B
B RST QA
div QB
QB (DN)
D Q Trst
1 Icp+δIcp/2
Itop
Icp-δIcp/2 Icp-δIcp/2
Ibot
C1
iout
-δIcp
(zero average)
Σn ancos(2πnfreft+αn) ("error")
Kpd,I dt
2πfout/N t+Φout/N
1/N
p1 > 2πKpdKvco/N
Kpd,I more poles can be used
s
φref(s) + vctl(s) 1 Vctl 2πKvco φout(s)
+ Σ Σ
1+s/p1 s
- +
Kpd
φout(s)/N
1/N
Vdd
Icp
1 QA (UP)
D Q
for two
A
ref RST iout extra poles
B RST R1 R2
div
QB (DN)
D Q
1
C1 C2 C3
Icp
for one
extra pole
φout/N
1/N
ωu,loop z1
s
L(s) = 1+
s s z1
2πKpd Kvco Icp RKvco
ωu,loop = =
N N
Kpd,I 1
z1 = =
Kpd RC
φout (s) 1 + s/z1
= N
φref (s) 1 + s/z1 + s2 /z1 ωu,loop
φout (s) N s/z1
=
Vnc (s) Kpd 1 + s/z1 + s2 /z1 ωu,loop
φout (s) s2 /z1 ωu,loop
=
φvco (s) 1 + s/z1 + s2 /z1 ωu,loop
L(s) 1 + s/z1
=
1 + L(s) 1 + s/z1 + s2 /z1 ωu,loop
−5
1/N|φout/φref| [dB]
1
−10
0
−15 −1 −3 −2 −1 0
10 10 10 10
−20 ζ=4.08
ζ=0.3162
ζ=1
−25 −3 −2 −1 0 1
10 10 10 10 10
ω/ω
u,loop
20
10
Magnitude response [dB]
−10
−20
−30
−40
−50 φ /φ
out ref
φ /v *1V
out nc
−60
φ /φ
out vco
−70 −2 −1 0 1 2
10 10 10 10 10
f/f
u,loop
(Example parameters:
N = 10, z1 = 0.1ωu,loop , N/Kpd = 2πKvco /ωu,loop = 25 V−1 )
|φout /φref |: Lowpass with a dc gain N
|φout /vnc |: Bandpass with peak gain N/Kpd = 25 V−1
|φout /φvco |: Highpass with a high frequency gain of 1
−40
−60
−80
dBc/Hz
−100
−120
−140 reference
ref. contribution to PLL
−160 VCO
VCO contribution to PLL
Total
−180 −2 −1 0 1 2
10 10 10 10 10
f/f
u,loop
(Example parameters:
N = 10, z1 = 0.1ωu,loop , N/Kpd = 2πKvco /ωu,loop = 25 V−1 )
Reference contribution dominant below 0.1ωu,loop
VCO contribution dominant above 0.1ωu,loop
VCO contribution reduced by the loop upto ωu,loop
Charge pump and loop filter noise ignored in the above
Nagendra Krishnapura Phase locked loop frequency synthesizers
Type-II PLL: Reference input
2πKpdKvco/N
|φout/φref|
dB, closed loop gain Sφ(f) dBc/Hz
Kpd,I/Kpd
20log(N)
ω ω
pole-zero
doublet at
2πKpdKvco/N
Kpd,I/Kpd
reference oscillator
phase noise
|φout/Vctl|
dB(radians/V)
20log(N/Kpd)
ω ω
2πKpdKvco/N
2πKpdKvco/N
zero at Kpd,I/Kpd
Kpd,I/Kpd
+20dB/dec
-20dB/dec
radians/Volt
Bandpass response
Mid band gain of N/Kpd
Lower cutoff at Kpd,I /Kpd , Upper cutoff at 2πKpd Kvco /N
Nagendra Krishnapura Phase locked loop frequency synthesizers
Type-II PLL: VCO noise
vco phase noise
-30dB/dec.(1/f3)
2πKpdKvco/N
|φout/φvco|
dB Sφ(f) dBc/Hz
-20dB/dec.(1/f2)
Kpd,I/Kpd
pll phase noise
ω +20dB/dec ω
0dB
2πKpdKvco/N
Kpd,I/Kpd
+10dB/dec
N
s2
φout (s) 2π Kpd,I Kvco
=
φvco (s) N Kpd
s2 +s +1
2π Kpd,I Kvco Kpd,I
due to vco
2πKpdKvco/N ω ω
2πKpdKvco/N
Kpd,I/Kpd
Kpd,I/Kpd
due to
reference oscillator
reference
dominated vco dominated
C C
RP (GP) GP
-GN
GN ≥ GP
for sustained
oscillation
Lossless LC resonator sustains a sinusoidal voltage
indefinitely
LC resonator loss modeled using a parallel resistance Rp
Compensate the loss of a lossy LC resonator using a
parallel negative resistance √
Oscillation frequency fo = 1/2π LC
Nagendra Krishnapura Phase locked loop frequency synthesizers
LC resonator losses
L Rs,L C Rs,C
L
C
L C
RP=RP,L||RP,C
GNv
+
v -GN
-
GNv
-gm/2
-gm/2
gmv/2 gmv/2
v/2 -v/2
gm gm
Itail Itail Itail
Vdd
L
GP
-gm/2
Itail
Vdd
L vp-vn
C M1 on
M2 off
GP M1 off
vp vn M2 on
M1 M2
Itail
C C C C
GP GP GP GP
vp vn
M1 off M1 on
I/2 I/2 0 M2 on I I M2 off 0 I/2
"bias" point
I/2
vp-vn To
2I/π 2IRP/π
I/2
fundamental
driving component differential voltage
current
a b
a b
n+ p+ n+ n+
n- well n- well
p- p-
a b
a b
metal metal
Wfinger Wfinger
n+ n+ n+ n+ n+ n+ n+ n+ n+ n+
metal
Lfinger Lfinger
nMOS in n-well
Multi fingered structure to reduce gate, channel resistance
W ∼ few microns; L > Lmin to reduce parasitics
Gate contacts at both ends to further reduce resistance
Quality factor: 20+
n+ n+ n+ n+ n+ n+ n+ n+ n+
n- well
p-
ap
an
b ap an
n+ n+
n- well b
p-
0V due to symmetry
via
L RS
1 2 1 2
C1 C2
R1 R2
substrate substrate
Winding resistance
R2 L/W
Effective R2 larger due to skin √
effect
Copper: 2 µm skin depth (∝ 1/ f ) at 1 GHz
Capacitive coupling to substrate and its resistance
Inductive coupling to (resistive) substrate
Quality factors upto 15 possible, typically 8-10
Use adequate thickness and number of vias during layout
via via
output
130fF Vc 130fF
vp vn V-bias
vp vn
6.2
6.1
fvco(in GHz)
5.9
5.8
5.7
5.6
−0.5 0 0.5 1 1.5 2
Vctl (V)
−30 dB/decade
−20
Phase Noise (dBc/Hz)
−40
−60
−80
−120
−140 2 3 4 5 6 7
10 10 10 10 10 10
Frequency offset from carrier (Hz)
D Q
combinational logic
D Q
D Q
fin
fin output
P/P+1 M
fin/N
reset
N=MP+A
fin fout
2/3 2/3 2/3 2/3 2/3 Vdd
p0 p1 p2 p3 p4
2/3 2/3
Vdd
mod0 mod1
p0 p1 p0p1=11
fin
mod0 3 2 2
f1
fout
A1 Latch1 Latch2
D Q D Q
clk clk Q Fout
Fin
modout
A2
A3
Q D modin
Q D
Q clk clk
Latch4 Latch3
Pi
Behzad Razavi (editor), Monolithic Phase Locked Loops and Clock Recovery Circuits-Theory and Design,
IEEE Press, 1996.
Behzad Razavi (editor), Phase Locking in High Performance Systems-From Devices to Architectures, IEEE
Press, 2003.
Nagendra Krishnapura, “Introducing Negative Feedback with an Integrator as the Central Element,” 2012
International Symposium on Circuits and Systems (ISCAS), Seoul, South Korea, 20-23 May 2012.
Nagendra Krishnapura, “Synthesis Based Introduction to Opamps and Phase Locked Loops,” 2012
International Symposium on Circuits and Systems (ISCAS), Seoul, South Korea, 20-23 May 2012.
Marc Tiebout, Low Power VCO Design in CMOS (Springer Series in Advanced Microelectronics) , Springer
2005.
A. S. Porret et al., “Design of high-Q varactors for low-power wireless applications using a standard CMOS
process”, IEEE Journal of Solid-State Circuits, pp. 337-345, Volume 35, Issue 3, March 2000.
C. Vaucher et al., “A family of low-power truly modular programmable dividers in standard 0.35- µm CMOS
technology,” IEEE Journal of Solid-State Circuits, vol. 35, no. 7, pp. 1039-1045, July 2000.