Professional Documents
Culture Documents
Vlsi 2 Marks PDF
Vlsi 2 Marks PDF
UNIT-1
PART-A
Stuck-at fault
Bridging fault
Stuck-open fault
It is a faults in logic gates results in one of its inputs or output being fixed either a logic 0 (stuck¬at-0) or a
logic 1 (stuck-at-1).
Two faults f and g are said to be functionally equivalent, iff Zf(x) = Zg(x).
Let G be the gate with inversion i and controlling value c, whose output is sensitized to a fault f(by a test t).
6. What is redundancy?
Let Tg be the set of all tests that detect a fault g. we say that a fault f dominates the fault g iff f and g are
functionally equivalent under To.
The faulty line is permanently set to 0 or 1.The fault can be at an input or output of a gate
shorts between two or more signal lines are called as bridging faults. It can be classified into three types.
Trans Wry fault -recurring faults and it is caused by power supply fluctuation. An intermittent Fault is a
recurring (reappear on a regular basis) and it is caused by loose connection, poor design and some environmental
conditions.
PART-B
I. Disciss the types of fault models used in digital circuits at different levels of design.
2. a. Explain how gate level event driven simulation is caned out. (10) b. Explain about die delay modeis.(6)
3. Discuss on the various types of fault simulation techniques used in digital circuits.
4. Discuss on the faults in digital circuit and its modeling at various levels of IC diagram.
TEST GENERATION
PART-A
1. Mention any four methods used in test generation for combinational circuits?
Boolean Difference
D-Algorithm
PODEM — AlgoOthm
Controllability is an ability to apply test patterns to the inputs of a sub circuit via primary of the circuit.
Observability is an ability to observe Me response of a sub circuit via the primary output of the circuit.
3. Define Backtrace
The procedure for obtaining a primary input assignment given an initial objective. It is known as Backtrace.
4. Mention any two methods used M test generation for sequential circuits
To design checking experiment it is necessary to blow the initial state of the network, which is determined by
distinguish or homing sequence.
1. Initialization phase
2. State identification phase
3. Transition verification phase
The elimination of all hazards and races greatly simplifies both test generation and fault
PART-B
I. Explain 17-algoritInn and using that algorithm fuld a tem vector for the given BIM in die circuit shown in Fig. I.
2. Explain how test sequence is generated in sequential circuits using checking experiments with example.
3. Explain PODEM algorithm and using PODEM find a test vector for the fault 'X S/O' in the circuit shown in Figure
4. Explain how sequential circuits are tested using time frame expansion method.
6. Explain the following i) Ad-hoc design rules for improving testability and ii) LSSD Design rules.
UNIT-3
PART-A
2. Define Predictability?
3. List out the characteristics that influences various cost associative with testing?
Status of a device to be determined and the isolation of faults within the device to be performed quickly to
reduce both test time and cost. The cost effective development of the tests to be determine this status.
5. Define Initialization?
It is a process of bringing a sequential circuit into a known state at some known time, such as when it is
powered on or after an initialization sequence is applied.
All internal storage elements must consist of polarity hold latches. Latches can be controlled by two or more
non overlapping clocks. Clock primary inputs cannot feed the data inputs to latches, either directly or through
combinational logic. They may only feed clock inputs ti latches or primary outputs.
Flipflops and latches are more complex. Hence scan designs are expensive in terms of board or silicon area.
Some designs are not easily realizable as scan designs. Test generation costs can be significantly reduced. This can
also lead to higher fault coverage.
PART-B
4. Explain any four ad-hoc design methods used for improving the testability of digital circuits.
6. Explain about the following i) Classical scan based design and ii) LSSD design rules.
UNIT-4
2. List out the categories of test pattern generation approaches for BIST?
Deterministic testing
4. What are the methods to derive n input and m output combinational circuit?
BILBO
STUMPS
LOCST
GALPAT
WALKING 0s AND 1s
March Test
Checkboard test
It is not necessary to store either the correct response sequence or the actualresponse sequence at any test
point; only the transition counts are needed.
LFSR/SR
PART-B
2. Discuss the fault models used in memories and explain how test generation is done for embedded RAM
3. Draw the circular BIST architecture and explain how testing is done using this architecture.
5. Explain about test generation and Built in self-test for embedded RAM.