LABORATORY EXERCISE 4

CMOS Inverter Layout

Objectives
ƒ To construct the layout (device-level implementation) of the CMOS inverter.
ƒ To be acquainted with the capabilities of Electric as a layout editor tool.
ƒ To simulate the dynamic behavior of the CMOS inverter using the layout-
extracted netlist.

Introduction

Full-Custom Design Flow

The layout, which is the final design for fabrication, is the lowest abstraction level
in the design hierarchy for digital systems. It is the accurate physical representation of the
device conforming to constraints imposed by the manufacturing process, the design flow,
and the specifications as verified through simulations. A layout-extracted netlist includes
parasitic resistances and capacitances for more accurate simulations.

The stick diagram is shown in figure 1 and layout of CMOS inverter done in
ElectricTM 6.03 is shown in figure 2.

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 Figure 1

Figure 2

In this exercise, the layout of the CMOS inverter that was designed in Exercises 1
and 2 will be implemented. The trainees are strongly encouraged to compare the
simulation results obtained in Exercise 2 with the data that will be gathered in this
exercise.

Materials needed
ElectricTM 6.03 and WinSpice3 software
Computer with the following specifications:
- Intel Pentium 2 processor or higher
- 128MB RAM, 500MB HDD space
- Windows 2000 or XP

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Procedure

(a) Layout

1. Load Electric.

2. Open the library Lab_Exercise.

3. Setup Electric for layout entry. Follow instructions below on how to set the Layout
Technology and changing the Lambda Size.

Setting the Layout Technology

1. Click on Technology → Change Current Technology… from the pulldown menu.
2. Select mocmossub as the technology (you will have to scroll down to find it).
3. Click OK. The symbols in the schematic menu will change to a mocmos subset.

Changing the Lambda Size

1. Click on Technology → Change Units.
2. Change Lambda Size to 350.
3. Change Display Units to Microns.
4. Change Internal Units to Half-Millimicrons.
5. Click OK.

4. Create new facet inverter_lay in library Lab_Exercise with layout as the facet view.
Make sure that the current technology is mocmossub.

Creating a New Layout Facet

1. Click on Facets → Edit Facet.
2. Select the appropriate library.
3. Click New Facet.
4. Type the facet name that you want to create. Set the facet view to layout.
5. Click OK.

5. Layout the CMOS inverter according to the design rules given in Appendix B of the
ASTI Training Manual. Figure 2 is a sample layout of a CMOS inverter. Before
proceeding with the layout implementation, the trainees are strongly encouraged to read
the transistor layout tips given in the Appendix C of the ASTI Training Manual. Follow
instruction below on how to add Nodes and Arcs.
Note: Lp, Ln = 0.35µm; Wp = 3.2µm; Wn = 0.8µm

Adding Nodes
1. Select a node from the components menu by using the left mouse button.
2. Click on the design window.
Note: Nodes in the mocmossub components menu are the ones in blue outlines.

Adding Arcs
1. Select an arc in the components menu.
2. Choose the arc starting point by left clicking the node near the desired port. Make
sure that the desired port is highlighted before proceeding to the next step.

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3. To create the arc, right click on another node port (to connect two node ports) or
anywhere on the design window (to create an arc segment). Once an arc has been
created, the other end is highlighted.
Note: Arcs in the mocmossub components menu are the ones in red outlines.

6. Add the export pins. Label each pin properly. Follow instructions below on how to
add export pins.

Adding Export Pins

1. Select the node or arc to be exported.
2. Click on Export → Create Export….
3. Type the export name and indicate the appropriate export characteristic.

7. After doing the layout, check for any design rule violation. Click on Tools → DRC →
Hierarchical Check.

Checking the Layout for Design Rule Errors

Before proceeding to the simulation, check for any layout violations by running a
Design Rule Check (DRC). Design rules are the set of rules that must be followed
when a given design is laid out. To run a DRC, click on Tools → DRC → Hierarchical
Check.

8. If no violations are reported save the inverter layout and close its design window.

Saving the Layout

To save the layout that you created click on File → Save All Libraries from the
pulldown menu. (Using the shortcut control key Ctrl-S will also save the layout.) A
message confirming that all facets of the library has been saved will be displayed in
the message window.

(b) Simulation

9. Create new facet inverter_lay_tst with schematic as the facet view. Make sure that the
current technology is schematic, analog.

10. Click on Edit → New Facet Instance. Choose library Lab_Exercise. Select
inverter_lay{lay} from this library. Click on the design window.

11. Click on Export → Re-Export Everything. Add necessary components for

simulation such as voltage/current sources, ground, voltage/current meters and load
capacitances. Please refer to Laboratory Exercise 2 for these components.

12. Save the schematic. Create a SPICE netlist and simulate the circuit using WinSpice.
Follow instructions below on how to create a SPICE Netlist using Layout Instance.

Creating a SPICE Netlist Using the Layout Instance

1. Change the current technology to mocmossub. Notice that the symbols in the
components menu will change from a schematic set to a layout set.
2. Click on Tools → Simulation Interface → SPICE Options….

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 a. Set the File format to SPICE3 and the SPICE level to 3.
b. Check the Use Node Names option.
c. Check the Use Parasitics option.
d. Click on Use Header Cards From File. In the SPICE Model File Selection
window set the file type to All Files (*.*).
e. Browse through the folder list to locate the model file
(\\Electric\models\BSIM3v31.txt). Select the model file.
f. Click OK.
3. Before creating the SPICE netlist, make sure that all connections are checked.
Refer to Transistor Layout on the Tips in Appendix C.
4. Click on Tools → Simulation Interface →Write SPICE Deck from the pulldown menu to
create a SPICE netlist of your circuit design.
5. Add a .cir extension to the file name.
6. Click Save.

13. Complete the table below by varying the width of the PMOS transistor. Round off
your answers to two decimal places.
Note: To view and edit the inverter layout while in the inverter_lay_tst schematic, select the
inverter icon instance in the design window and press Ctrl-D. To go back to the inverter_lay_tst
schematic window, simply press Ctrl-U.

14. Repeat the above procedures for loadcap = 500fF. Complete table 3 below. Round-
off your answers to two decimal places.

15. Compare the data obtained from Exercise 2 and Exercise 4. Note down your
observation.

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16. Determine the Area of your layout following the steps below:

Area = __________________________
Determining the Area of the Layout
1. Click on Info → Measure Distance from the pulldown menu.
2. Press X on the keyboard. This key tells Electric that you are ready to specify the
starting point of your measurement.
3. Left click on the starting point of your measurement.
4. Left click on the end point of your measurement. A line appears and the value of
the
length is shown.
5. Press the Enter key when done.

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 APPENDIX B
DESIGN RULE FOR MOCMOSSUB TECHNOLOGY

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VLSILAB/ECE6525 Lab_Exercise#4 – CMOS Inverter Layout page 8
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 APPENDIX C
TIPS ON MAKING TRANSISTOR LAYOUT
Transistor Layout
1. Overlapping two nodes does not automatically connect them. This will only
generate spacing errors. Make sure to connect them first using an arc and then move
them closer as in the example below:

2. Try to move the node closer one step at a time while checking the message
window to see if a DRC error is generated. Or you can perform the DRC
independently as specified in the Layout section of this manual.

3. Checking their connectivity is the same as with the schematic. Clicking a node
should highlight all that is connected to it as in the figures below.

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4. If nodes are well connected, and there are still spacing errors, double click on the
arc connecting the nodes with the spacing error.

5. Uncheck “ends extend” (This option sizes the node / arc in proportion to the node
width).

6. Another cause of spacing errors is multiple components that are overlapping. One
can easily identify this by moving the component concerned and checking if there is
an extra component under it as in the example below.

In this case, the extra component is not connected to the other nodes and so
it generates the other spacing errors. Simply delete the extra component and run a
DRC again.

7. If there is still a spacing error, then the two nodes must be really too close. One of
the nodes should therefore be moved until the error disappears.

References:

[1] Introduction to Full-Custom Digital IC Design Flow, ASTI-VCTI OpenLab Training

Manual.
[2] J. Rabaey, A. Chandrakasan and B. Nikolic, Digital Integrated Circuits – A Design
Perspective, Prentice Hall, 2002
[3] J. Uyemura, Introduction to VLSI Circuits and Systems, John Wiley & Sons, 2002
[4] S. Kang and Y. Leblebici, CMOS Digital Integrated Circuits, 3rd. Ed., McGraw-Hill,
2002

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