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Lecture No: 13
Introduction & Construction of Multiplexers –
Basic 2 to1– 4 to 1 – 8 to 1 Multiplexers –
Cascading MUXs for Larger Circuit Designs 1
Intro. & Const. of Multiplexers and their related Circuits
• Demultiplexers
MP3 Player
Docking Station
D0
Laptop
MUX
D1
Sound Card Y
D2
D3
Enable
n Input
Select Lines
6
Intro. & Const. of Multiplexers and their related Circuits
A basic 2x1 multiplexer (MUX) has 2 inputs, 1 output and 1 select line
D0 D0
2x1
Y Y
D1 MUX D1
S0
Logic Circuit Diagram
D0 D 1 S0 Y S0 Y
d0 d1 0 d0 0 D0
d0 d1 1 d1 1 D1
S0
• Y=D0 for S0=0, and Y=D1 for S0=1
• Minimizing will result in: Y = S0’.D0 + S0.D1
Logic circuit Equation
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Intro. & Const. of Multiplexers and their related Circuits
D0
MUX
D1
Y
D2
D3
B A
B A Y
0 0 D0
0 1 D1
1 0 D2
1 1 D3
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Intro. & Const. of Multiplexers and their related Circuits
D1
Input
Data
D2
D3
A
Select
Line
B
Y Output
9 9
D0 D1 D2 D3 D0 D1 D2 D3 Data
Intro. & Const. of Multiplexers and their related Circuits
Faculty of Engineering - UCP
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Intro. & Const. of Multiplexers and their related Circuits
• A 4x1 MUX has 4 input lines (D0, D1, D2, D3) , 1 output Y, and 2 Select
Lines (S0, S1)
• The output for different select values is defined as:
S0S1 = 00, Y = D0
S0S1 = 01, Y = D1
S0S1 = 10, Y = D2
S0S1 = 11, Y = D3
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Intro. & Const. of Multiplexers and their related Circuits
• A basic 4X1 multiplexer (MUX) has 4 inputs, 1 output and 2 select line
Inputs Inputs
I0 I0
0
I1 4:1 I1
1
MUX Mux Y
I2 2 Y I2
Output
I3 3 I3
S1 S0
S1 S 0
Block Diagrams for 4X1 MUX
select select
I0 I1 I2 I3 S1 S0 Y S1 S0 Y
d0 d1 d2 d3 0 0 d0 0 0 I0
d0 d1 d2 d3 0 1 d1 0 1 I1
d0 d1 d2 d3 1 0 d2 1 0 I2
d0 d1 d2 d3 1 1 d3 1 1 I3
Truth table for a 4-to-1 multiplexer 13
Intro. & Const. of Multiplexers and their related Circuits
I0 I0
I1 I1
Y Y
I2 I2
I3 I3
0 1 2 3
2-to-4
Decoder
S1 S0 S1 S0
S1 S0 15
Intro. & Const. of Multiplexers and their related Circuits
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Intro. & Const. of Multiplexers and their related Circuits
A0
• A MUX for two 4-bit
A1
numbers.
A2 Y0
• Has a 4-bit output and a QUAD
A3 Y1
single select line
B0 2X1 Y2
• Y = A If S0 = 0
B1 MUX Y3
• Y = B if S0 = 1 B2
B3
S0
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Intro. & Const. of Multiplexers and their related Circuits
A0 2x1 A1 2x1
Y0 Y1
B0 MUX B1 MUX
S0 S0
A2 2x1 A3 2x1
Y2 Y3
B2 MUX B3 MUX
S0 S0
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Intro. & Const. of Multiplexers and their related Circuits
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Intro. & Const. of Multiplexers and their related Circuits
its minterms
Example 1: Implement F(A,B,C)=∑(1,2,6,7) using MUXes
Solution1: We can use a MUX with the number of select lines
equal to the number of input variables of the function. Since this
function has 3 input variables, it will require 3 select lines, i.e.
an 8x1 MUX A B C F
0 0 0 0
0 0 1 1
0 1 0 1
F(A,B,C)=∑(1,2,6,7)
0 1 1 0
1 0 0 0
1 0 1 0
1 1 0 1
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1 1 1 1
Intro. & Const. of Multiplexers and their related Circuits
F(A,B,C)=∑(1,2,6,7)
A B C F D0
0 0 0 0 D1
0 0 1 1 D2
0 1 0 1 D3
0 1 1 0 F
D4
1 0 0 0
D5
1 0 1 0 S
D6
S1 0
1 1 0 1 S2
1 1 1 1 D7
A B C
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Intro. & Const. of Multiplexers and their related Circuits
F(A,B,C)=∑(1,2,6,7)
A B C F 0 D0
0 0 0 0 1 D1
0 0 1 1 1 D2
0 1 0 1 0 D3
0 1 1 0
0
F
D4
1 0 0 0
0 D5
1 0 1 0 S
1 D6
S1 0
1 1 0 1 S2
1 D7
1 1 1 1
A B C
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Intro. & Const. of Multiplexers and their related Circuits
A S1, B S0
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Intro. & Const. of Multiplexers and their related Circuits
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Intro. & Const. of Multiplexers and their related Circuits
A B C F
0 0 0 0
F=C F(A,B,C)=∑(1,2,6,7)
0 0 1 1
0 1 0 1 C D0
F = C’ C’
0 1 1 0 D1
F
0 D2
1 0 0 0 S1 S0
F=0 1 D3
1 0 1 0
1 1 0 1 A B
F=1
1 1 1 1
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Intro. & Const. of Multiplexers and their related Circuits
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Intro. & Const. of Multiplexers and their related Circuits
0 0 0 0 0 F=D
0 0 0 1 1
F(A,B,C,D)=∑(1,3,4,11,12,13,14,15)
0 0 1 0 0 F=D
0 0 1 1 1
0 1 0 0 1 F = D’ D D0
0 1 0 1 0 D1
0 1 1 0 0 F=0 D2
0 1 1 1 0 8x1 F
0 D3
1 0 0 0 0 F=0 D4 MUX
1 0 0 1 0
D5
1 0 1 0 0 F=D
1 D6
1 0 1 1 1
D7 S2 S1 S0
1 1 0 0 1 F=1
1 1 0 1 1
1 1 1 0 1 F=1
1 1 1 1 1 A B C 27
Intro. & Const. of Multiplexers and their related Circuits
Faculty of Engineering - UCP
28
Intro. & Const. of Multiplexers and their related Circuits
Multiplexer Expansion 0 0
Faculty of Engineering - UCP
1 1 4x1
- 8x1 Mux by two 4x1 Muxes 2 2 mux Y
& one 2x1 Mux 3 3
S0 S1
0
- 64x1 by four 16x1 & one 2x1
4x1? mux Y
4 0 1
5 1 4x1 S0
- 8x1 by two 4x1 with Enable
6 2 mux Y
and tri-state output? 7 3
S0 S1
S0 S1 S2 29
Intro. & Const. of Multiplexers and their related Circuits
Select
Enable
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